Xilinx buys high-level synthesis EDA vendor - EE Times

SAN FRANCISCO—Programmable logic vendor Xilinx Inc. Monday (Jan. 31) said it acquired high-level synthesis vendor AutoESL Design Technologies Inc. Financial terms of the deal were not disclosed.

Xilinx (San Jose, Calif.) said expanding its technology foundation and product portfolio to include high-level synthesis would enable the company to serve a broader base of companies where system architects and hardware designers are accustomed to designing at a higher level of abstraction in C, C++ and System C. Most of AutoESL's 25 employees located in Cupertino, Calif. and Beijing will be joining Xilinx, the company said.

Tom Feist, senior marketing director at Xilinx, said the acquisition is part of a strategy by Xilinx to grow the leading programmable logic vendor at the expense of competing products like digital signal processors, where designers are accustomed to designing at a higher level of abstraction.
“There are a finite number of people out there who do VHDL and Verilog,” Feist said. “High-level synthesis doesn't completely solve that problem, but you can develop a system with far fewer people who are the RTL guys.”

High-level synthesis tools have been used for about 20 years, mostly for ASIC design. But despite the promise of high-level synthesis for improving the efficiency of the design flow, the technology has yet to be adopted on a large scale.

Xilinx plans to make AutoESL's technology available to Xilinx customers as an option to Xilinx' ISE design suite.

Feist said Xilinx has been investing in high-level synthesis companies for more than 10 years. Prior to the acquisition of AutoESL, Xilinx had been an investor in the firm through its technology growth fund, Feist said. He added that Xilinx also invested in other high-level synthesis startups, including Synfora Inc., which was acquired by Synopsys Inc. last year.

“Over the years we've done a large investment out of the Xilinx venture fund out of the startups,” Feist said. “We spent over $10 million in investments trying to nurture these companies to get the technology to the place where it would get the results someone was looking for.”

In 2006, Xilinx launched an electronic system level initiative with a goal to help the industry improve quality of results, simplify and abstract design flows, establish interoperability and improve embedded processing flows.

Feist noted that there has been some skepticism that high-level synthesis would ever achieve mass adoption. But, he said, “It's not that we didn't believe in the promise.” Instead, Feist said, the question has been about whether the technology was mature enough to address the actual needs of the end user.

Last year, Xilinx commissioned a study by independent consulting firm BDTI Inc. to evaluate high-level synthesis tool offerings. That study found that high-level synthesis tools for FPGA design deliver excellent results and are easy to use, but do not fully abstract users from the FPGA RTL tool flow.

Jeff Bier, founder and president of BDTI, said in an article published by Xilinx' Xcell Journal magazine last year that demanding applications implemented in handwritten RTL code on an FPGA have historically typically achieved relatively good quality of results but poor productivity, while applications implemented on DSP processors provided good productivity but relatively poor quality of result.

“Development time has been a key impediment for many system designers trading off the use of a programmable DSP processor vs. an FPGA,” Bier said.

More than 25 Xilinx customers and Alliance Program members have adopted AutoESL’s flagship high level synthesis tool, AutoPilot, Xilinx said.  

The AutoPilot high level synthesis tool is optimized for Xilinx FPGA architectures and intelligently generates register transfer-level RTL code that produces the best possible quality of results to meet throughput, power, area and timing design goals, according to Xilinx. It also reduces verification time by orders of magnitude due the advantage of working at a higher level of abstraction in C, C++ or SystemC, Xilinx said.

With high level synthesis, embedded designers using Xilinx’s Extensible Processing Platform will be able to more seamlessly partition designs between the ARM Cortex-A9 MPCore processor and the programmable logic, according to Xilinx. The combination of AutoPilot and Xilinx' ISE Design Suite will enable system architects, hardware designers and, eventually, embedded software developers to apply a combination of serial and parallel processing to address system requirements, Xilinx said.

In the first half of 2011, a new Xilinx-only version of AutoPilot will be available to customers, Xilinx said. In the future, AutoPilot will be an option for the company’s ISE Design Suite software, Xilinx said.  

The AutoESL acquisition is Xilinx' first major acquisition of an EDA company in five years. In January 2006 Xilinx bought Feist's former company, Matlab-to-RTL DSP synthesis firm Accelchip

Dylan McGrath

Dylan McGrath is the executive editor of EE Times. With over 20 years experience covering the electronics and semiconductor industry, Dylan has at various times focused on consumer electronics, foundries, EDA, programmable logic, memory, and other specialty areas.