[PDF] Ray Tracing on the Cell Processor | Semantic Scholar

This work describes an optimised ray tracing kernel and parallelisation strategies, varying the workload distribution statically and dynamically, and achieves a maximum speedup multiplier of 35.97 on an 8 × 8 networked processor array using a NoC as the interconnect.

The trend in chip-multi-processors for the next several years is for on-chip FLOPS to grow much faster than bandwidth to off-chip DRAM, which suggests that substantial reductions in memory bandwidth requirements would be possible by designing algorithms that do a better job of scheduling ray traversals in a coherent fashion for divergent secondary rays.

The architecture and ASIC implementations of the DRPU design (dynamic ray processing unit) that provides similar capabilities as current GPUs are described and an FPGA prototype clocked at 66 MHz achieves higher ray tracing performance than CPU-based rays even on a modern multi-GHz CPU.