semanticscholar.org

High Density Interconnect Processes for Panel Level Packaging | Semantic Scholar

@article{Ostmann2018HighDI,
  title={High Density Interconnect Processes for Panel Level Packaging},
  author={Andreas Ostmann and Friedrich-Leonhard Schein and Michael Dietterle and Marc Kunz and Klaus-D. Lang},
  journal={2018 7th Electronic System-Integration Technology Conference (ESTC)},
  year={2018},
  pages={1-5},
  url={https://api.semanticscholar.org/CorpusID:54214952}
}

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Package (3D SIP) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for 3D SIPs with chips embedded into an organic laminate matrix…

5 Citations

6 References

Fan-Out Panel-Level Packaging (FOPLP)

J. Lau

Engineering, Materials Science

2018

All previously mentioned fan-out technologies are using the round 200 or 300 mm wafers as the temporary carriers for making the molds, RDLs, etc. (This is because of the existing equipment for…