Improving processor efficiency by statically pipelining instructions | Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Abstract
A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.
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Published In
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
June 2013
184 pages
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 25 October 2018
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LCTES '13 Paper Acceptance Rate 16 of 60 submissions, 27%;
Overall Acceptance Rate 116 of 438 submissions, 26%
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- Davis BBaird RGavin PSjälander MFinlayson IRasapour FCook GUh GWhalley DTyson GIyer RGarg S(2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
- Baird RGavin PSjälander MWhalley DUh G(2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureACM SIGPLAN Notices10.1145/2808704.275495250:5(1-10)Online publication date: 4-Jun-2015
- Baird RGavin PSjälander MWhalley DUh GNoh SFischmeister SXue J(2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureProceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM10.1145/2670529.2754952(1-10)Online publication date: 4-Jun-2015
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