Instruction scheduling, the Glossary

Table of Contents

1. 23 relations: Agner Fog, AIDA64, Basic block, Code generation (compiler), Computer science, Directed acyclic graph, Directed graph, GNU Compiler Collection, Hazard (computer architecture), Instruction pipelining, Instruction unit, Instruction-level parallelism, List scheduling, LLVM, Optimizing compiler, Out-of-order execution, Pipeline stall, Predication (computer architecture), Register allocation, Software pipelining, Topological sorting, Trace scheduling, X86.

Agner Fog

Agner Fog is a Danish evolutionary anthropologist and computer scientist.

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AIDA64

AIDA64 is a system information, diagnostics, and auditing application developed by FinalWire Ltd (a Hungarian company) that runs on Windows, Android, iOS, ChromeOS, Windows Phone, Sailfish OS, Ubuntu Touch and Tizen operating systems.

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Basic block

In compiler construction, a basic block is a straight-line code sequence with no branches in except to the entry and no branches out except at the exit.

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Code generation (compiler)

In computing, code generation is part of the process chain of a compiler and converts intermediate representation of source code into a form (e.g., machine code) that can be readily executed by the target system.

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Computer science

Computer science is the study of computation, information, and automation.

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Directed acyclic graph

In mathematics, particularly graph theory, and computer science, a directed acyclic graph (DAG) is a directed graph with no directed cycles.

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Directed graph

In mathematics, and more specifically in graph theory, a directed graph (or digraph) is a graph that is made up of a set of vertices connected by directed edges, often called arcs.

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GNU Compiler Collection

The GNU Compiler Collection (GCC) is a collection of compilers from the GNU Project that support various programming languages, hardware architectures and operating systems.

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Hazard (computer architecture)

In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results.

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Instruction pipelining

In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor.

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Instruction unit

The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU).

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Instruction-level parallelism

Instruction-level parallelism (ILP) is the parallel or simultaneous execution of a sequence of instructions in a computer program.

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List scheduling

List scheduling is a greedy algorithm for Identical-machines scheduling.

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LLVM

LLVM is a set of compiler and toolchain technologies that can be used to develop a frontend for any programming language and a backend for any instruction set architecture.

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Optimizing compiler

An optimizing compiler is a compiler designed to generate code that is optimized in aspects such as minimizing program execution time, memory use, storage size, and power consumption. Instruction scheduling and optimizing compiler are compiler optimizations.

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Out-of-order execution

In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted.

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Pipeline stall

In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard.

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Predication (computer architecture)

In computer architecture, predication is a feature that provides an alternative to conditional transfer of control, as implemented by conditional branch machine instructions.

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Register allocation

In compiler optimization, register allocation is the process of assigning local automatic variables and expression results to a limited number of processor registers. Instruction scheduling and register allocation are compiler optimizations.

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Software pipelining

In computer science, software pipelining is a technique used to optimize loops, in a manner that parallels hardware pipelining. Instruction scheduling and software pipelining are compiler optimizations.

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Topological sorting

In computer science, a topological sort or topological ordering of a directed graph is a linear ordering of its vertices such that for every directed edge (u,v) from vertex u to vertex v, u comes before v in the ordering.

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Trace scheduling

Trace scheduling is an optimization technique developed by Josh Fisher used in compilers for computer programs. Instruction scheduling and Trace scheduling are compiler optimizations.

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X86

x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088.

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References

[1] https://en.wikipedia.org/wiki/Instruction_scheduling

Also known as Basic block scheduler, Basic block scheduling, Cold scheduler, Cold scheduling, Cold scheduling algorithm, Global scheduler, Global scheduling, Instruction reordering, Instruction scheduler, Instruction scheduling algorithm, Local scheduler, Local scheduling, Modulo scheduler, Modulo scheduling, Percolation scheduler, Percolation scheduling, Superblock scheduler, Superblock scheduling.