CN100339979C - Flash memory unit and manufacturing method thereof - Google Patents

A flash memory cell mainly comprises a first conductive substrate, a second conductive well, a patterned film, a second conductive doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates. The floating gates are configured on the first conductive type substrate which is not covered by the patterned film layer, and the thickness of the floating gates is larger than that of the patterned film layer. Since the floating gate has a proper thickness, the area between the floating gate and the control gate can have a larger area, thereby improving the coupling ratio of the flash memory cell.

快闪存储单元及其制造方法Flash memory unit and manufacturing method thereof

技术领域technical field

本发明涉及一种存储器元件及其制造方法，特别是涉及一种快闪存储单元(Flash memory cell)的结构及其制造方法。The invention relates to a memory element and a manufacturing method thereof, in particular to a structure of a flash memory cell (Flash memory cell) and a manufacturing method thereof.

背景技术Background technique

非挥发性存储器(Nonvolatile memory)目前多应用在各种电子元件的使用上，如储存结构数据、程序数据及其它可以重复存取的数据。而其中一种可重复存取数据的非挥发性存储器称为闪存。闪存为一种可电抹除且可编程只读存储器(Electrically Erasable Programmable Read Only Memory，EEPROM)，其具有可进行多次数据的存入、读取、抹除等动作且存入的数据在断电后也不会消失的优点，所以已成为个人计算机和电子设备所广泛采用的一种存储器元件。Nonvolatile memory (Nonvolatile memory) is currently mostly used in the use of various electronic components, such as storing structure data, program data and other data that can be accessed repeatedly. One type of non-volatile memory that can repeatedly access data is called flash memory. Flash memory is a kind of electrically erasable and programmable read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM). It has the advantage of not disappearing after power on, so it has become a memory element widely used in personal computers and electronic equipment.

图1绘示为现有一种闪存的存储单元的布局示意图。图2A至图2C绘示为图1所绘示的存储单元沿I-I’线的制造流程剖面图。而图3A绘示为图1的存储单元在图2A的步骤中沿II-II’线的剖面示意图。图3B绘示为图1的存储单元在图2B及图2C的步骤中沿II-II’线的剖面示意图。FIG. 1 is a schematic diagram of a conventional layout of a storage unit of a flash memory. 2A to 2C are sectional views of the manufacturing process of the memory cell shown in FIG. 1 along line I-I'. 3A is a schematic cross-sectional view of the memory cell of FIG. 1 along the line II-II' in the step of FIG. 2A. FIG. 3B is a schematic cross-sectional view of the memory cell of FIG. 1 along the line II-II' during the steps of FIG. 2B and FIG. 2C.

请同时参照图2A及图3A，首先在基底100上形成多条元件隔离结构102，接着再以元件隔离结构102为掩模而在基底100中形成井区104以及掺杂区106。然后，在掺杂区106上方的基底100上形成穿隧介电层(tunnelingdielectric layer)108。之后，再于穿隧介电层108上形成图案化导体层110。其中，图案化导体层110具有多个相互平行的条状图案。Please refer to FIG. 2A and FIG. 3A at the same time. First, a plurality of device isolation structures 102 are formed on the substrate 100 , and then well regions 104 and doped regions 106 are formed in the substrate 100 using the device isolation structures 102 as a mask. Then, a tunneling dielectric layer 108 is formed on the substrate 100 above the doped region 106 . Afterwards, a patterned conductor layer 110 is formed on the tunnel dielectric layer 108 . Wherein, the patterned conductor layer 110 has a plurality of parallel strip patterns.

请同时参照图2B以及图3B，在基底100与图案化导体层110上形成栅间介电层112。接着在栅间介电层112上形成导体层114。然后请同时参照图2C以及图3B，同时对导体层114、栅间介电层112以及图案化导体层110进行图案化工艺，以形成多条控制栅极(control gate)114a以及多个浮置栅极(floating gate)110a，并暴露出浮置栅极110a两侧的基底100。接着，在浮置栅极110a两侧的基底100中形成掺杂区116，以作为快闪存储单元的源极/漏极区。而掺杂区116之间的掺杂区106即成为快闪存储单元的通道区。Referring to FIG. 2B and FIG. 3B at the same time, an inter-gate dielectric layer 112 is formed on the substrate 100 and the patterned conductor layer 110 . Next, a conductive layer 114 is formed on the inter-gate dielectric layer 112 . Then please refer to FIG. 2C and FIG. 3B at the same time, and conduct a patterning process on the conductor layer 114, the inter-gate dielectric layer 112 and the patterned conductor layer 110 to form a plurality of control gates (control gate) 114a and a plurality of floating structures. gate (floating gate) 110a, and expose the substrate 100 on both sides of the floating gate 110a. Next, doping regions 116 are formed in the substrate 100 on both sides of the floating gate 110a to serve as source/drain regions of the flash memory cells. The doped region 106 between the doped regions 116 becomes the channel region of the flash memory unit.

目前的半导体技术正逐渐朝向提高集成度以及缩小元件尺寸的发展趋势。而在缩小元件尺寸的过程中，常会遭遇到许多工艺上的困难。以上述的现有快闪存储单元的工艺为例，为了增加浮置栅极110a与控制栅极114a之间所夹的面积以提高快闪存储单元的耦合率(coupling ratio)，因此在制作浮置栅极110a时，必须使其具有足够的厚度，且在元件隔离结构102上两相邻的浮置栅极110之间的距离越小越好。也就是说，图3A所绘示的图案化导体层110必须具有一定的厚度，且开口113的越小越好，因此图案化导体层110中的开口113深宽比(aspect ratio)就会很大，进而导致形成图案化导体层110的蚀刻工艺的困难度提高。The current semiconductor technology is gradually moving towards the development trend of increasing the integration level and reducing the size of the components. In the process of reducing the size of components, many process difficulties are often encountered. Taking the above-mentioned existing flash memory cell technology as an example, in order to increase the area sandwiched between the floating gate 110a and the control gate 114a to improve the coupling ratio of the flash memory cell, the floating When arranging the gate 110a, it must have sufficient thickness, and the distance between two adjacent floating gates 110 on the device isolation structure 102 should be as small as possible. That is to say, the patterned conductor layer 110 shown in FIG. 3A must have a certain thickness, and the smaller the opening 113, the better. Therefore, the aspect ratio of the opening 113 in the patterned conductor layer 110 will be very high. is large, which in turn increases the difficulty of the etching process for forming the patterned conductor layer 110 .

而且，在形成控制栅极114a以及浮置栅极110a的蚀刻工艺中，为了完全移除残留的栅间介电层112而增长蚀刻时间，也容易对元件隔离结构102造成过度蚀刻，导致元件发生漏电流的现象，进而影响元件效能。Moreover, in the etching process for forming the control gate 114a and the floating gate 110a, in order to completely remove the residual inter-gate dielectric layer 112 and increase the etching time, it is also easy to cause over-etching to the device isolation structure 102, resulting in device failure. The phenomenon of leakage current will affect the performance of the device.

发明内容Contents of the invention

因此，本发明的目的就是提供一种快闪存储单元的制造方法，以降低工艺的困难度，并提高元件的可靠性。Therefore, the object of the present invention is to provide a method for manufacturing a flash memory unit, so as to reduce the difficulty of the process and improve the reliability of the device.

本发明的另一目的是提供一种快闪存储单元，具有高耦合比，可提升存储单元的读取及抹除速度。Another object of the present invention is to provide a flash memory unit with a high coupling ratio, which can increase the reading and erasing speed of the memory unit.

本发明提出一种快闪存储单元的制造方法，此方法先提供第一导电型基底，此第一导电型基底中已形成有第二导电型井区以及多个元件隔离结构，其中这些元件隔离结构位于第二导电型井区内，并且在第一导电型基底上定义出有源区。接着，于有源区内的第二导电型井区中形成第一导电型掺杂区。之后，在第一导电型基底上形成图案化膜层，且此图案化膜层中具有多个开口，而这些开口暴露出部分的第一导电型掺杂区。The present invention proposes a method for manufacturing a flash memory unit. The method firstly provides a substrate of a first conductivity type, in which a well region of a second conductivity type and a plurality of element isolation structures have been formed, wherein the elements are isolated The structure is located in the well region of the second conductivity type, and defines an active region on the substrate of the first conductivity type. Next, a doped region of the first conductivity type is formed in the well region of the second conductivity type in the active region. Afterwards, a patterned film layer is formed on the substrate of the first conductivity type, and the patterned film layer has a plurality of openings, and these openings expose part of the doped regions of the first conductivity type.

然后，在这些开口所暴露出的第一导电型基底中形成第二导电型掺杂区，再于这些开口所暴露出的第一导电型基底上形成穿隧介电层。之后，在每一个开口内的穿隧介电层上形成一浮置栅极，然后移除部分的图案化膜层，以使其厚度小于浮置栅极的厚度。接着，在图案化膜层上形成栅间介电层，且此栅间介电层覆盖住这些浮置栅极。在栅间介电层上形成多个控制栅极，而这些控制栅极与浮置栅极重叠。Then, a doped region of the second conductivity type is formed in the substrate of the first conductivity type exposed by the openings, and then a tunneling dielectric layer is formed on the substrate of the first conductivity type exposed by the openings. Afterwards, a floating gate is formed on the tunnel dielectric layer in each opening, and then part of the patterned film layer is removed so that its thickness is smaller than that of the floating gate. Next, an inter-gate dielectric layer is formed on the patterned film layer, and the inter-gate dielectric layer covers the floating gates. A plurality of control gates are formed on the inter-gate dielectric layer, and the control gates overlap with the floating gates.

本发明先在基底上形成具有开口的图案化膜层，之后再将导体材料填入开口中，以形成浮置栅极。由此可知，本发明的快闪存储单元的工艺中并非以蚀刻工艺来形成浮置栅极，因此可避免现有在形成浮置栅极的蚀刻工艺中，因欲形成的开口深宽比太大而遭遇到的困难。In the present invention, a patterned film layer with an opening is firstly formed on the base, and then the conductor material is filled into the opening to form a floating gate. It can be seen from this that the etching process is not used to form the floating gate in the process of the flash memory cell of the present invention, so it can avoid the problem that the opening aspect ratio to be formed is too large in the existing etching process for forming the floating gate. great difficulties encountered.

本发明提出一种闪存，主要包括第一导电型基底、第二导电型井区、多个元件隔离结构、第一导电型掺杂区、图案化膜层、穿隧介电层、多个浮置栅极、栅间介电层以及多条控制栅极。其中，第一第二导电型井区与这些元件隔离结构位于第一导电型基底中，且这些元件隔离结构于第一导电型基底上定义出一有源区，而第一导电型掺杂区配置在有源区内的第二导电型井区中。图案化膜层则配置在部分的第一导电型基底上。The present invention proposes a flash memory, which mainly includes a first conductivity type substrate, a second conductivity type well region, multiple element isolation structures, a first conductivity type doped region, a patterned film layer, a tunneling dielectric layer, a plurality of floating The gate, the inter-gate dielectric layer and a plurality of control gates are arranged. Wherein, the well region of the first and second conductivity type and these element isolation structures are located in the first conductivity type substrate, and these element isolation structures define an active region on the first conductivity type substrate, and the first conductivity type doped region It is arranged in the well region of the second conductivity type in the active region. The patterned film layer is configured on part of the first conductivity type substrate.

穿隧介电层配置于未被图案化膜层所覆盖的第一导电型基底上，而这些浮置栅极配置在穿隧介电层上，且其厚度大于图案化膜层的厚度。栅间介电层配置在浮置栅极上，并覆盖住这些图案化膜层。而控制栅极则配置在栅间介电层上，并与这些浮置栅极重叠。The tunnel dielectric layer is disposed on the first conductive type substrate not covered by the patterned film layer, and the floating gates are disposed on the tunnel dielectric layer, and their thickness is greater than that of the patterned film layer. The inter-gate dielectric layer is disposed on the floating gate and covers the patterned film layers. The control gate is disposed on the inter-gate dielectric layer and overlaps with the floating gates.

由于本发明的快闪存储单元的浮置栅极的厚度并未受限于蚀刻工艺的极限，因此本发明的快闪存储单元的浮置栅极可具有较为适当的厚度，进而提高快闪存储单元的耦合率。Since the thickness of the floating gate of the flash memory unit of the present invention is not limited by the limit of the etching process, the floating gate of the flash memory unit of the present invention can have a relatively appropriate thickness, thereby improving the performance of the flash memory. Unit coupling ratio.

为让本发明的上述和其它目的、特征和优点能更明显易懂，以下配合附图以及优选实施例，以更详细地说明本发明。In order to make the above and other objects, features and advantages of the present invention more comprehensible, the present invention will be described in more detail below with reference to the accompanying drawings and preferred embodiments.

附图说明Description of drawings

图1绘示为现有一种闪存的存储单元的布局示意图。FIG. 1 is a schematic diagram of a conventional layout of a storage unit of a flash memory.

图2A至图2C绘示为图1所绘示的存储单元沿I-I’线的制造流程剖面图。2A to 2C are sectional views of the manufacturing process of the memory cell shown in FIG. 1 along line I-I'.

图3A绘示为图1的存储单元在图2A的步骤中沿II-II’线的剖面示意图。FIG. 3A is a schematic cross-sectional view of the memory cell of FIG. 1 along the line II-II' in the step of FIG. 2A.

图3B绘示为图1的存储单元在图2B及图2C的步骤中沿II-II’线的剖面示意图。FIG. 3B is a schematic cross-sectional view of the memory cell of FIG. 1 along the line II-II' during the steps of FIG. 2B and FIG. 2C.

图4绘示为本发明的一种闪存的存储单元的布局示意图。FIG. 4 is a schematic layout diagram of a storage unit of a flash memory according to the present invention.

图5A至图5D绘示为图4所绘示的存储单元沿I-I’线的制造流程剖面图。5A to 5D are cross-sectional views of the manufacturing process of the memory cell shown in FIG. 4 along line I-I'.

图6A至图6D则分别对应至图5A至图5D而绘示为图4的存储单元沿II-II’线的制造流程剖面图。FIGS. 6A to 6D correspond to FIGS. 5A to 5D respectively and are sectional views of the manufacturing process of the memory cell of FIG. 4 along the line II-II'.

图7A至图7B绘示为图4所绘示的快闪存储单元的浮置栅极沿II-II’线的制造流程剖面图。7A to 7B are cross-sectional views of the manufacturing process of the floating gate of the flash memory cell shown in FIG. 4 along the line II-II'.

图8及图9分别绘示为图4所绘示的快闪存储单元的控制栅极沿I-I’线及II-II’线的制造流程剖面图。8 and 9 are cross-sectional views of the manufacturing process of the control gate of the flash memory cell shown in FIG. 4 along line I-I' and line II-II', respectively.

图10绘示为本发明的另一种快闪存储单元的剖面示意图。FIG. 10 is a schematic cross-sectional view of another flash memory unit of the present invention.

图11A至图11C绘示为本发明的另一种快闪存储单元沿I-I’线的制造流程剖面图。FIG. 11A to FIG. 11C are cross-sectional views of the manufacturing process along line I-I' of another flash memory unit of the present invention.

图12A至图12C则分别对应图11A至图11C而绘示为本发明的另一种快闪存储单元沿II-II’线的制造流程剖面图。12A to 12C respectively correspond to FIG. 11A to FIG. 11C and are schematic cross-sectional views of another flash memory unit of the present invention along line II-II'.

简单符号说明simple notation

100：基底100: base

102、504：元件隔离结构102, 504: Component isolation structure

104：井区104: Well Area

106、116：掺杂区106, 116: doped area

108、514：穿隧介电层108, 514: tunneling dielectric layer

110、114、518、519：导体层110, 114, 518, 519: conductor layer

110a、516：浮置栅极110a, 516: floating gate

111、530、532、534：快闪存储单元111, 530, 532, 534: flash memory unit

112、520：栅间介电层112, 520: inter-gate dielectric layer

113、510、510a：开口113, 510, 510a: opening

114a、522、522a：控制栅极114a, 522, 522a: Control grids

500：n型基底500: n-type substrate

502：p型井区502: p-well area

503：有源区503: Active area

506：n型掺杂区506: n-type doped region

508：图案化膜层508: Patterned film layer

512：p型掺杂区512: p-type doped region

524：图案化光致抗蚀剂层524: Patterned photoresist layer

526：间隙壁526: spacer wall

528：牺牲层528: Sacrificial layer

具体实施方式Detailed ways

以下实施例是以第一导电型为n型，而第二导电型为p型来说明，但本领域技术人员应知，若将第一导电型置换成p型，第二导电型置换成n型，则下述实施例仍可据以实施。The following embodiments are described with the first conductivity type being n-type and the second conductivity type being p-type, but those skilled in the art should know that if the first conductivity type is replaced by p-type, the second conductivity type is replaced by n-type type, then the following embodiments can still be implemented according to.

图4绘示为本发明的一种闪存的存储单元的布局示意图。图5A至图5D绘示为图4所绘示的快闪存储单元沿I-I’线的制造流程剖面图。图6A至图6D则分别对应图5A至图5D而绘示为图4的快闪存储单元沿II-II’线的制造流程剖面图。FIG. 4 is a schematic layout diagram of a storage unit of a flash memory according to the present invention. 5A to 5D are cross-sectional views of the manufacturing process of the flash memory cell shown in FIG. 4 along line I-I'. 6A to 6D respectively correspond to FIG. 5A to FIG. 5D and are shown as cross-sectional views of the manufacturing process of the flash memory unit of FIG. 4 along line II-II'.

请同时参照图5A及图6A，首先在n型基底500上形成多条元件隔离结构504(如图6A所示)，以定义出存储器元件的有源区503，接着在有源区503内的n型基底500中形成p型井区502。其中，元件隔离结构504的形成方法例如是利用浅沟渠隔离(Shallow Trench Insulator，简称STI)法或是区域氧化(local oxidation，简称LOCOS)法。然后，在n型基底500的有源区503内的p型井区502中形成n型掺杂区506，其例如是在后续工艺中用以作为快闪存储单元的源极/漏极区。之后，在n型基底500上形成图案化膜层508，其材料例如是氧化硅。图案化膜层508中具有多个开口510，而这些开口510暴露出部分的有源区503内的n型掺杂区506。Please refer to FIG. 5A and FIG. 6A at the same time. First, a plurality of element isolation structures 504 (as shown in FIG. 6A ) are formed on the n-type substrate 500 to define the active region 503 of the memory element, and then in the active region 503 A p-type well region 502 is formed in the n-type substrate 500 . Wherein, the formation method of the device isolation structure 504 is, for example, utilizing a shallow trench isolation (Shallow Trench Insulator, referred to as STI) method or a local oxidation (local oxidation, referred to as LOCOS) method. Then, an n-type doped region 506 is formed in the p-type well region 502 in the active region 503 of the n-type substrate 500 , which is used as a source/drain region of a flash memory cell in a subsequent process, for example. Afterwards, a patterned film layer 508 is formed on the n-type substrate 500, and its material is, for example, silicon oxide. The patterned film layer 508 has a plurality of openings 510 , and these openings 510 expose a portion of the n-type doped region 506 in the active region 503 .

图案化膜层508的形成方法例如是先在n型基底500形成一层材料层(未绘示)，在一实施例中，此材料层例如是氧化硅层，而其形成方法例如是化学气相沉积(Chemical Vapor Deposition，简称CVD)法。接着再进行例如是光刻及蚀刻工艺，以形成具有多个开口510的图案化膜层508。The patterned film layer 508 is formed by, for example, first forming a layer of material (not shown) on the n-type substrate 500. In one embodiment, the material layer is, for example, a silicon oxide layer, and the formation method is, for example, chemical vapor phase Deposition (Chemical Vapor Deposition, referred to as CVD) method. Then, photolithography and etching processes are performed to form a patterned film layer 508 having a plurality of openings 510 .

请参照图5B及图6B，在开口510所暴露出的n型掺杂区506中形成p型掺杂区512，其例如是用以在后续工艺中作为快闪存储单元的通道区。而p型掺杂区512的形成方法例如是利用图案化膜层508为掩模以进行一离子掺入工艺，以便于将p型离子掺入开口510所暴露出的n型掺杂区506中。Referring to FIG. 5B and FIG. 6B , a p-type doped region 512 is formed in the n-type doped region 506 exposed by the opening 510 , which is, for example, used as a channel region of a flash memory cell in a subsequent process. The p-type doped region 512 is formed by, for example, using the patterned film layer 508 as a mask to perform an ion doping process, so that p-type ions can be doped into the n-type doped region 506 exposed by the opening 510. .

请参照图5C及图6C，在p型掺杂区512上方的n型基底500上形成穿隧介电层514，且穿隧介电层514的材料例如是氧化硅，而其形成方法例如是热氧化法(thermal oxidation)。接着，在每一开口510内的穿隧介电层514上形成浮置栅极516。Referring to FIG. 5C and FIG. 6C, a tunneling dielectric layer 514 is formed on the n-type substrate 500 above the p-type doped region 512, and the material of the tunneling dielectric layer 514 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation. Next, a floating gate 516 is formed on the tunneling dielectric layer 514 within each opening 510 .

请参照图7A及图7B，在一优选实施例中，浮置栅极516的形成方法例如是先在图案化膜层508以及n型基底500上形成导体层518(如图7A所示)，并填入开口510内，且导体层518例如是掺杂多晶硅层，而其形成方法例如是化学气相沉积。之后，再进行平坦化工艺，其例如是化学机械研磨(chemical mechanical polishing，简称CMP)工艺或是蚀刻工艺，并以图案化膜层508作为化学机械研磨终止层(CMP stop layer)或是蚀刻终止层(etch stoplayer)，以移除部分的导体层518而暴露出图案化膜层508，并形成多个浮置栅极516，如图7B所示。然后，再回蚀(etch back)图案化膜层508。由于图案化膜层508的材料与浮置栅极516的材料之间具有较高的蚀刻选择性，因此可在不损坏浮置栅极516的情况下，移除部分图案化膜层508，以使图案化膜层508的厚度小于浮置栅极516的厚度，如图5C及图6C所示。其中，浮置栅极516的厚度例如是5000埃，而图案化膜层508的厚度则例如是介于1500埃至2000埃之间。特别值得注意的是，浮置栅极516与图案化膜层508的厚度差(也就是浮置栅极516暴露在图案化膜层508的开口510外的高度)h将决定此快闪存储单元的耦合率。更进一步地来说，当h愈大时，快闪存储单元的耦合率也会愈大，则此快闪存储单元可具有优选的读取及抹除速度。Please refer to FIG. 7A and FIG. 7B. In a preferred embodiment, the method for forming the floating gate 516 is, for example, first forming a conductor layer 518 on the patterned film layer 508 and the n-type substrate 500 (as shown in FIG. 7A ), And fill in the opening 510, and the conductive layer 518 is, for example, a doped polysilicon layer, and its forming method is, for example, chemical vapor deposition. Afterwards, a planarization process is performed, such as a chemical mechanical polishing (CMP) process or an etching process, and the patterned film layer 508 is used as a chemical mechanical polishing stop layer (CMP stop layer) or an etching stop layer (etch stoplayer), to remove part of the conductor layer 518 to expose the patterned film layer 508, and form a plurality of floating gates 516, as shown in FIG. 7B. Then, the patterned film layer 508 is etched back. Due to the high etching selectivity between the material of the patterned film layer 508 and the material of the floating gate 516, part of the patterned film layer 508 can be removed without damaging the floating gate 516, so as to Make the thickness of the patterned film layer 508 smaller than the thickness of the floating gate 516 , as shown in FIG. 5C and FIG. 6C . Wherein, the thickness of the floating gate 516 is, for example, 5000 angstroms, and the thickness of the patterned film layer 508 is, for example, between 1500 angstroms and 2000 angstroms. It is particularly worth noting that the thickness difference between the floating gate 516 and the patterned film layer 508 (that is, the height of the floating gate 516 exposed outside the opening 510 of the patterned film layer 508) h will determine the flash memory cell coupling rate. Furthermore, when h is larger, the coupling rate of the flash memory cell is also larger, and the flash memory cell can have an optimal reading and erasing speed.

值得注意的是，本发明并不限定浮置栅极516的形成方法为上述工艺(如图7A至图7B所示)，本领域技术人员可以依照本发明的精神而利用其它工艺来形成图5C及图6C所绘示的浮置栅极516，惟其亦落于本发明的范围内。It should be noted that the present invention does not limit the formation method of the floating gate 516 to the above process (as shown in FIG. 7A to FIG. 7B ), and those skilled in the art can use other processes to form FIG. 5C according to the spirit of the present invention. and the floating gate 516 shown in FIG. 6C , but it also falls within the scope of the present invention.

请参照图5D及图6D，在图案化膜层508上形成栅间介电层520，并覆盖住这些浮置栅极516。其中，栅间介电层520的材料例如是氧化硅/氮化硅/氧化硅等，或是由氧化硅层或氧化硅/氮化硅层等所构成，而其形成方法例如是低压化学气相沉积(Low Pressure CVD，LPCVD)。接着，在栅间介电层520上形成控制栅极522，且这些控制栅极522实质上相互平行的(如图4所示)，以于后续工艺中作为快闪存储单元的字符线(word line)。而且，这些控制栅极522覆盖住浮置栅极516及其侧壁上的栅间介电层520。此外，若n型基底500上形成有元件隔离结构504，则控制栅极522与条状的元件隔离结构504相交，且优选的是控制栅极522垂直于元件隔离结构504，如图4所示。Referring to FIG. 5D and FIG. 6D , an inter-gate dielectric layer 520 is formed on the patterned film layer 508 to cover the floating gates 516 . Wherein, the material of inter-gate dielectric layer 520 is, for example, silicon oxide/silicon nitride/silicon oxide, etc., or is composed of silicon oxide layer or silicon oxide/silicon nitride layer, etc., and its formation method is, for example, low pressure chemical vapor phase. Deposition (Low Pressure CVD, LPCVD). Next, control gates 522 are formed on the inter-gate dielectric layer 520, and these control gates 522 are substantially parallel to each other (as shown in FIG. line). Moreover, the control gates 522 cover the floating gates 516 and the inter-gate dielectric layer 520 on their sidewalls. In addition, if the element isolation structure 504 is formed on the n-type substrate 500, the control gate 522 intersects the strip-shaped element isolation structure 504, and preferably the control gate 522 is perpendicular to the element isolation structure 504, as shown in FIG. 4 .

图8及图9分别绘示为图4所绘示的快闪存储单元沿I-I’及II-II’的部分制造流程剖面图。请参照图8及图9，控制栅极522的形成方法例如是先在栅间介电层520上形成导体层519，其材料例如是掺杂多晶硅，且导体层519的形成方法例如是化学气相沉积。然后在导体层519上形成图案化光致抗蚀剂层524，且图案化光致抗蚀剂层524覆盖住浮置栅极516。而且，图案化光致抗蚀剂层524具有多个实质上相互平行的条状图案，其形成方法例如是光刻工艺。之后，以图案化光致抗蚀剂524为掩模，进行蚀刻工艺以移除部分的导电层519。然后再移除图案化光致抗蚀剂层524，即可在栅间介电层520上形成多条控制栅极522，如图5D及图6D所示。此时即完成快闪存储单元530的工艺，而后续完成闪存的工艺为本领域技术人员所周知，在此不再赘述。FIG. 8 and FIG. 9 are sectional views of part of the manufacturing process of the flash memory unit shown in FIG. 4 along lines I-I' and II-II' respectively. Please refer to FIG. 8 and FIG. 9, the formation method of the control gate 522 is, for example, to first form a conductive layer 519 on the inter-gate dielectric layer 520, the material of which is, for example, doped polysilicon, and the formation method of the conductive layer 519 is, for example, chemical vapor phase. deposition. A patterned photoresist layer 524 is then formed on the conductor layer 519 , and the patterned photoresist layer 524 covers the floating gate 516 . Moreover, the patterned photoresist layer 524 has a plurality of strip patterns substantially parallel to each other, and its formation method is, for example, a photolithography process. Afterwards, an etching process is performed to remove part of the conductive layer 519 by using the patterned photoresist 524 as a mask. Then, the patterned photoresist layer 524 is removed to form a plurality of control gates 522 on the inter-gate dielectric layer 520 , as shown in FIGS. 5D and 6D . At this point, the process of the flash memory unit 530 is completed, and the subsequent process of completing the flash memory is well known to those skilled in the art, and will not be repeated here.

此外，在本发明的另一优选实施例中，快闪存储单元的控制栅极522a可以是位于浮置栅极516的正上方且未覆盖住浮置栅极516的侧壁，如图10所示。在此，为了增加快闪存储单元的耦合率，可以在控制栅极522a的侧壁形成间隙壁526。特别的是，间隙壁526的材料例如是导体材料，且优选的是与控制栅极522a的材料相同，也就是多晶硅材料。由此可知，控制栅极522a与间隙壁526电连接。间隙壁526的形成方法例如是先在基底上方形成一层共形导体层(未绘示)覆盖住栅间介电层520以及控制栅极522a，之后再回蚀此导体层，以使其形成间隙壁526，即完成快闪存储单元532的制作。后续的工艺即同于一般的存储器元件的工艺。In addition, in another preferred embodiment of the present invention, the control gate 522a of the flash memory unit may be located directly above the floating gate 516 and does not cover the sidewall of the floating gate 516, as shown in FIG. 10 Show. Here, in order to increase the coupling rate of the flash memory cells, spacers 526 may be formed on the sidewalls of the control gate 522a. In particular, the material of the spacer 526 is, for example, a conductive material, which is preferably the same as that of the control gate 522 a , that is, polysilicon. It can be seen from this that the control gate 522 a is electrically connected to the spacer 526 . The formation method of the spacer 526 is, for example, to form a conformal conductive layer (not shown) above the substrate to cover the inter-gate dielectric layer 520 and the control gate 522a, and then etch back the conductive layer to form The spacer 526 completes the fabrication of the flash memory unit 532 . Subsequent processes are the same as those of general memory elements.

另外，在一优选实施例中，本发明还可以在形成元件隔离结构504之后及形成p型井区502之前，先在n型基底500上形成牺牲层528(如图11A及图12A所示)，用以保护n型基底500及元件隔离结构504，使其在后续工艺(例如是蚀刻工艺)中不会受到损坏。举例来说，请同时参照图11B及图12B，形成图案化膜层508的方法例如是利用光刻及蚀刻工艺以于一材料层(未绘示)中形成开口510a。在此蚀刻工艺中，牺牲层528用来作为蚀刻终止层(etching stop layer)，以防止在形成开口510a的蚀刻工艺中过度蚀刻n型基底500及元件隔离结构504，因此可避免元件产生漏电流的问题。之后再移除部分的牺牲层528，以暴露出部分的n型基底500及元件隔离结构504。然后，再以前述的工艺完成快闪存储单元534，如图11C及图12C所示。In addition, in a preferred embodiment, the present invention can also form a sacrificial layer 528 on the n-type substrate 500 after the element isolation structure 504 is formed and before the p-type well region 502 is formed (as shown in FIG. 11A and FIG. 12A ). , used to protect the n-type substrate 500 and the device isolation structure 504 from being damaged in subsequent processes (such as etching processes). For example, please refer to FIG. 11B and FIG. 12B at the same time, the method of forming the patterned film layer 508 is, for example, using photolithography and etching processes to form an opening 510a in a material layer (not shown). In this etching process, the sacrificial layer 528 is used as an etching stop layer (etching stop layer) to prevent the n-type substrate 500 and the device isolation structure 504 from being over-etched during the etching process for forming the opening 510a, so that the device can avoid leakage current The problem. Then part of the sacrificial layer 528 is removed to expose part of the n-type substrate 500 and the device isolation structure 504 . Then, the flash memory unit 534 is completed by the aforementioned process, as shown in FIG. 11C and FIG. 12C .

以下将以图5D及图6D所绘示的快闪存储单元为例来详细说明本发明的快闪存储单元，而图中所绘示的膜层的材料已于上述实施例中说明，以下不再赘述。The following will take the flash memory cell shown in FIG. 5D and FIG. 6D as an example to describe the flash memory cell of the present invention in detail, and the material of the film layer shown in the figure has been described in the above-mentioned embodiment, and will not be described below. Let me repeat.

请再参照图5D及图6D，本发明的快闪存储单元530主要包括n型基底500、多条元件隔离结构504、n型掺杂区506、图案化膜层508、p型掺杂区512、穿隧介电层514、多个浮置栅极516、栅间介电层520以及多条控制栅极522。其中，n型基底500中已形成有p型井区502。n型掺杂区506配置在n型基底500中的p型井区502内，以于后续工艺中作为快闪存储单元530的源极/漏极区。图案化膜层508配置在n型基底500上，而p型掺杂区512则系是配置在未被图案化膜层508所覆盖的n型基底500中，以于后续工艺中作为快闪存储单元530的通道区。穿隧介电层514则配置在p型掺杂区512上方的n型基底500上。Please refer to FIG. 5D and FIG. 6D again. The flash memory unit 530 of the present invention mainly includes an n-type substrate 500, a plurality of element isolation structures 504, an n-type doped region 506, a patterned film layer 508, and a p-type doped region 512. , a tunneling dielectric layer 514 , a plurality of floating gates 516 , an inter-gate dielectric layer 520 and a plurality of control gates 522 . Wherein, a p-type well region 502 has been formed in the n-type substrate 500 . The n-type doped region 506 is disposed in the p-type well region 502 in the n-type substrate 500 to serve as a source/drain region of the flash memory unit 530 in subsequent processes. The patterned film layer 508 is disposed on the n-type substrate 500, and the p-type doped region 512 is disposed in the n-type substrate 500 not covered by the patterned film layer 508 to serve as a flash memory in subsequent processes. Access area of unit 530. The tunnel dielectric layer 514 is disposed on the n-type substrate 500 above the p-type doped region 512 .

浮置栅极516配置在穿隧介电层514上，且浮置栅极516的厚度大于图案化膜层508的厚度。在一优选实施例中，浮置栅极516的厚度例如是5000埃，而图案化膜层508的厚度例如是1500埃至2000埃之间。栅间介电层520配置在图案化膜层508上，并覆盖住浮置栅极516。控制栅极522则实质上相互平行地配置在栅间介电层520上，并覆盖住浮置栅极516及其侧壁。The floating gate 516 is disposed on the tunneling dielectric layer 514 , and the thickness of the floating gate 516 is greater than the thickness of the patterned film layer 508 . In a preferred embodiment, the thickness of the floating gate 516 is, for example, 5000 angstroms, and the thickness of the patterned film layer 508 is, for example, between 1500 angstroms and 2000 angstroms. The inter-gate dielectric layer 520 is disposed on the patterned film layer 508 and covers the floating gate 516 . The control gates 522 are disposed substantially parallel to each other on the inter-gate dielectric layer 520 and cover the floating gate 516 and its sidewalls.

在本发明的另一优选实施例中，控制栅极522a(见图10)还可以是配置在浮置栅极516的正上方。换言之，控制栅极522a并未覆盖住浮置栅极516的侧壁。而且，控制栅极522a以及浮置栅极516的侧壁上配置有间隙壁526，如图10所示。其中间隙壁526的材料例如是导体材料，而在一优选实施例中，间隙壁526的材料例如是多晶硅。In another preferred embodiment of the present invention, the control gate 522 a (see FIG. 10 ) can also be disposed directly above the floating gate 516 . In other words, the control gate 522 a does not cover the sidewall of the floating gate 516 . Furthermore, spacers 526 are disposed on the sidewalls of the control gate 522 a and the floating gate 516 , as shown in FIG. 10 . The material of the spacer 526 is, for example, a conductive material, and in a preferred embodiment, the material of the spacer 526 is, for example, polysilicon.

再者，在本发明的又一实施例中，图案化膜层508与n型基底500之间还可以配置有牺牲层528(如图11C及图12C所示)，用以保护n型基底500及元件隔离结构504，使其在工艺(例如是蚀刻工艺)中不会受到损坏。另外，在此实施例中，浮置栅极516配置于穿隧介电层514上，并延伸至部分的元件隔离结构504上，如图12C所示。Furthermore, in another embodiment of the present invention, a sacrificial layer 528 (as shown in FIG. 11C and FIG. 12C ) may also be disposed between the patterned film layer 508 and the n-type substrate 500 to protect the n-type substrate 500 And the device isolation structure 504, so that it will not be damaged during the process (eg, etching process). In addition, in this embodiment, the floating gate 516 is disposed on the tunneling dielectric layer 514 and extends to part of the device isolation structure 504 , as shown in FIG. 12C .

本发明的快闪存储单元的制造方法先在基底上形成具有开口的图案化膜层，之后再将导体材料填入开口中，以形成浮置栅极。由此可知，本发明的快闪存储单元的工艺中并非以蚀刻工艺来形成浮置栅极，因此可避免现有在形成浮置栅极的蚀刻工艺中，因欲形成的开口深宽比太大而遭遇到的困难。而且，本发明在一优选实施例中更在基底上形成一层牺牲层，用以保护基底及元件隔离结构在形成图案化膜层的蚀刻工艺中不会受到损坏。由此可知，本发明可避免现有工艺中因对元件隔离结构过度蚀刻而导致元件产生漏电流的问题。总而言之，本发明的快闪存储单元的制造方法可以降低工艺困难度，并且提高元件的可靠性。In the manufacturing method of the flash memory unit of the present invention, a patterned film layer with an opening is firstly formed on the substrate, and then a conductor material is filled into the opening to form a floating gate. It can be seen from this that the etching process is not used to form the floating gate in the process of the flash memory cell of the present invention, so it can avoid the problem that the opening aspect ratio to be formed is too large in the existing etching process for forming the floating gate. great difficulties encountered. Moreover, in a preferred embodiment of the present invention, a sacrificial layer is further formed on the substrate to protect the substrate and the device isolation structure from being damaged during the etching process for forming the patterned film layer. It can be seen that the present invention can avoid the problem of element leakage current caused by over-etching the element isolation structure in the prior art. In a word, the manufacturing method of the flash memory unit of the present invention can reduce the process difficulty and improve the reliability of the device.

本发明的快闪存储单元可依实际所需而决定浮置栅极被控制栅极所覆盖的厚度，以使快闪存储单元具有较高的耦合率，进而提高快闪存储单元的读取及抹除速度。In the flash memory unit of the present invention, the thickness of the floating gate covered by the control gate can be determined according to actual needs, so that the flash memory unit has a higher coupling rate, thereby improving the read and write performance of the flash memory unit. Erase speed.

虽然本发明以优选实施例揭露如上，然而其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作些许的更动与润饰，因此本发明的保护范围应当以后附的权利要求所界定者为准。Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the appended claims.