CN100511172C - Inter-board transparent transmission bus test device and method thereof - Google Patents

本发明公开了一种板间透传总线的测试装置及方法，一种板间透传总线的测试装置，其中，包括：主控单元、板间连接器单元和环境板存储单元，连接有被测总线单元；所述的主控单元用于发起透传总线测试命令、控制被测总线单元向所述环境板存储单元写数据、所述被测总线单元从所述环境板存储单元读取数据、并对写读数据的一致性进行判断并对测试结果进行分析和故障定位，给出测试结论；所述板间连接器单元用于构成所述被测总线单元和所述环境板存储单元之间的连接通道；所述环境板存储单元用于提供与所述被测总线单元匹配的总线接口和存储介质。本发明测试装置及方法成本低，实现简易，工作稳定可靠。

The invention discloses a test device and method for an inter-board transparent transmission bus, a test device for an inter-board transparent transmission bus, which includes: a main control unit, an inter-board connector unit and an environment The bus unit under test; the main control unit is used to initiate a transparent transmission bus test command, control the bus unit under test to write data to the storage unit of the environmental board, and the bus unit under test to read data from the storage unit of the environmental board , and judge the consistency of the write and read data, analyze the test results and locate the fault, and give the test conclusion; the inter-board connector unit is used to form the connection between the measured bus unit and the environment board storage unit The connecting channel between them; the environment board storage unit is used to provide a bus interface and a storage medium matching the bus unit under test. The test device and method of the invention have low cost, simple implementation and stable and reliable operation.

一种板间透传总线的测试装置及方法 A test device and method for an inter-board transparent transmission bus

技术领域 technical field

本发明涉及一种电子和通信系统中的单板测试装置及方法，具体的说，涉及的是一种针对板间透传的板级总线，比如SPI、I2C、并行总线等的功能测试装置及方法。The present invention relates to a single-board test device and method in an electronic and communication system, specifically, to a board-level bus for inter-board transparent transmission, such as a functional test device for SPI, I2C, parallel bus, etc. method.

背景技术 Background technique

在现有技术的电子和通信领域中，经常出现单板上的总线信号通过各类接口透传到另外一块单板或子卡上的情况，在单板功能测试中需要检测批量生产的单板上这类透传总线信号相关的功能芯片是否正常，以及信号所经过的驱动和连接器是否正常。In the electronic and communication fields of the prior art, it often occurs that the bus signal on a single board is transparently transmitted to another single board or sub-card through various interfaces, and it is necessary to detect the mass-produced single board in the single board function test Whether the function chip related to this kind of transparent transmission bus signal is normal, and whether the driver and connector that the signal passes through are normal.

透传总线的功能测试装置一般包括短路、开路、接口时序等方面的测试，通常的实现方式有以下两种：The functional test device of the transparent transmission bus generally includes tests of short circuit, open circuit, interface timing, etc. There are usually two implementation methods:

一是将每根总线信号线当成单独的I/O来测试，但该方案存在如下缺点：测试环境需要提供支持I/O读写的硬件功能模块，在总线信号线数量较多的情况下，所需的I/O数量很多，成本较高，操作繁琐；而且无法实现总线的时序测试。One is to test each bus signal line as a separate I/O, but this solution has the following disadvantages: the test environment needs to provide hardware function modules that support I/O reading and writing. In the case of a large number of bus signal lines, The required I/O quantity is large, the cost is high, and the operation is cumbersome; and the timing test of the bus cannot be realized.

二是在测试环境板上的EPLD设计一个与被测单板的总线对应的接口，测试时通过被测单板与EPLD之间进行数据收发并判断数据一致性来完成。中国专利号为CN99127441、申请人是国际商业机器公司的中国专利“生产测试接口接至全局串行总线的方法和装置”，是一种将一个生产测试接口接至一个诸如互联集成电路(I2C)总线之类的全局串行总线的方法和装置，其输入/输出缓存逻辑对需传送给和来自全局串行总线的数据进行缓存；与输入/输出缓存逻辑连接的从控接口逻辑接收来自输入/输出缓存逻辑的数据和将数据发送给输入/输出缓存逻辑；与输入/输出缓存逻辑和从控接口逻辑连接的从控控制器对与输入/输出缓存逻辑的数据交换进行调步；接在输入/输出缓存器和全局串行总线之间的差错检测逻辑用来检测差错状况。The second is to design an interface corresponding to the bus of the single board under test on the EPLD on the test environment board, and complete the test by sending and receiving data between the single board under test and the EPLD and judging the data consistency. The Chinese patent No. is CN99127441, and the applicant is International Business Machines Corporation's Chinese patent "Method and device for connecting a production test interface to a global serial bus", which is a method and device for connecting a production test interface to an interconnected integrated circuit (I2C) The method and device of the global serial bus such as bus, its input/output cache logic buffers the data that needs to be sent to and from the global serial bus; Output cache logic data and send data to I/O cache logic; slave controller connected to I/O cache logic and slave interface logic to pace data exchange with I/O cache logic; connected to input The error detection logic between the / output buffer and the global serial bus is used to detect the error condition.

该专利思路基本与前面提到的方案二相同，主要增加了对输入/输出数据的缓冲和调整功能，但其缺点是设计相对复杂，有一定的逻辑编码和调试的工作量和难度，另外需要增加逻辑芯片，成本相对比较高，而且在实际的应用中，可能还会由于逻辑设计不当，造成测试的不稳定。The idea of this patent is basically the same as the aforementioned scheme 2, which mainly adds buffering and adjustment functions for input/output data, but its disadvantage is that the design is relatively complicated, and there is a certain amount of work and difficulty in logic coding and debugging. The cost of adding logic chips is relatively high, and in actual applications, the test may be unstable due to improper logic design.

发明内容 Contents of the invention

本发明的目的在于提供一种板间透传总线的测试装置及方法，对板间透传的板级总线进行测试，以快速的实现对SPI、I2C、并行总线等在板间透传情况下的接口测试。The object of the present invention is to provide a test device and method for inter-board transparent transmission bus, to test the inter-board transparent transmission board-level bus, to quickly realize the inter-board transparent transmission of SPI, I2C, parallel bus, etc. interface testing.

本发明的技术方案如下：Technical scheme of the present invention is as follows:

一种板间透传总线的测试装置，其中，包括：主控单元、板间连接器单元和环境板存储单元，连接有被测总线单元；A test device for an inter-board transparent transmission bus, including: a main control unit, an inter-board connector unit, and an environment board storage unit, connected to a bus unit to be tested;

所述的主控单元用于发起透传总线测试命令、控制被测总线单元向所述环境板存储单元写数据、所述被测总线单元从所述环境板存储单元读取数据、并对写读数据的一致性进行判断并对测试结果进行分析和故障定位，给出测试结论；The main control unit is used to initiate a transparent transmission bus test command, control the bus unit under test to write data to the storage unit of the environmental board, and the bus unit under test to read data from the storage unit of the environmental board, and write data to the storage unit of the environmental board. Judging the consistency of the read data, analyzing the test results and locating the fault, and giving the test conclusion;

所述板间连接器单元用于构成所述被测总线单元和所述环境板存储单元之间的连接通道；The inter-board connector unit is used to form a connection channel between the bus unit under test and the environment board storage unit;

所述环境板存储单元用于提供与所述被测总线单元匹配的总线接口和存储介质。The environmental board storage unit is used to provide a bus interface and a storage medium matching the bus unit under test.

所述的装置，其中，所述环境板存储单元为与所述被测总线单元接口匹配的E2PROM芯片或RAM芯片。In the device described above, the environment board storage unit is an E2PROM chip or a RAM chip that matches the interface of the bus unit under test.

所述的装置，其中，所述主控单元为各类CPU、MPU系统或具有处理能力的逻辑功能模块。In the device described above, the main control unit is various types of CPUs, MPU systems or logical function modules with processing capabilities.

所述的装置，其中，所述板间连接器单元是单板间各类的插座连接器。In the device described above, the inter-board connector unit is various types of socket connectors between single boards.

所述的装置，其中，所述板间连接器为2mm高密插座连接器。The device described above, wherein the inter-board connector is a 2mm high-density socket connector.

一种板间透传总线的测试方法，其包括以下步骤：A method for testing a transparent transmission bus between boards, comprising the following steps:

A、主控单元发起写总线测试命令；A. The main control unit initiates a write bus test command;

B、被测总线单元向环境板存储单元写数据，写过程的控制、地址、数据信号从所述被测总线单元发出经板间连接器单元到环境板存储单元，并完成写操作；B. The bus unit under test writes data to the environment board storage unit, and the control, address, and data signals of the writing process are sent from the bus unit under test to the environment board storage unit through the inter-board connector unit, and the write operation is completed;

C、在延时预定时间后，保证写操作正常结束后，所述主控单元发起读总线测试命令，被测总线单元从所述环境板存储单元回读测试数据，读过程的控制、地址、数据信号通道与写过程相同，但数据信号流向相反；C. After delaying for a predetermined time and ensuring that the write operation ends normally, the main control unit initiates a bus read test command, and the bus unit under test reads back the test data from the storage unit of the environmental board, and the control, address, and The data signal channel is the same as the writing process, but the data signal flows in the opposite direction;

D、所述主控单元完成读操作后，将读写的数据进行对比，并判断被测总线单元是否正常，并给出故障定位和测试结论。D. After the main control unit completes the read operation, it compares the data read and written, and judges whether the bus unit under test is normal, and gives fault location and test conclusions.

本发明所提供的一种板间透传总线的测试装置及方法，成本低，实现简易，工作稳定可靠；其软硬件实现简易，硬件相当于外扩一个带SPI或I2C或并行接口的E2PROM芯片或RAM芯片，软件就是对存储器的读写操作；测试速度快，E2PROM的擦写操作在毫秒级时间内就可以完成，RAM的读写速度更高。A test device and method for inter-board transparent transmission bus provided by the present invention has low cost, simple implementation, stable and reliable operation; its software and hardware are easy to implement, and the hardware is equivalent to expanding an E2PROM chip with SPI or I2C or parallel interface Or RAM chip, the software is the read and write operation of the memory; the test speed is fast, the erase and write operation of E2PROM can be completed in milliseconds, and the read and write speed of RAM is higher.

附图说明 Description of drawings

图1为本发明的基于存储器实现透传总线测试框图；Fig. 1 is the block diagram of realizing transparent transmission bus test based on memory of the present invention;

图2为本发明装置的SPI透传总线接口测试实例框图。Fig. 2 is a block diagram of the SPI transparent transmission bus interface test example of the device of the present invention.

具体实施方式 Detailed ways

下面结合附图，将对本发明的各较佳实施例进行更为详细的说明。Various preferred embodiments of the present invention will be described in more detail below in conjunction with the accompanying drawings.

本发明的板间透传总线的测试装置包含以下这些部分，如图1所示的，主控单元101、板间连接器单元102和环境板存储单元103，单元201是被测总线单元。其中，所述主控单元101实现的功能是发起透传总线测试命令、控制总线单元201向环境板存储单元103写数据、控制总线单元201从环境板存储单元读取数据、对写读数据的一致性进行判断并对测试结果进行分析和故障定位、给出测试结论。The test device of the inter-board transparent transmission bus of the present invention includes the following parts. As shown in FIG. 1 , the main control unit 101, the inter-board connector unit 102 and the environment board storage unit 103, the unit 201 is the bus unit under test. Wherein, the function realized by the main control unit 101 is to initiate a transparent transmission bus test command, control the bus unit 201 to write data to the environment board storage unit 103, control the bus unit 201 to read data from the environment board storage unit, and perform the process of writing and reading data. Consistency is judged, the test results are analyzed and the fault location is given, and the test conclusion is given.

所述板间连接器单元102实现的功能是构成被测总线单元201和环境板存储单元103之间连接通道；所述环境板存储单元103实现的功能是提供与被测总线单元匹配的总线接口和存储介质，可以选择与被测总线接口匹配的E2PROM芯片或RAM芯片。The function realized by the inter-board connector unit 102 is to form the connection channel between the bus unit 201 under test and the environment board storage unit 103; the function realized by the environment board storage unit 103 is to provide a bus interface matched with the bus unit under test And storage medium, you can choose the E2PROM chip or RAM chip that matches the interface of the bus to be tested.

本装置的连接如图1所示，各单元连接关系如下：所述主控单元101发起写总线测试命令，控制总线单元201向环境板存储单元103写数据，写过程的控制、地址、数据信号从总线单元201发出经板间连接器单元102到环境板存储单元103，并完成写操作；在延时若干时间，保证写操作正常结束后，主控单元101发起读总线测试命令，控制总线单元201从环境板存储单元103回读测试数据，读过程的控制、地址、数据信号通道与写过程相同，但数据信号流向相反。主控单元101完成读操作后，将读写的数据进行对比，从而判断被测总线单元是否正常，并给出故障定位和测试结论。The connection of this device is shown in Fig. 1, and each unit connection relation is as follows: described main control unit 101 initiates write bus test order, and control bus unit 201 writes data to environment board storage unit 103, the control of writing process, address, data signal Send from the bus unit 201 to the environment board storage unit 103 via the inter-board connector unit 102, and complete the write operation; after delaying for a certain time to ensure that the write operation ends normally, the main control unit 101 initiates a read bus test command to control the bus unit 201 reads back test data from the environment board storage unit 103, the control, address, and data signal channels of the read process are the same as those of the write process, but the data signal flows in the opposite direction. After the main control unit 101 completes the read operation, it compares the read and written data, thereby judging whether the bus unit under test is normal, and gives fault location and test conclusions.

本发明装置的适用范围包括：对透传到板间连接器的总线接口的测试，并且这类总线能找到与之接口的E2PROM芯片或RAM芯片。总线可以包括但不限于下面几种，①SPI；②I2C；③并行总线。The scope of application of the device of the invention includes: the test of the bus interface transparently transmitted to the inter-board connector, and this type of bus can find the E2PROM chip or RAM chip interfaced therewith. The bus can include but not limited to the following, ①SPI; ②I2C; ③parallel bus.

本发明所述主控单元101可以是各类CPU、MPU系统或具有处理能力的逻辑功能模块，比如单片机、DSP、POWERPC小系统。板间连接器单元102可以是单板间各类的插座连接器，比如2mm高密插座连接器；环境板存储单元103是满足透传总线接口的E2PROM芯片或RAM，比如SPI总线接口测试可以选用AT25040；I2C总线接口测试可以选用24C02；并行总线接口测试可以选用低速RAM实现，RAM的选择根据并行总线地址和数据线的位数而定。The main control unit 101 of the present invention can be various types of CPU, MPU system or logical function module with processing capability, such as single chip microcomputer, DSP, POWERPC small system. The inter-board connector unit 102 can be various types of socket connectors between single boards, such as 2mm high-density socket connectors; the environmental board storage unit 103 is an E2PROM chip or RAM that meets the transparent transmission bus interface, such as the SPI bus interface test can use AT25040 ; I2C bus interface test can choose 24C02; Parallel bus interface test can choose low-speed RAM to realize, the choice of RAM depends on the number of bits of parallel bus address and data line.

本发明装置的使用方便，简单，其测试过程如下：①主控单元101启动透传总线测试命令，控制透传总线单元201向环境板存储单元103某个空间写入特定数据，比如0x55；②延迟一小段时间，保证写操作正常结束(延时时间根据存储器件特性而定)；③主控单元101控制透传总线单元201，从第①步所写的103单元空间中回读数据，并进行对比；④主控单元101判断读写数据的一致性；⑤通过向存储单元不同的地址空间写入和读出特定的其他数据，重复①～④的测试过程，使测试能覆盖被测总线的各个信号线；⑥汇总测试结果，如果出错，给出故障定位信息，最后对测试结果进行显示。The device of the present invention is easy to use and simple, and its testing process is as follows: ① The main control unit 101 starts the transparent transmission bus test command, and controls the transparent transmission bus unit 201 to write specific data, such as 0x55, into a certain space of the environment board storage unit 103; ② Delay for a short period of time to ensure that the write operation ends normally (the delay time is determined according to the characteristics of the storage device); ③ the main control unit 101 controls the transparent transmission bus unit 201, reads back the data from the 103 unit space written in the first step, and For comparison; ④The main control unit 101 judges the consistency of the read and write data; ⑤By writing and reading specific other data to different address spaces of the storage unit, repeat the test process of ①～④, so that the test can cover the bus under test ⑥summarize the test results, if there is an error, give fault location information, and finally display the test results.

下面以SPI总线透传接口测试流程为例，如图2所示，对本发明装置的一个具体实现进行介绍。Taking the test flow of the SPI bus transparent transmission interface as an example, as shown in FIG. 2 , a specific implementation of the device of the present invention is introduced.

在该实施例中，所述主控单元101是一个MPC860小系统，板间连接器单元102是一个100芯0.8间距直式PCB贴片插头(片式针)，环境板存储单元103是采用具有SPI接口的E2RPOM芯片AT25040，被测对象201包括SPI控制器、SPI总线信号所经过的缓冲驱动芯片及板间100芯插座。In this embodiment, the main control unit 101 is a small MPC860 system, the inter-board connector unit 102 is a 100-core 0.8-pitch straight PCB patch plug (chip pin), and the environmental board storage unit 103 adopts a The E2RPOM chip AT25040 of the SPI interface, the tested object 201 includes the SPI controller, the buffer driver chip through which the SPI bus signal passes, and the 100-core socket between the boards.

其测试过程如下：MPC860发起SPI透传总线测试命令，并控制MPC860上的SPI控制器向环境板上AT25040的地址0x0单元写入0x55，延时10ms，MPC860控制SPI控制器从AT25040的地址0x0单元回读数据，并判断是否是0x55，如果一致，则认为SPI总线透传接口正常，如果不一致，则SPI总线单元存在故障。The test process is as follows: MPC860 initiates the SPI transparent transmission bus test command, and controls the SPI controller on the MPC860 to write 0x55 to the address 0x0 unit of the AT25040 on the environment board, with a delay of 10ms, and MPC860 controls the SPI controller to read from the address 0x0 unit of the AT25040 Read back the data and judge whether it is 0x55. If it is consistent, it is considered that the SPI bus transparent transmission interface is normal. If it is not consistent, the SPI bus unit is faulty.

本发明装置由于其软硬件实现简易，硬件相当于外扩一个带SPI或I2C或并行接口的E2PROM芯片或RAM芯片，软件就是对存储器的读写操作；由于总线时序由存储器芯片硬件支持，因此工作稳定可靠，而且E2PROM擦写次数一般在数十万次以上，RAM芯片的可读写次数更高，足以满足测试要求；并且E2PROM和低速RAM价格便宜，因此成本低廉；并且测试速度快，E2PROM的擦写操作在毫秒级时间内就可以完成，RAM的读写速度更高。The device of the present invention is easy to realize because of its hardware and software, and the hardware is equivalent to expanding an E2PROM chip or RAM chip with SPI or I2C or parallel interface, and the software is exactly the read and write operation to the memory; Stable and reliable, and E2PROM erasing and writing times are generally more than hundreds of thousands of times, and the number of readable and writable RAM chips is higher, which is sufficient to meet the test requirements; and E2PROM and low-speed RAM are cheap, so the cost is low; and the test speed is fast, E2PROM's Erase and write operations can be completed within milliseconds, and the read and write speed of RAM is higher.

应当理解的是，上述针对具体实施例的描述较为详细，并不能因此而理解为对本发明专利保护范围的限制，本发明的专利保护范围应以所附权利要求为准。It should be understood that the above descriptions for specific embodiments are relatively detailed, and should not be construed as limiting the scope of the patent protection of the present invention, and the scope of protection of the patent protection of the present invention should be determined by the appended claims.