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CN101064284A - Manufacturing method of non-volatile memory - Google Patents

  • ️Wed Oct 31 2007

CN101064284A - Manufacturing method of non-volatile memory - Google Patents

Manufacturing method of non-volatile memory Download PDF

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Publication number
CN101064284A
CN101064284A CN 200610077052 CN200610077052A CN101064284A CN 101064284 A CN101064284 A CN 101064284A CN 200610077052 CN200610077052 CN 200610077052 CN 200610077052 A CN200610077052 A CN 200610077052A CN 101064284 A CN101064284 A CN 101064284A Authority
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Prior art keywords
layer
substrate
mask layer
nonvolatile memory
manufacture method
Prior art date
2006-04-26
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CN 200610077052
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Chinese (zh)
Inventor
张格荥
张骕远
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Powerchip Semiconductor Corp
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Powerchip Semiconductor Corp
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2006-04-26
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2006-04-26
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2007-10-31
2006-04-26 Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
2006-04-26 Priority to CN 200610077052 priority Critical patent/CN101064284A/en
2007-10-31 Publication of CN101064284A publication Critical patent/CN101064284A/en
Status Pending legal-status Critical Current

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  • 238000000034 method Methods 0.000 claims description 61
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  • VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
  • 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
  • 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
  • HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
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  • 229910021332 silicide Inorganic materials 0.000 description 1
  • FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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  • 238000004528 spin coating Methods 0.000 description 1

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Abstract

A method of manufacturing a non-volatile memory. First, a substrate with a plurality of isolation structures formed thereon is provided, the isolation structures protrude from the surface of the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is then formed on the substrate. Then, the second mask layer and the first mask layer are patterned to form a plurality of openings, and part of the substrate surface and the isolation structure surface are exposed by the openings. And forming a tunneling dielectric layer and a cylindrical floating gate with a recess on the substrate, wherein the cylindrical floating gate is respectively positioned at the position surrounded by the two adjacent isolation structures and the first mask layer. An inter-gate dielectric layer is then formed on the substrate. And forming a control grid on the substrate to fill the opening.

Description

非易失性存储器的制造方法Manufacturing method of non-volatile memory

技术领域technical field

本发明涉及一种半导体元件,且特别是涉及一种非易失性存储器的制造方法。The present invention relates to a semiconductor element, and in particular to a method for manufacturing a nonvolatile memory.

背景技术Background technique

非易失性存储器元件由于具有可多次数据的存入、读取、抹除等操作,且存入的数据在断电后也不会消失的优点,因此已成为个人计算机和电子设备所广泛采用的一种存储器元件。Non-volatile memory elements have become widely used in personal computers and electronic devices because they can store, read, and erase data multiple times, and the stored data will not disappear after power off. A memory element used.

典型的非易失性存储器元件,一般是被设计成具有堆叠栅极(Stacked-Gate)结构,其中包括以掺杂多晶硅制作的浮置栅极(Floating Gate)与控制栅极(Control Gate)。浮置栅极位于控制栅极和基底之间,且处于浮置状态,没有和任何电路相连接,而控制栅极则与字线(Word Line)相接,此外还包括隧穿氧化层(Tunneling Oxide)和栅间介电层(Inter-Gate Dielectric Layer)分别位于基底和浮置栅极之间以及浮置栅极和控制栅极之间。A typical non-volatile memory device is generally designed to have a stacked gate (Stacked-Gate) structure, which includes a floating gate (Floating Gate) and a control gate (Control Gate) made of doped polysilicon. The floating gate is located between the control gate and the substrate, and is in a floating state, not connected to any circuit, while the control gate is connected to the word line (Word Line), and also includes the tunneling oxide layer (Tunneling Oxide) and the inter-gate dielectric layer (Inter-Gate Dielectric Layer) are respectively located between the substrate and the floating gate and between the floating gate and the control gate.

在目前提高元件集成度的趋势下,会依据设计规则缩小元件的尺寸,通常浮置栅极与控制栅极之间的栅极耦合率(Gate Coupling Ratio)越大,其操作所需的工作电压将越低。而提高栅极耦合率的方法包括增加栅间介电层的电容或减少隧穿氧化层的电容。其中,增加栅间介电层电容的方法为增加控制栅极层与浮置栅极之间所夹的面积。然而,随着半导体元件集成度增加,现有的堆叠栅极结构,并无法增加控制栅极层与浮置栅极之间所夹的面积,而产生无法达到增加栅极耦合率以及增加元件集成度的问题。Under the current trend of improving the integration of components, the size of the components will be reduced according to the design rules. Usually, the larger the Gate Coupling Ratio between the floating gate and the control gate, the greater the operating voltage required for its operation. will be lower. The method for improving the gate coupling ratio includes increasing the capacitance of the inter-gate dielectric layer or reducing the capacitance of the tunnel oxide layer. Wherein, the method for increasing the capacitance of the inter-gate dielectric layer is to increase the area between the control gate layer and the floating gate. However, with the increase in the integration of semiconductor elements, the existing stacked gate structure cannot increase the area between the control gate layer and the floating gate, and cannot increase the gate coupling ratio and increase the integration of elements. question of degree.

另一方面,与非门(NAND)型阵列的闪存结构是使各存储单元串接在一起,其集成度与面积利用率比或非门(NOR)型阵列的闪存好,已经广泛地应用在多种电子产品中。但是,在制作与非门型阵列闪存时,往往需要两道以上的光掩模才能将浮置栅极与控制栅极定义出来。也就是说,需进行两次以上的光刻、蚀刻工艺才能完成。On the other hand, the flash memory structure of the NAND gate (NAND) array is to connect the memory cells in series, and its integration and area utilization are better than the flash memory of the NOR gate (NOR) array, and has been widely used in various electronic products. However, more than two photomasks are usually required to define the floating gate and the control gate when making the NAND array flash memory. That is to say, more than two photolithography and etching processes are required to complete the process.

发明内容Contents of the invention

有鉴于此,本发明的目的就是在提供一种非易失性存储器的制造方法,可以减少所使用的光掩模数,并且提高元件的集成度。In view of this, the object of the present invention is to provide a method for manufacturing a non-volatile memory, which can reduce the number of photomasks used and improve the integration of components.

本发明的另一目的是提供一种非易失性存储器的制造方法,可以增加浮置栅极与控制栅极之间所夹的面积,而提高栅极耦合率,并提升元件效能。Another object of the present invention is to provide a manufacturing method of a non-volatile memory, which can increase the area between the floating gate and the control gate, thereby increasing the gate coupling ratio and improving device performance.

本发明提出一种非易失性存储器的制造方法,包括下列步骤。首先,提供基底,此基底中已形成有往第一方向延伸的多个隔离结构。这些隔离结构突出于基底表面,且在隔离结构之间的基底上已形成有第一掩模层。在基底上形成第二掩模层,此第二掩模层覆盖住隔离结构与第一掩模层。图案化第二掩模层与第一掩模层,以形成往第二方向延伸的多个开口。这些开口暴露出部分基底表面与部分隔离结构的表面,且第一方向与第二方向交错。在基底上形成隧穿介电层后,在开口中形成分别具有凹陷部的多个筒状浮置栅极,这些筒状浮置栅极分别位于相邻的两隔离结构与第一掩模层所包围的位置上。在基底上形成栅间介电层。然后,在开口中分别形成多个控制栅极,这些控制栅极并填满筒状浮置栅极的凹陷部。The invention proposes a method for manufacturing a nonvolatile memory, which includes the following steps. First, a substrate is provided, and a plurality of isolation structures extending toward a first direction have been formed in the substrate. These isolation structures protrude from the surface of the substrate, and a first mask layer has been formed on the substrate between the isolation structures. A second mask layer is formed on the substrate, and the second mask layer covers the isolation structure and the first mask layer. The second mask layer and the first mask layer are patterned to form a plurality of openings extending in the second direction. The openings expose part of the surface of the substrate and part of the surface of the isolation structure, and the first direction and the second direction intersect. After the tunneling dielectric layer is formed on the substrate, a plurality of cylindrical floating gates respectively having recesses are formed in the openings, and these cylindrical floating gates are respectively located between the two adjacent isolation structures and the first mask layer. surrounded by the location. An inter-gate dielectric layer is formed on the substrate. Then, a plurality of control gates are respectively formed in the openings, and these control gates fill up the recessed portion of the cylindrical floating gate.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在开口中形成分别具有凹陷部的多个筒状浮置栅极的步骤如下。先在基底上形成共形的第一导体层,并移除部分第一导体层,直到暴露出第二掩模层的表面。接着,在基底上形成牺牲材料层,并移除部分牺牲材料层,直到暴露出第二掩模层的表面。之后,移除部分第一导体层,直到暴露出隔离结构的表面。然后,移除牺牲材料层。According to the manufacturing method of the nonvolatile memory according to the preferred embodiment of the present invention, the steps of forming a plurality of cylindrical floating gates each having a recess in the opening are as follows. First, a conformal first conductor layer is formed on the substrate, and part of the first conductor layer is removed until the surface of the second mask layer is exposed. Next, a sacrificial material layer is formed on the substrate, and part of the sacrificial material layer is removed until the surface of the second mask layer is exposed. Afterwards, part of the first conductor layer is removed until the surface of the isolation structure is exposed. Then, the layer of sacrificial material is removed.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在开口中形成分别具有凹陷部的筒状浮置栅极之后,还包括移除部分隔离结构,使隔离结构的顶部低于筒状浮置栅极的顶部。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, after the cylindrical floating gates respectively having recesses are formed in the openings, it further includes removing part of the isolation structure so that the top of the isolation structure is lower on top of the cylindrical floating gate.

依照本发明的优选实施例所述的非易失性存储器的制造方法,上述的第一掩模层与基底之间还包括形成有垫层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, a pad layer is further formed between the above-mentioned first mask layer and the substrate.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在图案化第二掩模层与第一掩模层的步骤之后与形成隧穿介电层的步骤之前,还包括移除部分垫层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, after the step of patterning the second mask layer and the first mask layer and before the step of forming the tunnel dielectric layer, further comprising moving Remove part of the cushion.

依照本发明的优选实施例所述的非易失性存储器的制造方法,上述的垫层的材料与隔离结构的材料相同。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the material of the pad layer is the same as that of the isolation structure.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在移除垫层的同时,还包括移除部分隔离结构。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, when removing the pad layer, it also includes removing part of the isolation structure.

依照本发明的优选实施例所述的非易失性存储器的制造方法,上述的栅间介电层的材料包括氧化硅/氮化硅/氧化硅。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the material of the inter-gate dielectric layer includes silicon oxide/silicon nitride/silicon oxide.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在基底上形成控制栅极的步骤之后,还包括移除第一掩模层与第二掩模层。According to the manufacturing method of the non-volatile memory according to the preferred embodiment of the present invention, after the step of forming the control gate on the substrate, it further includes removing the first mask layer and the second mask layer.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在基底上形成控制栅极的步骤如下。先在基底上形成第二导体层,并以第二掩模层为终止层,移除部分第二导体层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the steps of forming the control gate on the substrate are as follows. A second conductor layer is firstly formed on the substrate, and a part of the second conductor layer is removed by using the second mask layer as a termination layer.

本发明提出一种非易失性存储器的制造方法,包括下列步骤。首先提供基底,此基底中已形成有往第一方向延伸的多个隔离结构。这些隔离结构突出于基底表面,且隔离结构之间的基底上已形成有第一掩模层。在基底上形成第二掩模层后,图案化第二掩模层与第一掩模层,以形成往第二方向延伸的多个开口。这些开口暴露出部分基底表面与部分隔离结构的表面,且第一方向与第二方向交错。然后,依序在基底上形成隧穿介电层与共形的第一导体层。移除部分第一导体层,直到暴露出第二掩模层的表面后,在基底上形成牺牲材料层。然后,移除部分牺牲材料层,直到暴露出第一导体层的表面。之后,移除部分第一导体层,直到暴露出隔离结构的表面,以形成分别具有凹陷部的多个筒状导体块。移除牺牲材料层,并在基底上形成栅间介电层。在基底上形成第二导体层,此第二导体层填入筒状导体块的凹陷部并填满开口。之后,在第二导体层两侧的基底中形成多个掺杂区。The invention proposes a method for manufacturing a nonvolatile memory, which includes the following steps. Firstly, a substrate is provided, and a plurality of isolation structures extending toward the first direction have been formed on the substrate. These isolation structures protrude from the surface of the substrate, and a first mask layer has been formed on the substrate between the isolation structures. After the second mask layer is formed on the substrate, the second mask layer and the first mask layer are patterned to form a plurality of openings extending in the second direction. The openings expose part of the surface of the substrate and part of the surface of the isolation structure, and the first direction and the second direction intersect. Then, sequentially forming a tunnel dielectric layer and a conformal first conductor layer on the substrate. After removing part of the first conductor layer until the surface of the second mask layer is exposed, a sacrificial material layer is formed on the substrate. Then, part of the sacrificial material layer is removed until the surface of the first conductor layer is exposed. Afterwards, part of the first conductor layer is removed until the surface of the isolation structure is exposed, so as to form a plurality of cylindrical conductor blocks respectively having recesses. The sacrificial material layer is removed, and an inter-gate dielectric layer is formed on the substrate. A second conductor layer is formed on the base, and the second conductor layer fills the recessed portion of the cylindrical conductor block and fills up the opening. Afterwards, a plurality of doped regions are formed in the substrate on both sides of the second conductor layer.

依照本发明的优选实施例所述的非易失性存储器的制造方法,上述的牺牲材料层的材料包括光致抗蚀剂材料。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the material of the sacrificial material layer includes a photoresist material.

依照本发明的优选实施例所述的非易失性存储器的制造方法,移除牺牲材料层之后,还包括移除部分隔离结构,使隔离结构的顶部低于筒状导体块的顶部。According to the manufacturing method of the non-volatile memory according to the preferred embodiment of the present invention, after removing the sacrificial material layer, it further includes removing part of the isolation structure so that the top of the isolation structure is lower than the top of the cylindrical conductor block.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在第一掩模层与基底之间还包括形成有垫层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, a pad layer is further formed between the first mask layer and the substrate.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在图案化第二掩模层与第一掩模层的步骤之后与形成隧穿介电层的步骤之前,还包括移除部分垫层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, after the step of patterning the second mask layer and the first mask layer and before the step of forming the tunnel dielectric layer, further comprising moving Remove part of the cushion.

依照本发明的优选实施例所述的非易失性存储器的制造方法,垫层的材料与隔离结构的材料相同。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the material of the cushion layer is the same as that of the isolation structure.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在移除垫层的同时,还包括移除部分隔离结构。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, when removing the pad layer, it also includes removing part of the isolation structure.

依照本发明的优选实施例所述的非易失性存储器的制造方法,栅间介电层的材料包括氧化硅/氮化硅/氧化硅。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the material of the inter-gate dielectric layer includes silicon oxide/silicon nitride/silicon oxide.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在基底上形成第二导体层的步骤之后,还包括移除第一掩模层与第二掩模层。According to the manufacturing method of the non-volatile memory according to the preferred embodiment of the present invention, after the step of forming the second conductor layer on the substrate, it further includes removing the first mask layer and the second mask layer.

依照本发明的优选实施例所述的非易失性存储器的制造方法,在基底上形成第二导体层的步骤如下。先在基底上形成第二导体层。然后,以第二掩模层为终止层,移除部分第二导体层。According to the manufacturing method of the non-volatile memory described in the preferred embodiment of the present invention, the steps of forming the second conductor layer on the substrate are as follows. A second conductor layer is first formed on the substrate. Then, using the second mask layer as a stop layer, part of the second conductor layer is removed.

本发明的非易失性存储器的制造方法,由于利用第一掩模层与第二掩模层的形成,先定义出浮置栅极与控制栅极的图案,而在后续制作浮置栅极与控制栅极时,可以利用第一掩模层与第二掩模层为自对准掩模,无须再进行光刻蚀刻等步骤,能够减少工艺的光掩模数,进而节省制造成本。In the manufacturing method of the non-volatile memory of the present invention, since the formation of the first mask layer and the second mask layer is used, the patterns of the floating gate and the control gate are defined first, and the floating gate is subsequently fabricated. In the case of controlling the grid, the first mask layer and the second mask layer can be used as self-aligned masks, eliminating the need for steps such as photolithography and etching, which can reduce the number of photomasks in the process, thereby saving manufacturing costs.

而且,由于不必对于第一导体层、第二导体层直接进行光刻、蚀刻等步骤,因此,还可以避免由于线宽缩小所导致的在导体层之间形成微桥接的情形,进而预防短路现象。这也就是说,本发明所采用的存储器的制造方法,可以制造线宽更窄的存储器,达到提高元件集成度的功效。Moreover, since it is not necessary to directly perform steps such as photolithography and etching on the first conductor layer and the second conductor layer, it is also possible to avoid the formation of micro-bridges between the conductor layers due to the narrowing of the line width, thereby preventing short circuits. . That is to say, the memory manufacturing method adopted in the present invention can manufacture memory with narrower line width, so as to achieve the effect of improving the integration degree of components.

此外,本发明的非易失性存储器的制造方法,可制作出具有凹陷部的筒状浮置栅极(导体块)。而控制栅极填入筒状浮置栅极的凹陷部,因此浮置栅极与控制栅极之间的面积可以增加,进而提升存储器的栅极耦合率,降低存储器在操作时所需的电压,而提升元件的效能。In addition, the manufacturing method of the nonvolatile memory of the present invention can manufacture a cylindrical floating gate (conductor block) having a recessed portion. The control gate is filled into the recess of the cylindrical floating gate, so the area between the floating gate and the control gate can be increased, thereby improving the gate coupling rate of the memory and reducing the voltage required for the memory to operate. , and enhance the performance of the device.

为让本发明的上述和其它目的、特征和优点能更明显易懂,以下配合附图以及优选实施例,以更详细地说明本发明。In order to make the above and other objects, features and advantages of the present invention more comprehensible, the present invention will be described in more detail below with reference to the accompanying drawings and preferred embodiments.

附图说明Description of drawings

图1A至图1F为绘示本发明的实施例的一种非易失性存储器的制造流程上视图。1A to 1F are top views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

图2A至图2F为分别绘示图1A至图1F中沿A-A’线的剖面示意图。2A to 2F are schematic cross-sectional views along line A-A' in FIGS. 1A to 1F .

图3A至图3F为分别绘示图1A至图1F中沿B-B’线的剖面示意图。3A to 3F are schematic cross-sectional views along line B-B' in FIGS. 1A to 1F respectively.

图4A至图4F为分别绘示图1A至图1F中沿C-C’线的剖面示意图。FIGS. 4A to 4F are schematic cross-sectional views along line C-C' in FIGS. 1A to 1F .

简单符号说明simple notation

100:基底100: base

102:隔离结构102: Isolation structure

104:有源区104: Active area

106:垫层106: Cushion

108、110:掩模层108, 110: mask layer

112:开口112: opening

114:凹陷114: sunken

116:隧穿介电层116: tunneling dielectric layer

118、128、128a:导体层118, 128, 128a: conductor layer

118a:筒状导体块118a: cylindrical conductor block

120:牺牲材料层120: sacrificial material layer

122:凹陷部122: Depressed part

124:下凹124: Concave

126:栅间介电层126: inter-gate dielectric layer

130:掺杂区130: doped area

具体实施方式Detailed ways

图1A至图1F为绘示本发明的实施例的一种非易失性存储器的制造流程上视图。图2A至图2F2分别绘示图1A至图1F中沿A-A’线的剖面示意图。图3A至图3F为分别绘示图1A至图1F中沿B-B’线的剖面示意图。图4A至图4F为分别绘示图1A至图1F中沿C-C’线的剖面示意图。其中,A-A’线是沿着字线的切线;B-B’线是沿着有源区的切线;C-C’是沿着隔离结构的切线。1A to 1F are top views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the present invention. 2A to 2F2 are schematic cross-sectional views along line A-A' in FIGS. 1A to 1F respectively. 3A to 3F are schematic cross-sectional views along line B-B' in FIGS. 1A to 1F respectively. FIGS. 4A to 4F are schematic cross-sectional views along line C-C' in FIGS. 1A to 1F . Wherein, A-A' line is a tangent line along the word line; B-B' line is a tangent line along the active region; C-C' is a tangent line along the isolation structure.

本发明所提出的非易失性存储器的制造方法例如是适用于形成与非门型阵列的闪存,当然,此制造方法亦可用于形成其它种类的非易失性存储器。The manufacturing method of the non-volatile memory proposed by the present invention is, for example, suitable for forming NAND gate array flash memory, of course, this manufacturing method can also be used to form other types of non-volatile memory.

请参照图1A、图2A、图3A与图4A,首先提供基底100。基底100例如是硅基底。在基底100中已形成有多个隔离结构102,这些隔离结构102突出于基底100表面,以定义出有源区104。Referring to FIG. 1A , FIG. 2A , FIG. 3A and FIG. 4A , firstly, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. A plurality of isolation structures 102 have been formed in the substrate 100 , and these isolation structures 102 protrude from the surface of the substrate 100 to define an active region 104 .

隔离结构102例如是往X方向延伸。隔离结构102之间的基底100上已形成有垫层106与掩模层108。隔离结构102例如是浅沟槽隔离结构,其形成方法例如是先在基底100上依序形成整层垫层106与整层掩模层108,之后图案化掩模层108与垫层106,以形成暴露基底100的开口(未绘示)。然后,以掩模层108为掩模蚀刻基底100,而在基底100中形成多个沟槽(未绘示),之后再于沟槽中填入绝缘材料而形成之。The isolation structure 102 extends in the X direction, for example. A pad layer 106 and a mask layer 108 have been formed on the substrate 100 between the isolation structures 102 . The isolation structure 102 is, for example, a shallow trench isolation structure, and its formation method is, for example, firstly forming an entire pad layer 106 and an entire mask layer 108 on the substrate 100, and then patterning the mask layer 108 and the pad layer 106 to An opening (not shown) exposing the substrate 100 is formed. Then, the substrate 100 is etched using the mask layer 108 as a mask to form a plurality of trenches (not shown) in the substrate 100 , and then an insulating material is filled in the trenches to form them.

垫层106的材料例如是氧化硅,其形成方法例如是热氧化法。掩模层108的材料例如是氮化硅,其形成方法例如是化学气相沉积法。沟槽中所填入的绝缘材料例如是氧化硅。The material of the pad layer 106 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation. The material of the mask layer 108 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition. The insulating material filled in the trench is, for example, silicon oxide.

接着,在基底100上形成另一层掩模层110。掩模层110的材料可以是与掩模层108相同的材料,例如是氮化硅,其形成方法例如是化学气相沉积法。而且,掩模层108与掩模层110的材料与隔离结构102的材料具有不同的蚀刻选择性。Next, another mask layer 110 is formed on the substrate 100 . The mask layer 110 can be made of the same material as the mask layer 108 , such as silicon nitride, and its formation method is, for example, chemical vapor deposition. Moreover, the materials of the mask layer 108 and the mask layer 110 and the material of the isolation structure 102 have different etch selectivities.

请参照图1B、图2B、图3B与图4B,图案化掩模层110与掩模层108,形成多个开口112。这些开口112例如是往Y方向延伸,并暴露出部分垫层106的表面与部分隔离结构102的表面。图案化掩模层110与掩模层108的方法例如是利用光刻蚀刻工艺而形成之。由于掩模层110与掩模层108的材料与隔离结构102的材料具有不同的蚀刻选择性,因此隔离结构102不会受到蚀刻,而得以保留下来。Referring to FIG. 1B , FIG. 2B , FIG. 3B and FIG. 4B , the mask layer 110 and the mask layer 108 are patterned to form a plurality of openings 112 . The openings 112 extend in the Y direction, for example, and expose part of the surface of the pad layer 106 and part of the surface of the isolation structure 102 . A method of patterning the mask layer 110 and the mask layer 108 is, for example, formed by photolithography and etching. Since the materials of the mask layer 110 and the mask layer 108 and the material of the isolation structure 102 have different etch selectivities, the isolation structure 102 will not be etched and will remain.

请参照图1C、图2C、图3C与图4C,移除垫层106。移除垫层106的方法例如是湿式蚀刻法。在本实施例中,由于隔离结构102的材料与垫层106的材料相同,因此在移除垫层106的同时,也会移除掉部分的隔离结构102,而形成如图2C中的凹陷114,并使两相邻隔离结构102的突出基底100表面部分的间距变大。Referring to FIG. 1C , FIG. 2C , FIG. 3C and FIG. 4C , the cushion layer 106 is removed. A method for removing the pad layer 106 is, for example, a wet etching method. In this embodiment, since the material of the isolation structure 102 is the same as that of the pad layer 106, when the pad layer 106 is removed, part of the isolation structure 102 will also be removed to form a depression 114 as shown in FIG. 2C , and make the distance between two adjacent isolation structures 102 protruding from the surface of the substrate 100 larger.

接着,在基底100上形成一层隧穿介电层116。隧穿介电层116的材料例如是氧化硅。隧穿介电层116的形成方法例如是热氧化法。Next, a tunneling dielectric layer 116 is formed on the substrate 100 . The material of the tunneling dielectric layer 116 is, for example, silicon oxide. A method for forming the tunneling dielectric layer 116 is, for example, a thermal oxidation method.

然后,在基底100上形成一层导体层118。导体层118例如是共形于基底100表面。导体层118的材料例如是掺杂多晶硅,其形成方法例如是利用化学气相沉积法形成一层未掺杂多晶硅层后(未绘示),进行离子注入步骤以形成之;或者是采用临场注入掺杂物的方式以化学气相沉积法形成之。然后,移除部分导体层118直到暴露出掩模层110的表面。移除部分导体层118的方法例如是化学机械研磨法。而且,在以化学机械研磨法移除部分导体层118时,例如是以掩模层110作为研磨终止层。此外,掩模层110表面高于隔离结构102表面,因此隔离结构102上方的导体层118将不会完全被化学机械研磨法移除。Then, a conductor layer 118 is formed on the substrate 100 . The conductive layer 118 is, for example, conformal to the surface of the substrate 100 . The material of the conductive layer 118 is, for example, doped polysilicon, and its formation method is, for example, to form an undoped polysilicon layer (not shown) by chemical vapor deposition, and then perform ion implantation to form it; Impurities are formed by chemical vapor deposition. Then, a portion of the conductive layer 118 is removed until the surface of the mask layer 110 is exposed. A method for removing part of the conductive layer 118 is, for example, chemical mechanical polishing. Moreover, when removing part of the conductive layer 118 by chemical mechanical polishing, for example, the mask layer 110 is used as a polishing stop layer. In addition, the surface of the mask layer 110 is higher than the surface of the isolation structure 102, so the conductive layer 118 above the isolation structure 102 will not be completely removed by the chemical mechanical polishing method.

然后,在基底100上形成一层牺牲材料层120,此牺牲材料层120填满开口112。牺牲材料层120的材料例如是光致抗蚀剂材料或底层抗反射蚀刻材料。牺牲材料层120的形成方法例如是旋转涂布法。Then, a sacrificial material layer 120 is formed on the substrate 100 , and the sacrificial material layer 120 fills the opening 112 . The material of the sacrificial material layer 120 is, for example, photoresist material or underlying anti-reflective etching material. The formation method of the sacrificial material layer 120 is, for example, a spin coating method.

然后,请参照图1D、图2D、图3D与图4D,移除部分牺牲材料层120直到暴露出掩模层110的表面。移除部分牺牲材料层120的方法例如是化学机械研磨法。而且,在以化学机械研磨法移除部分牺牲材料层120时,例如是以隔离结构102上方的导体层118作为研磨终止层。Then, referring to FIG. 1D , FIG. 2D , FIG. 3D and FIG. 4D , part of the sacrificial material layer 120 is removed until the surface of the mask layer 110 is exposed. A method for removing part of the sacrificial material layer 120 is, for example, a chemical mechanical polishing method. Moreover, when the part of the sacrificial material layer 120 is removed by chemical mechanical polishing, for example, the conductive layer 118 above the isolation structure 102 is used as a polishing stop layer.

之后,移除隔离结构102上的导体层118,使导体层118的表面等于隔离结构102的表面(未绘示),而使导体层118被分隔成分别具有凹陷部122的多个筒状导体块118a。移除部分导体层118的方法例如是以牺牲材料层120为掩模进行回蚀刻法。此时,相邻的两隔离结构102与相邻的两掩模层108分隔出筒状导体块118a,此筒状导体块118a即作为浮置栅极之用。亦即,本发明的筒状导体块118a分别位于相邻的两隔离结构102与掩模层108所包围的位置上。Afterwards, the conductor layer 118 on the isolation structure 102 is removed, so that the surface of the conductor layer 118 is equal to the surface (not shown) of the isolation structure 102, and the conductor layer 118 is separated into a plurality of cylindrical conductors each having a recess 122 Block 118a. A method for removing part of the conductor layer 118 is, for example, using the sacrificial material layer 120 as a mask to etch back. At this time, the two adjacent isolation structures 102 and the two adjacent mask layers 108 separate a cylindrical conductor block 118a, and the cylindrical conductive block 118a is used as a floating gate. That is to say, the cylindrical conductor blocks 118 a of the present invention are respectively located at positions surrounded by two adjacent isolation structures 102 and the mask layer 108 .

然后,请参照图1E、图2E、图3E与图4E,移除牺牲材料层120。移除牺牲材料层120的方法例如是湿式去光致抗蚀剂法。接着,移除部分隔离结构102,使隔离结构102的顶面低于筒状导体块118a的顶面,而形成如图2E与图4E中的下凹124。移除部分隔离结构102的方法例如是蚀刻法。Then, referring to FIG. 1E , FIG. 2E , FIG. 3E and FIG. 4E , the sacrificial material layer 120 is removed. A method for removing the sacrificial material layer 120 is, for example, a wet stripping photoresist method. Next, part of the isolation structure 102 is removed, so that the top surface of the isolation structure 102 is lower than the top surface of the cylindrical conductor block 118a, thereby forming the recess 124 as shown in FIG. 2E and FIG. 4E. A method for removing part of the isolation structure 102 is, for example, an etching method.

接着,在基底100上形成栅间介电层126。栅间介电层126的材料例如是氧化硅/氮化硅/氧化硅,其形成方法例如是利用化学气相沉积法依序形成一层氧化硅层、一层氮化硅与一层氧化硅层。当然,栅间介电层126的材料还可以是氧化硅、氮化硅或氧化硅/氮化硅等材料,其形成方法例如是依照其材料以不同的反应气体进行化学气相沉积法。Next, an inter-gate dielectric layer 126 is formed on the substrate 100 . The material of the inter-gate dielectric layer 126 is, for example, silicon oxide/silicon nitride/silicon oxide, and its formation method is, for example, using chemical vapor deposition to sequentially form a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. . Of course, the material of the inter-gate dielectric layer 126 can also be silicon oxide, silicon nitride or silicon oxide/silicon nitride, and the formation method is, for example, chemical vapor deposition with different reactive gases according to the material.

之后,在基底100上形成填满开口112的另一层导体层128。导体层128并填满筒状导体块118a的凹陷部122。Afterwards, another conductive layer 128 filling the opening 112 is formed on the substrate 100 . The conductor layer 128 also fills the recessed portion 122 of the cylindrical conductor block 118a.

导体层128的材料例如是金属、金属硅化物或掺杂多晶硅等适当的导体材料。导体层128的形成方法例如是依其材料选用物理气相沉积法或化学气相沉积法。The material of the conductor layer 128 is, for example, a suitable conductor material such as metal, metal silicide, or doped polysilicon. The formation method of the conductor layer 128 is, for example, physical vapor deposition or chemical vapor deposition according to its material.

接着,请参照图1F、图2F、图3F与图4F,移除部分导体层128,而形成只位于开口112内的导体层128a。导体层128a即作为控制栅极之用。移除部分导体层128的方法例如是化学机械研磨法或是回蚀刻法。在移除部分导体层128时,例如是以掩模层110作为研磨终止层或蚀刻终止层。而且,在移除部分导体层128时,由于栅间介电层126的厚度不大,因此掩模层110上的栅间介电层126也可能会一并被移除。此外,掩模层110表面高于浮置栅极118a,因此导体层128a在图2F中为连续无间断的控制栅极。Next, referring to FIG. 1F , FIG. 2F , FIG. 3F and FIG. 4F , part of the conductor layer 128 is removed to form the conductor layer 128 a only located in the opening 112 . The conductive layer 128a is used as a control gate. The method for removing part of the conductive layer 128 is, for example, chemical mechanical polishing or etching back. When removing part of the conductive layer 128 , for example, the mask layer 110 is used as a grinding stop layer or an etching stop layer. Moreover, when removing part of the conductive layer 128 , since the thickness of the inter-gate dielectric layer 126 is not large, the inter-gate dielectric layer 126 on the mask layer 110 may also be removed together. In addition, the surface of the mask layer 110 is higher than the floating gate 118a, so the conductive layer 128a is a continuous and uninterrupted control gate in FIG. 2F.

接着,移除掩模层110、掩模层108后,在导体层128a两侧的基底100中形成多个掺杂区130。移除掩模层110、掩模层108与垫层106的方法例如是干式或湿式蚀刻法。掺杂区130的形成方法例如是以导体层128a为掩模,进行掺杂物注入工艺,注入的掺杂物例如是N型掺杂物。当然移除垫层106,其端视工艺的需求而定。至于后续完成非易失性存储器的工艺为本领域技术人员所周知,在此不再赘述。Next, after removing the mask layer 110 and the mask layer 108 , a plurality of doped regions 130 are formed in the substrate 100 on both sides of the conductor layer 128 a. The method for removing the mask layer 110 , the mask layer 108 and the pad layer 106 is, for example, dry or wet etching. The method for forming the doped region 130 is, for example, using the conductive layer 128 a as a mask to perform a dopant implantation process, and the implanted dopant is, for example, an N-type dopant. Of course, the bedding layer 106 is removed, but it depends on the requirements of the process. The subsequent process for completing the non-volatile memory is well known to those skilled in the art and will not be repeated here.

本发明提出的非易失性存储器的制造方法,利用制作字线的光掩模图案化掩模层110、掩模层108,而先将欲形成的栅极图案定义出来,再依序形成浮置栅极(导体层118a)与控制栅极(导体层128a)。由于栅极的图案已经定义,因此浮置栅极与控制栅极的形成仅需利用掩模层110、掩模层108的自对准掩模,无须再进行光刻蚀刻等步骤,可以节省光掩模数目与成本。The manufacturing method of the non-volatile memory proposed by the present invention uses a photomask for making word lines to pattern the mask layer 110 and mask layer 108, and first defines the gate pattern to be formed, and then sequentially forms the floating gate pattern. A gate (conductive layer 118a) and a control gate (conductive layer 128a) are placed. Since the pattern of the gate has been defined, the formation of the floating gate and the control gate only needs to use the self-aligned mask of the mask layer 110 and the mask layer 108, and there is no need to perform steps such as photolithography and etching, which can save light. Mask count and cost.

而且,本发明的非易失性存储器的制造方法,可制作出具有凹陷部的筒状浮置栅极(导体层118a),而控制栅极(导体层128a)填入筒状浮置栅极(导体层118a)的凹陷部。因此浮置栅极(导体层118a)与控制栅极(导体层128a)之间的面积可以增加,进而提升存储器的栅极耦合率。同样的,凹陷114与下凹124的形成,也都可以增加浮置栅极(导体层118a)与控制栅极(导体层128a)之间的面积,进而提升存储器的栅极耦合率。栅极耦合率(Coupling Ratio)值越高,则存储器在操作时所需的电压越低,元件的效率也会随之提高。Moreover, the manufacturing method of the nonvolatile memory of the present invention can produce a cylindrical floating gate (conductive layer 118a) with a recessed portion, and the control gate (conductive layer 128a) is filled in the cylindrical floating gate. (Conductor layer 118a). Therefore, the area between the floating gate (conductive layer 118 a ) and the control gate (conductive layer 128 a ) can be increased, thereby improving the gate coupling ratio of the memory. Similarly, the formation of the recess 114 and the recess 124 can also increase the area between the floating gate (conductive layer 118 a ) and the control gate (conductive layer 128 a ), thereby increasing the gate coupling rate of the memory. The higher the value of the gate coupling ratio (Coupling Ratio), the lower the voltage required for the memory to operate, and the efficiency of the device will increase accordingly.

综上所述,本发明利用掩模层的形成,先定义出浮置栅极与控制栅极的图案,而在后续制作浮置栅极与控制栅极时,可以利用掩模层为自对准掩模,无须再进行光刻蚀刻等步骤,能够减少工艺的光掩模数,进而节省制造成本。In summary, the present invention uses the formation of the mask layer to first define the patterns of the floating gate and the control gate, and when the floating gate and the control gate are subsequently manufactured, the mask layer can be used as a self-aligning gate. The quasi-mask eliminates the need for steps such as photolithography and etching, which can reduce the number of photomasks in the process, thereby saving manufacturing costs.

而且,由于不必对在导体层直接进行光刻、蚀刻等步骤,因此,还可以避免由于线宽缩小所导致在导体层之间形成微桥接的情形,进而预防短路现象。这也就是说,本发明所采用的存储器的制造方法,可以制造线宽更窄的存储器,达到提高元件集成度的功效。Moreover, since it is not necessary to directly perform steps such as photolithography and etching on the conductor layer, it is also possible to avoid the formation of micro-bridges between the conductor layers due to the narrowing of the line width, thereby preventing short circuits. That is to say, the memory manufacturing method adopted in the present invention can manufacture memory with narrower line width, so as to achieve the effect of improving the integration degree of components.

此外,本发明的非易失性存储器的制造方法,可制作出具有凹陷部的筒状浮置栅极。而控制栅极填入筒状浮置栅极的凹陷部,因此浮置栅极与控制栅极之间的面积可以增加,进而提升存储器的栅极耦合率,降低存储器在操作时所需的电压,而提升元件的效能。In addition, the manufacturing method of the nonvolatile memory of the present invention can manufacture a cylindrical floating gate with a recessed portion. The control gate is filled into the recess of the cylindrical floating gate, so the area between the floating gate and the control gate can be increased, thereby improving the gate coupling rate of the memory and reducing the voltage required for the memory to operate. , and enhance the performance of the device.

虽然本发明以优选实施例揭露如上,然而其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作些许的更动与润饰,因此本发明的保护范围应当以后附的权利要求所界定者为准。Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the appended claims.

Claims (20)

1, a kind of manufacture method of nonvolatile memory comprises:

Substrate is provided, has been formed with a plurality of isolation structures that extend toward first direction in the described substrate, described isolation structure is outstanding at described substrate surface, and has been formed with first mask layer in the described substrate between the described isolation structure;

Form second mask layer in described substrate, described second mask layer covers described isolation structure and described first mask layer;

Described second mask layer of patterning and described first mask layer form a plurality of openings that extend toward second direction, and described opening exposes the surface of described substrate surface of part and the described isolation structure of part, and described first direction and described second direction are staggered;

In described substrate, form tunnel dielectric layer;

In described opening, form and have a plurality of tubular float gate electrode of depressed part respectively, described tubular float gate electrode respectively the position on the position that two adjacent described isolation structures and described first mask layer are surrounded;

Forming dielectric layer between grid in the described substrate; And

Form a plurality of control grids in described opening respectively, described control grid also fills up the described depressed part of described tubular float gate electrode.

2, the manufacture method of nonvolatile memory as claimed in claim 1, the step that wherein forms a plurality of tubular float gate electrode that have described depressed part respectively in described opening comprises:

In described substrate, form the first conformal conductor layer;

Remove described first conductor layer of part, up to the surface that exposes described second mask layer;

In described substrate, form sacrificial material layer;

Remove the described sacrificial material layer of part, up to the surface that exposes described second mask layer;

Remove described first conductor layer of part, up to the surface that exposes described isolation structure; And

Remove described sacrificial material layer.

3, the manufacture method of nonvolatile memory as claimed in claim 1, wherein in described opening, form and have respectively after the described tubular float gate electrode of described depressed part, also comprise removing the described isolation structure of part, make the top of described isolation structure hang down top in described tubular float gate electrode.

4, the manufacture method of nonvolatile memory as claimed in claim 1 wherein also comprises being formed with bed course between described first mask layer and described substrate.

5, the manufacture method of nonvolatile memory as claimed in claim 4, wherein after the step of described second mask layer of patterning and described first mask layer with the step that forms described tunnel dielectric layer before, also comprise removing the described bed course of part.

6, the manufacture method of nonvolatile memory as claimed in claim 4, the material of wherein said bed course is identical with the material of described isolation structure.

7, the manufacture method of nonvolatile memory as claimed in claim 5 wherein when removing described bed course, also comprises removing the described isolation structure of part.

8, the manufacture method of nonvolatile memory as claimed in claim 1, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between wherein said grid.

9, the manufacture method of nonvolatile memory as claimed in claim 1 wherein forms in described substrate after the step of described control grid, also comprises removing described first mask layer and described second mask layer.

10, the manufacture method of nonvolatile memory as claimed in claim 1, the step that wherein forms described control grid in described substrate comprises:

In described substrate, form second conductor layer; And

With described second mask layer is stop layer, removes described second conductor layer of part.

11, a kind of manufacture method of nonvolatile memory comprises:

One substrate is provided, has been formed with a plurality of isolation structures that extend toward first direction in the described substrate, described isolation structure is outstanding at described substrate surface, and has been formed with first mask layer in the described substrate between the described isolation structure;

In described substrate, form second mask layer;

Described second mask layer of patterning and described first mask layer form a plurality of openings that extend toward second direction, and described opening exposes the surface of described substrate surface of part and the described isolation structure of part, and described first direction and described second direction are staggered;

In described substrate, form tunnel dielectric layer;

In described substrate, form the first conformal conductor layer;

Remove described first conductor layer of part, up to the surface that exposes described second mask layer;

In described substrate, form sacrificial material layer;

Remove the described sacrificial material layer of part, up to the surface that exposes described first conductor layer;

Remove described first conductor layer of part,, have a plurality of tubular conductor block of a depressed part respectively to form up to the surface that exposes described isolation structure;

Remove described sacrificial material layer;

Forming dielectric layer between grid in the described substrate;

Form second conductor layer in described substrate, described second conductor layer is inserted the described depressed part of described tubular conductor block and is filled up described opening; And

In the described substrate of the described second conductor layer both sides, form a plurality of doped regions.

12, the manufacture method of nonvolatile memory as claimed in claim 11, the material of wherein said sacrificial material layer comprises photo anti-corrosion agent material.

13, the manufacture method of nonvolatile memory as claimed in claim 11 wherein removes after the described sacrificial material layer, also comprises removing the described isolation structure of part, makes the top of described isolation structure hang down top in described tubular conductor block.

14, the manufacture method of nonvolatile memory as claimed in claim 11 wherein also comprises being formed with bed course between described first mask layer and described substrate.

15, the manufacture method of nonvolatile memory as claimed in claim 14, wherein after the step of described second mask layer of patterning and described first mask layer with the step that forms described tunnel dielectric layer before, also comprise removing the described bed course of part.

16, the manufacture method of nonvolatile memory as claimed in claim 14, the material of wherein said bed course is identical with the material of described isolation structure.

17, the manufacture method of nonvolatile memory as claimed in claim 15 wherein when removing described bed course, also comprises removing the described isolation structure of part.

18, the manufacture method of nonvolatile memory as claimed in claim 11, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between wherein said grid.

19, the manufacture method of nonvolatile memory as claimed in claim 11 wherein forms in described substrate after the step of described second conductor layer, also comprises removing described first mask layer and described second mask layer.

20, the manufacture method of nonvolatile memory as claimed in claim 11, the step that wherein forms described second conductor layer in described substrate comprises:

In described substrate, form described second conductor layer; And

With described second mask layer is stop layer, removes described second conductor layer of part.

CN 200610077052 2006-04-26 2006-04-26 Manufacturing method of non-volatile memory Pending CN101064284A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311282A (en) * 2012-03-14 2013-09-18 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN102881693B (en) * 2012-10-25 2017-05-24 上海华虹宏力半导体制造有限公司 Storage device and manufacturing method thereof
CN108962900A (en) * 2017-05-17 2018-12-07 力晶科技股份有限公司 memory structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311282A (en) * 2012-03-14 2013-09-18 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN102881693B (en) * 2012-10-25 2017-05-24 上海华虹宏力半导体制造有限公司 Storage device and manufacturing method thereof
CN108962900A (en) * 2017-05-17 2018-12-07 力晶科技股份有限公司 memory structure and manufacturing method thereof

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