CN101178932A - Method for reading double-bit memory cell - Google Patents

A method of reading a dual bit memory cell. The dual bit memory cell includes a control terminal, a first terminal and a second terminal, and the dual bit memory cell has a first bit storage node and a second bit storage node adjacent to the first terminal and the second terminal, respectively. First, a control voltage and a read voltage are applied to the control terminal and the first terminal, respectively, and the second terminal is grounded to measure a first output current value of the first terminal. Then, the control voltage and the reading voltage are respectively applied to the control end and the second end, and the first end is grounded so as to measure a second output current value of the second end. Finally, the bit states of the first bit storage node and the second bit storage node are read simultaneously according to the first output current value and the second output current value.

读取双位存储单元的方法 Method for reading double-bit memory cells

技术领域 technical field

本发明有关一种读取双位存储单元的方法，且特别是有关一种读取双位的氮化物只读存储器存储单元(Nitride Read-Only Memory cell)的方法。The present invention relates to a method for reading a double-bit memory cell, and in particular to a method for reading a double-bit Nitride Read-Only Memory cell (Nitride Read-Only Memory cell).

背景技术 Background technique

请参照图1，其是氮化物只读存储器的存储单元结构的剖面示意图。为了获得高密度的存储元件，目前已发展出可储存2位的氮化物只读存储器(NitrideRead-Only Memory)存储单元10，以取代传统利用浮动栅极(floating gate)而只能储存1位的设计。如图1所示，氮化物只读存储器存储单元10包括注入有源极12及漏极14的基材(bulk)15，且基材15上方为氧化物-氮化物-氧化物(oxide-nitride-oxide，ONO)结构16与栅极13。ONO结构16是由上氧化物层(top oxide layer)16a、氮化物层16b以及底氧化物层(bottom oxide layer)16c堆栈而成。Please refer to FIG. 1 , which is a schematic cross-sectional view of a memory cell structure of a nitride ROM. In order to obtain high-density storage elements, a Nitride Read-Only Memory (Nitride Read-Only Memory) memory cell 10 that can store 2 bits has been developed to replace the traditional one that uses a floating gate (floating gate) and can only store 1 bit. design. As shown in FIG. 1 , a nitride read-only memory unit 10 includes a substrate (bulk) 15 implanted with a source 12 and a drain 14, and an oxide-nitride-oxide (oxide-nitride) is formed above the substrate 15. -oxide, ONO) structure 16 and gate 13. The ONO structure 16 is formed by stacking a top oxide layer 16a, a nitride layer 16b and a bottom oxide layer 16c.

ONO结构16中的氮化物层16b(如氮化硅)是作为非导体的电荷捕捉层(charge-trapping layer)。借此，进行编程(program)动作时，氮化物层16b的两侧(即分别邻近源极12及漏极14)可各自供来自源极12及漏极14的热电子注入并加以捕捉。于是，氮化物层16b的两侧分别形成氮化物只读存储器存储单元10的第一位储存节(bit storage node)B1及第二位储存节B2，如虚线框所示；视其中有无捕捉电荷而分别储存1位的0或1的逻辑数据。借由这两个位储存节B1及B2，氮化物只读存储器存储单元10一次能储存两位，并较佳地以逆向读取(reverse read)的方式将氮化物只读存储器存储单元10的输出电流大小与一参考默认值作一比较判断而分别独立存取两位储存节B1及B2的位状态。然而，第二位效应(second-bit effect)会影响读取时氮化物只读存储器存储单元10的输出电流大小，大幅限制参考默认值的设定范围而减少了读取感测窗口(sensing window)。The nitride layer 16b (such as silicon nitride) in the ONO structure 16 is a charge-trapping layer as a non-conductor. Thereby, during the program operation, the two sides of the nitride layer 16b (ie adjacent to the source 12 and the drain 14 respectively) can respectively inject and capture hot electrons from the source 12 and the drain 14 . Then, the first bit storage node (bit storage node) B1 and the second bit storage node B2 of the nitride ROM storage unit 10 are respectively formed on both sides of the nitride layer 16b, as shown in the dotted line box; charge to store logic data of 1 bit of 0 or 1 respectively. By means of these two bit storage nodes B1 and B2, the nitride ROM storage unit 10 can store two bits at a time, and the nitride ROM storage unit 10 is preferably read in a reverse read manner. The magnitude of the output current is compared with a reference default value for judgment, and the bit states of the two-bit storage sections B1 and B2 are independently accessed. However, the second-bit effect will affect the magnitude of the output current of the nitride ROM storage unit 10 during reading, which greatly limits the setting range of the reference default value and reduces the reading sensing window (sensing window) ).

发明内容 Contents of the invention

有鉴于此，本发明的目的就是提供一种读取双位存储单元的方法。有别于传统的对两个位储存节分别独立读取其位状态，本发明是利用双位存储单元于两种读取方向时的两输出电流值来同时决定出其所具有的位状态组合。借此，能更正确判读出两个位状态，有效增加读取感测窗口。In view of this, the object of the present invention is to provide a method for reading a double-bit memory cell. Different from the traditional way of independently reading the bit states of the two bit storage sections, the present invention uses the two output current values of the double-bit memory cell in two reading directions to simultaneously determine its bit state combination . Thereby, the states of the two bits can be read out more correctly, and the reading sensing window can be effectively increased.

根据本发明的目的，提出一种读取双位存储单元的方法。双位存储单元包括控制端、第一端以及第二端，双位存储单元于邻近第一端及第二端之处分别具有第一位储存节及第二位储存节。首先，分别施加控制电压及读取电压至控制端及第一端，且将第二端接地，以测量第一端的第一输出电流值。接着，分别施加控制电压及读取电压至控制端及第二端，且将第一端接地，以测量第二端的第二输出电流值。最后，根据第一输出电流值及第二输出电流值来同时读取第一位储存节及第二位储存节的位状态。According to the object of the present invention, a method for reading a double-bit memory cell is proposed. The double-bit storage unit includes a control terminal, a first terminal and a second terminal. The double-bit storage unit has a first storage node and a second storage node adjacent to the first terminal and the second terminal. Firstly, apply the control voltage and the reading voltage to the control terminal and the first terminal respectively, and ground the second terminal to measure the first output current value of the first terminal. Then, apply the control voltage and the reading voltage to the control terminal and the second terminal respectively, and ground the first terminal to measure the second output current value of the second terminal. Finally, the bit states of the first bit storage section and the second bit storage section are simultaneously read according to the first output current value and the second output current value.

为让本发明的上述目的、特征、和优点能更明显易懂，下文特举较佳实施例，并配合附图进行详细说明如下：In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below, and are described in detail in conjunction with the accompanying drawings as follows:

附图说明 Description of drawings

图1是氮化物只读存储器的存储单元结构的剖面示意图。FIG. 1 is a schematic cross-sectional view of a memory cell structure of a nitride read-only memory.

图2A至2D是双位存储单元的四种位状态组合的示意图。2A to 2D are schematic diagrams of four bit state combinations of a double-bit memory cell.

图3是依照本发明的读取双位存储单元200的方法的流程图。FIG. 3 is a flowchart of a method for reading a dual-bit memory cell 200 according to the present invention.

图4A至4D分别绘示图2A至2D的双位存储单元200的四种位状态组合下第一输出电流值I_1及第二输出电流值I_2随控制电压Vg变化的曲线图。FIGS. 4A to 4D are graphs showing the variation of the first output current value I_1 and the second output current value I_2 with the control voltage Vg under the four bit state combinations of the two-bit memory cell 200 in FIGS. 2A to 2D .

图4E是图4A至4D中的第二输出电流值I_2随控制电压Vg变化的曲线图。FIG. 4E is a graph showing the variation of the second output current value I_2 with the control voltage Vg in FIGS. 4A to 4D .

图5是依照本发明第一实施例的图3中步骤330的子步骤的流程图。FIG. 5 is a flow chart of the sub-steps of step 330 in FIG. 3 according to the first embodiment of the present invention.

图6是依照本发明第二实施例的图3中步骤330的子步骤的流程图。FIG. 6 is a flowchart of sub-steps of step 330 in FIG. 3 according to a second embodiment of the present invention.

具体实施方式 Detailed ways

请参照图2A至2D，其是双位存储单元的四种位状态组合的示意图。双位存储单元200例如为氮化物只读存储器存储单元(Nitride Read-Only Memorycell)，并包括控制端G、第一端D、第二端S以及氧化物-氮化物-氧化物(oxide-nitride-oxide，ONO)结构210。控制端G、第一端D及第二端S是以分别为栅极、漏极及源极为例做说明。此外，双位存储单元200于邻近第一端D及第二端S之处分别具有第一位储存节B1及第二位储存节B2(以虚线框表示)。Please refer to FIGS. 2A to 2D , which are schematic diagrams of combinations of four bit states of a double-bit memory cell. The double-bit memory cell 200 is, for example, a Nitride Read-Only Memory cell (Nitride Read-Only Memorycell), and includes a control terminal G, a first terminal D, a second terminal S, and an oxide-nitride-oxide (oxide-nitride) -oxide, ONO) structure 210. The control terminal G, the first terminal D, and the second terminal S are illustrated by taking the gate, the drain, and the source respectively as an example. In addition, the double-bit memory cell 200 has a first bit storage node B1 and a second bit storage node B2 adjacent to the first terminal D and the second terminal S respectively (indicated by a dashed box).

其中，如图2A至2D依序所示，第一位储存节B1及第二位储存节B2的位状态分别为逻辑「1」及「1」(图2A)、「1」及「0」(图2B)、「0」及「1」(图2C)以及「0」及「0」(图2D)。且以斜线表示0N0结构210中捕捉有注入电荷，而使对应的位储存节被编程为逻辑「0」。Wherein, as shown in sequence in Figures 2A to 2D, the bit states of the first bit storage section B1 and the second bit storage section B2 are logic "1" and "1" (Figure 2A), "1" and "0" respectively (Fig. 2B), "0" and "1" (Fig. 2C), and "0" and "0" (Fig. 2D). And the oblique line indicates that the injected charges are trapped in the 0N0 structure 210, so that the corresponding bit storage node is programmed as logic "0".

请参照图3，其是依照本发明的读取双位存储单元200的方法的流程图。本发明主要是分别对双位存储单元200的第一端D及第二端S进行读取动作，并以其对应的输出电流值来同时决定出双位存储单元200所储存的两个位状态。Please refer to FIG. 3 , which is a flowchart of a method for reading a double-bit memory cell 200 according to the present invention. The present invention mainly reads the first end D and the second end S of the double-bit memory unit 200 respectively, and simultaneously determines the two bit states stored in the double-bit memory unit 200 by using the corresponding output current value. .

如图3所示，首先，开始进入步骤310中，分别施加控制电压Vg及读取电压Vr至控制端G及第一端D，且将第二端S接地，以测量第一端D的第一输出电流值I_1。接着，进入步骤320中，分别施加控制电压Vg及读取电压Vr至控制端G及第二端S，且将第一端D接地，以测量第二端S的第二输出电流值I_2。最后，进入步骤330中，根据第一输出电流值I_1及第二输出电流值I_2来同时读取第一位储存节B1及第二位储存节B2的位状态，而结束读取双位存储单元200的方法。As shown in FIG. 3 , first, enter step 310, respectively apply the control voltage Vg and the read voltage Vr to the control terminal G and the first terminal D, and ground the second terminal S to measure the first terminal D. - Output current value I_1. Next, enter step 320, apply the control voltage Vg and the read voltage Vr to the control terminal G and the second terminal S respectively, and ground the first terminal D to measure the second output current value I_2 of the second terminal S. Finally, enter step 330, read the bit states of the first bit storage node B1 and the second bit storage node B2 simultaneously according to the first output current value I_1 and the second output current value I_2, and finish reading the double-bit memory cell 200 ways.

至于步骤330中的具体判读方式，以下再结合附图予以详细说明。然而下列文字与图中标号仅为说明之用，并不会限定本发明的欲保护范围。As for the specific interpretation method in step 330, it will be described in detail below in conjunction with the accompanying drawings. However, the following words and symbols in the figure are for illustration only, and will not limit the protection scope of the present invention.

请参照图4A至4E，图4A至4D分别绘示图2A至2D的双位存储单元200的四种位状态组合下第一输出电流值I_1及第二输出电流值I_2随控制电压Vg变化的曲线图，图4E是图4A至4D中的第二输出电流值I_2随控制电压Vg变化的曲线图。例如，于步骤310及320中，施加1.5伏特(V)的读取电压Vr及3V至5V的控制电压Vg，并测量第一输出电流值I_1及第二输出电流值I_2的对应变化。此外，为说明方便，各图中的纵轴是取输出电流值I的对数值。Please refer to FIGS. 4A to 4E. FIGS. 4A to 4D respectively illustrate the change of the first output current value I_1 and the second output current value I_2 with the control voltage Vg under the four bit state combinations of the double-bit memory cell 200 in FIGS. 2A to 2D. 4E is a graph showing the variation of the second output current value I_2 with the control voltage Vg in FIGS. 4A to 4D . For example, in steps 310 and 320 , a read voltage Vr of 1.5 volts (V) and a control voltage Vg of 3V to 5V are applied, and the corresponding changes of the first output current value I_1 and the second output current value I_2 are measured. In addition, for the convenience of description, the vertical axis in each figure is the logarithmic value of the output current value I.

其中，如分别对应图2A及图2D的图4A及4D所示，由于两储存位节B1及B2其位状态的对称性，第一输出电流值I_1及第二输出电流值I_2相等；但由于编程动作造成的临界电压(threshold voltage)变化，图4D中第一输出电流值I_1及第二输出电流值I_2的图形曲线发生一偏移现象。而如分别对应图2B及图2C的图4B及4C所示，仅有一位储存节被执行编程动作，因此仅有对应的第一输出电流值I_1或第二输出电流值I_2的图形曲线发生偏移现象。Wherein, as shown in FIG. 4A and 4D corresponding to FIG. 2A and FIG. 2D respectively, due to the symmetry of the bit states of the two storage bit nodes B1 and B2, the first output current value I_1 and the second output current value I_2 are equal; but due to The threshold voltage (threshold voltage) change caused by the programming action causes a shift phenomenon in the graphic curves of the first output current value I_1 and the second output current value I_2 in FIG. 4D . However, as shown in FIG. 4B and 4C corresponding to FIG. 2B and FIG. 2C respectively, only one bit storage section is programmed, so only the corresponding first output current value I_1 or the second output current value I_2 is biased. shift phenomenon.

此外，如图4E所示，是将图4A至4D中的第二输出电流值I_2随控制电压Vg变化的四曲线做一比较，并以I_2(11)、I_2(01)、I_2(10)及I_2(00)分别代表图4A至4D中的第二输出电流值I_2。当然，I_2(11)及I_2(00)也可分别视为图4A及4D中的第一输出电流值I_1，而I_2(01)及I_2(10)则可分别视为图4C及4B中的第一输出电流值I_1。可看出第二位效应造成对应图4B的曲线I_2(01)与对应图4A的曲线I_2(11)不相同，以及对应图4C的曲线I_2(10)与对应图4D的曲线I_2(00)不相同。此时，例如以传统的逆向读取对第一位储存节B1进行判读，即以一控制电压Vg_0下对应的第二输出电流值I_2与一参考电流值Ir作大小比较而读取为位状态「1」或「0」时，log(Ir)显然必须落于曲线I_2(01)及I_2(10)之间对应的纵轴范围内，如图4E所示。借此，才能在第二位效应下，正确判读出第一位储存节B1的位状态。In addition, as shown in FIG. 4E, the four curves of the second output current value I_2 in FIGS. 4A to 4D are compared with the control voltage Vg, and I_2(11), I_2(01), I_2(10) and I_2(00) respectively represent the second output current value I_2 in FIGS. 4A to 4D . Of course, I_2(11) and I_2(00) can also be regarded as the first output current value I_1 in Fig. 4A and 4D respectively, and I_2(01) and I_2(10) can be regarded as the first output current value I_1 in Fig. 4C and 4B respectively. The first output current value I_1. It can be seen that the second bit effect causes the curve I_2(01) corresponding to Figure 4B to be different from the curve I_2(11) corresponding to Figure 4A, and the curve I_2(10) corresponding to Figure 4C is different from the curve I_2(00) corresponding to Figure 4D Are not the same. At this time, for example, the first bit storage node B1 is interpreted by traditional reverse reading, that is, the second output current value I_2 corresponding to a control voltage Vg_0 is compared with a reference current value Ir to read the bit state When "1" or "0", log(Ir) must obviously fall within the range of the vertical axis corresponding between the curves I_2(01) and I_2(10), as shown in FIG. 4E . In this way, the bit state of the first bit storage section B1 can be correctly judged under the second bit effect.

至此，本发明主要是利用上述图4A至4D中，第一输出电流值I_1及第二输出电流值I_2两者间的图形曲线关系，于步骤330中同时判读出第一位储存节B1及第二位储存节B2的位状态，并可增加参考电流值Ir的范围。以下是列举较佳实施例做详细说明。So far, the present invention mainly utilizes the graph-curve relationship between the first output current value I_1 and the second output current value I_2 in the above-mentioned FIGS. The bit state of the node B2 is stored in two bits, and the range of the reference current value Ir can be increased. The following is a detailed description of preferred embodiments.

第一实施例first embodiment

请参照图5，其是依照本发明第一实施例的图3中步骤330的子步骤的流程图。并以在图4E的控制电压Vg_0下对应的第一输出电流值I_1及第二输出电流值I_2为例。首先，于步骤531中，是判断第一输出电流值I_1及第二输出电流值I_2的一大小关系。此时，可得三种大小关系：即I_1＞I_2、I_1＜I_2或I_1＝I_2。Please refer to FIG. 5 , which is a flow chart of the sub-steps of step 330 in FIG. 3 according to the first embodiment of the present invention. And take the first output current value I_1 and the second output current value I_2 corresponding to the control voltage Vg_0 in FIG. 4E as an example. First, in step 531 , a magnitude relationship between the first output current value I_1 and the second output current value I_2 is determined. At this time, three magnitude relationships can be obtained: namely I_1>I_2, I_1<I_2 or I_1=I_2.

如图5所示，当第一输出电流值I_1大于第二输出电流值I_2时，是进入步骤532a中，读取第一位储存节B1及第二位储存节B2的位状态分别为「0」及「1」。而当第一输出电流值I_1小于第二输出电流值I_2时，是进入步骤532b中，读取第一位储存节B1及第二位储存节B2的位状态分别为「1」及「0」。As shown in FIG. 5, when the first output current value I_1 is greater than the second output current value I_2, enter step 532a, and read the bit states of the first bit storage node B1 and the second bit storage node B2 as "0" respectively. " and "1". And when the first output current value I_1 is smaller than the second output current value I_2, enter step 532b, read the bit states of the first bit storage node B1 and the second bit storage node B2 as "1" and "0" respectively .

再者，当第一输出电流值I_1及第二输出电流值I_2相等时，是进入步骤532c中，判断第一输出电流值I_1及第二输出电流值I_2是否大于一第一默认值Ir_1。若I_1＝I_2大于Ir_1，则进入步骤533a中，读取第一位储存节B1及第二位储存节B2的位状态分别为「1」及「1」。反之，若I_1＝I_2未大于Ir_1，则进入步骤533b中，判断第一输出电流值I_1及第二输出电流值I_2是否小于一第二默认值Ir_2。若I_2＝I_2小于Ir_2，则进入步骤534中，读取第一位储存节B1及第二位储存节B2的位状态分别为「0」及「0」。Furthermore, when the first output current value I_1 and the second output current value I_2 are equal, enter step 532c to determine whether the first output current value I_1 and the second output current value I_2 are greater than a first default value Ir_1. If I_1=I_2 is greater than Ir_1, then enter step 533a, and read the bit states of the first bit storage section B1 and the second bit storage section B2 as "1" and "1" respectively. On the contrary, if I_1=I_2 is not greater than Ir_1, then enter step 533b to determine whether the first output current value I_1 and the second output current value I_2 are smaller than a second default value Ir_2. If I_2=I_2 is less than Ir_2, then enter step 534 to read the bit states of the first bit storage section B1 and the second bit storage section B2 as "0" and "0" respectively.

由上可知，判断出I_1＞I_2或I_1＜I_2之后，借由图4B及4C中I_1及I_2的曲线关系，可简单地同时判读出第一位储存节B1及第二位储存节B2的位状态。而对于I_1＝I_2的情形，由图4A及4D还可知，可如传统的作法取一参考电流值来对图4E中曲线I_2(11)及I_2(00)加以判别。但由于已经排除了I_1＞I_2及I_1＜I_2的情形，也即图4E中曲线I_2(01)及I_2(10)的情形，参考电流值的范围可从曲线I_2(01)及I_2(10)之间扩大至I_2(11)及I_2(00)之间。例如，可设定Ir_1使log(Ir_1)落于图4E中曲线I_2(11)及I_2(01)之间对应的纵轴范围使之有更大的读取感测窗口。It can be seen from the above that after judging I_1>I_2 or I_1<I_2, by means of the curve relationship between I_1 and I_2 in Figures 4B and 4C, the bits of the first storage section B1 and the second storage section B2 can be easily and simultaneously read out state. As for the situation of I_1=I_2, it can also be known from FIGS. 4A and 4D that a reference current value can be taken as the traditional method to judge the curves I_2(11) and I_2(00) in FIG. 4E. But since the situations of I_1>I_2 and I_1<I_2 have been excluded, that is, the situation of curves I_2(01) and I_2(10) in Fig. 4E, the range of reference current value can be from curves I_2(01) and I_2(10) between I_2(11) and I_2(00). For example, Ir_1 can be set so that log(Ir_1) falls within the range of the vertical axis corresponding to curves I_2(11) and I_2(01) in FIG. 4E to have a larger read sensing window.

同样，也可设定Ir_2使log(Ir_2)落于图4E中曲线I_2(10)及I_2(00)之间。或者，直接设定Ir_2＝Ir_1，即I_1＝I_2小于Ir_1时，即读取第一位储存节B1及第二位储存节B2的位状态分别为「0」及「0」。当然，视使用需求或其它考虑，也能改变「1」及「1」与「0」及「0」两种位状态组合的判断顺序。例如，先于步骤532c中判断第一输出电流值I_1及第二输出电流值I_2是否小于第二默认值Ir_2，若是，则可读取为「0」及「0」；若否，便继续判断是否大于第一默认值Ir_1，以读取出「1」及「1」。Similarly, Ir_2 can also be set so that log(Ir_2) falls between the curves I_2(10) and I_2(00) in FIG. 4E. Alternatively, directly set Ir_2=Ir_1, that is, when I_1=I_2 is smaller than Ir_1, the bit states of the first bit storage section B1 and the second bit storage section B2 are read as "0" and "0" respectively. Of course, depending on usage requirements or other considerations, the judgment sequence of the two bit state combinations of "1" and "1" and "0" and "0" can also be changed. For example, first in step 532c, it is judged whether the first output current value I_1 and the second output current value I_2 are smaller than the second default value Ir_2, if yes, it can be read as "0" and "0"; if not, continue to judge Whether it is greater than the first default value Ir_1 to read "1" and "1".

第二实施例second embodiment

请参照图6，其是依照本发明第二实施例的图3中步骤330的子步骤的流程图。同样以在图4E的控制电压Vg_0下对应的第一输出电流值I_1及第二输出电流值I_2为例。首先，于步骤631中，判断第一输出电流值I_1及第二输出电流值I_2是否皆大于一第一默认值Ir_1’。若是，则进入步骤632a中，读取第一位储存节B1及第二位储存节B2的位状态分别为「1」及「1」。Please refer to FIG. 6 , which is a flowchart of sub-steps of step 330 in FIG. 3 according to a second embodiment of the present invention. Also take the first output current value I_1 and the second output current value I_2 corresponding to the control voltage Vg_0 in FIG. 4E as an example. First, in step 631, it is judged whether the first output current value I_1 and the second output current value I_2 are both greater than a first default value Ir_1'. If yes, enter step 632a to read the bit states of the first bit storage section B1 and the second bit storage section B2 as "1" and "1" respectively.

如图6所示，当第一输出电流值I_1及第二输出电流值I_2未皆大于Ir_1’时，则进入步骤632b中，判断第一输出电流值I_1及第二输出电流值I_2是否皆小于一第二默认值Ir_2’。若是，则进入步骤633a中，读取第一位储存节B1及第二位储存节B2的位状态分别为「0」及「0」。As shown in FIG. 6, when both the first output current value I_1 and the second output current value I_2 are not greater than Ir_1', enter step 632b to determine whether the first output current value I_1 and the second output current value I_2 are both less than A second default value Ir_2'. If yes, enter step 633a to read the bit states of the first bit storage section B1 and the second bit storage section B2 as "0" and "0" respectively.

再者，当第一输出电流值I_1及第二输出电流值I_2未皆小于Ir_2’时，是进入步骤633b中，判断第一输出电流值I_1是否大于第二输出电流值I_2。若是，则进入步骤634a中，读取第一位储存节B1及第二位储存节B2的位状态分别为「0」及「1」。若否，则进入步骤634b中，读取第一位储存节B1及第二位储存节B2的位状态分别为「1」及「0」。Furthermore, when both the first output current value I_1 and the second output current value I_2 are not less than Ir_2', enter step 633b to determine whether the first output current value I_1 is greater than the second output current value I_2. If yes, enter step 634a to read the bit states of the first bit storage section B1 and the second bit storage section B2 as "0" and "1" respectively. If not, go to step 634b to read the bit states of the first bit storage section B1 and the second bit storage section B2 as "1" and "0" respectively.

由上可知，与第一实施例不同之处在于，第二实施例是先判读出「1」及「1」与「0」及「0」两种位状态组合。以步骤631为例，是利用除了「1」及「1」外的其它三种位状态组合皆至少有一位储存节被执行编程动作，即I_1及I_2中至少有一个图形曲线发生偏移现象，来先加以区分判读出是否为「1」及「1」。接着，同样以偏移现象来区分「0」及「0」与另外两种位状态组合。若排除了「1」及「1」与「0」及「0」两种情形后，再以I_1及I_2之间的大小关系即可判读出「0」及「1」与「1」及「0」两种情形。It can be seen from the above that the difference from the first embodiment is that the second embodiment first judges the two bit state combinations of "1" and "1" and "0" and "0". Taking step 631 as an example, it uses at least one storage section to execute the programming action in the other three bit state combinations except "1" and "1", that is, at least one of the graph curves in I_1 and I_2 is shifted, Let's first distinguish and judge whether it is "1" or "1". Next, "0" and "0" are also distinguished from the other two bit state combinations by using the offset phenomenon. If the two situations of "1" and "1" and "0" and "0" are excluded, the relationship between "0" and "1" and "1" and "0" can be judged based on the size relationship between I_1 and I_2. 0" in two situations.

此外，Ir_1’及Ir_2’的设定范围可如同第一实施例的Ir_1及Ir_2，或可设定Ir_1’＝Ir_2’。但需注意的是，Ir_1’必须落于图4E中曲线I_2(10)与I_2(11)之间的范围，Ir_2’则需落于曲线I_2(01)与I_2(00)之间的范围，如此才能于步骤631及632b中达成正确的判断区分。而「1」及「1」与「0」及「0」两种位状态组合的判断顺序也可视使用需求或其它考虑做改变，例如于步骤631先以Ir_2’来对「0」及「0」与其它三种位状态组合做一区别；接着，再以Ir_1’来区分「1」及「1」与另外两种位状态组合。In addition, the setting ranges of Ir_1' and Ir_2' can be the same as those of Ir_1 and Ir_2 in the first embodiment, or Ir_1'=Ir_2' can be set. However, it should be noted that Ir_1' must fall within the range between curves I_2(10) and I_2(11) in Figure 4E, and Ir_2' must fall within the range between curves I_2(01) and I_2(00). Only in this way can a correct judgment and distinction be achieved in steps 631 and 632b. And the judging order of "1" and "1" and "0" and "0" bit state combinations can also be changed according to the use requirements or other considerations. 0" is distinguished from the other three bit state combinations; then, "1" and "1" are distinguished from the other two bit state combinations by Ir_1'.

然本发明所属技术领域中具有通常知识者当可明了，本发明的技术并不局限于此。例如，因为实际上可能由于工艺上的因素或测量上的误差，使得图4A或4D的位状态组合其输出电流值并没有表现出预期的对称性；也即，如图4A中的I_1与I_2实际的测量结果可能具有一微小差距。此时，图5的步骤531中，即可允许两者间有一弹性范围而仍判断为I_1＝I_2。而第一及第二实施例中的第一默认值及第二默认值也可相应作微调。只要是利用双位存储单元于两种读取方向时的两输出电流值来一起作判读，达到同时决定出其所储存的两个位状态的目的，皆不脱离本发明的技术范围。However, those with ordinary knowledge in the technical field of the present invention should understand that the technology of the present invention is not limited thereto. For example, due to process factors or measurement errors, the output current value of the bit state combination in Figure 4A or 4D does not show the expected symmetry; that is, I_1 and I_2 in Figure 4A Actual measurements may vary slightly. At this time, in step 531 of FIG. 5 , it is possible to allow a flexible range between the two and still determine that I_1=I_2. The first default value and the second default value in the first and second embodiments can also be fine-tuned accordingly. As long as the two output current values of the double-bit memory cell in the two reading directions are used to judge together to achieve the purpose of simultaneously determining the two stored bit states, it does not depart from the technical scope of the present invention.

本发明上述实施例所揭示的读取双位存储单元的方法，有别于传统上对两个位储存节分别独立读取其位状态，是利用双位存储单元于两种读取方向时的两输出电流值，其两者间的大小关系及与预设的参考值作比较，来同时决定出其所储存的两个位状态。借此，能更正确判读出双位存储单元所具有的位状态组合，并有效增加读取感测窗口。The method for reading a double-bit memory cell disclosed in the above-mentioned embodiments of the present invention is different from the traditional way of independently reading the bit states of two bit storage sections, and uses the double-bit memory cell in two reading directions. The two output current values are compared with the preset reference value to determine the two stored bit states at the same time. Thereby, the bit state combination of the double-bit memory cell can be read out more correctly, and the read sensing window can be effectively increased.

综上所述，虽然本发明已以较佳实施例揭示如上，然而其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种等同的更动与润饰。因此，本发明的保护范围当视后附的本申请权利要求范围所界定的为准。In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the technical field to which the present invention belongs may make various equivalent changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims of the application.