CN101218651B - Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells - Google Patents

将一组非易失性存储元件划分为子组进行软编程，以便更完全地软编程较慢的软编程元件。所述整个组的元件经软编程，直到被验证为经软编程为止(或直到第一子组元件被验证为经软编程，同时从验证中排除第二子组为止)。在所述组被验证为经软编程之后，第一子组元件被抑制进一步软编程，同时对第二子组元件实施额外的软编程。第二子组可包含较慢的软编程元件。第二子组可接着经历软编程验证，同时从验证中排除所述第一子组。针对所述第二子组的软编程和验证可持续，直到其被验证为经软编程为止。取决于哪一子组正经软编程和验证，可使用不同的步长大小以增加软编程信号的大小。

A group of non-volatile storage elements is divided into subgroups for soft programming to more completely soft program slower soft programming elements. The entire set of elements is soft programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, the first subset of elements are inhibited from further soft programming while additional soft programming is performed on the second subset of elements. The second subset may contain slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verification for the second subset continues until it is verified as soft programmed. Depending on which subset is being soft programmed and verified, different step sizes can be used to increase the size of the soft programming signal.

非易失性存储器系统及软编程方法Non-volatile memory system and soft programming method

优先权priority

本申请案主张2005年3月31日申请的Hemink等人的题为“NON-VOLATILEMEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION”的第60/667,043号美国临时专利申请案的优先权，所述申请案以全文引用的方式并入本文中。  This application claims priority to U.S. Provisional Patent Application No. 60/667,043, entitled "NON-VOLATILEMEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION," filed March 31, 2005, by Hemink et al. It is incorporated herein by reference in its entirety. the

相关申请案的交叉参考Cross References to Related Applications

以下申请案是交叉参考的且以全文引用的方式并入本文中：  The following applications are cross-referenced and incorporated herein by reference in their entirety:

2005年12月6日申请的Hemink等人的题为“ERASING NON-VOLATILE MEMORYUSING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OFMEMORY CELLS”的第11/296,055号(代理人案号SAND-01066US0)的美国专利申请案；  U.S. Patent Application No. 11/296,055 (Attorney Docket No. SAND-01066US0) entitled "ERASING NON-VOLATILE MEMORYUSING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OFMEMORY CELLS" by Hemink et al., filed December 6, 2005 ;

2005年12月6日申请的Hemink等人的题为“SYSTEMS FOR ERASINGNON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONALERASING OF SUBSETS OF MEMORY CELLS”的第11/296,028号(代理人案号SAND-01066US1)美国专利申请案；  U.S. Patent Application No. 11/296,028 (Attorney Docket No. SAND-01066US1) entitled "SYSTEMS FOR ERASINGNON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONALERASING OF SUBSETS OF MEMORY CELLS" by Hemink et al., filed December 6, 2005 Case;

2005年12月6日申请的Hemink等人的题为“SYSTEMS FOR SOFT PROGRAMMINGNONVOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION ANDADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS”的第11/296,071号(代理人案号SAND-01 066US3)的美国专利申请案；  11/296,071 (Attorney Docket No. SAND-031) entitled "SYSTEMS FOR SOFT PROGRAMMINGNONVOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION AND ADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS" by Hemink et al., filed December 6, 2005 patent applications;

2005年12月6日申请的Masaaki Higashitani的题为“ERASING NON-VOLATILEMEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FORSLOWER ERASING MEMORY CELLS”的第11/295,755号(代理人案号SAND-01054US0)的美国专利申请案；以及  U.S. Patent Application No. 11/295,755, entitled "ERASING NON-VOLATILEMEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FORSLOWER ERASING MEMORY CELLS," filed December 6, 2005 by Masaaki Higashitani (Attorney Docket No. SAND-01054US0) ;as well as

2005年12月6日申请的Masaaki Higashitani的题为“SYSTEMS FOR ERASINGNON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TOOMPENSATE FOR SLOWER ERASING MEMORY CELLS”的第11/296,032号(代理人案号SAND-01054US2)的美国专利申请案。  U.S. Patent No. 11/296,032 (Attorney Docket No. SAND-01054) entitled "SYSTEMS FOR ERASINGNON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TOOMPENSATE FOR SLOWER ERASING MEMORY CELLS" filed December 6, 2005 by Masaaki Higashitani application case. the

技术领域technical field

本发明大体上涉及用于擦除非易失性存储器装置的半导体技术。  The present invention generally relates to semiconductor technology for erasing non-volatile memory devices. the

背景技术 Background technique

半导体存储器装置已变得越来越普遍地用于各种电子装置。举例来说，非易失性半导体存储器用于蜂窝式电话、数码相机、个人数字助理、移动计算装置、非移动计算装置和其它装置。电可擦可编程只读存储器(EEPROM)(包含快闪EEPROM)和电可编程只读存储器(EPROM)属于最普遍的非易失性半导体存储器。  Semiconductor memory devices have become more and more commonly used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read-Only Memory (EEPROM) (including flash EEPROM) and Electrically Programmable Read-Only Memory (EPROM) are among the most common non-volatile semiconductor memories. the

快闪存储器系统的一个实例使用夹在两个选择栅极之间的NAND结构，其包含串联布置多个晶体管。串联的晶体管和选择栅极称为NAND串。图1是展示一个NAND串的顶视图。图2是其等效电路。图1和2中描绘的NAND串包含四个晶体管100、102、104和106，其串联且夹在第一选择栅极120与第二选择栅极122之间。选择栅极120将NAND串连接到位线126。选择栅极122将NAND串连接到源极线128。通过经由选择线SGD向控制栅极120CG施加适当电压来控制选择栅极120。通过经由选择线SGS向控制栅极122CG施加适当电压来控制选择栅极122。晶体管100、102、104和106中的每一者均包含控制栅极和浮动栅极，从而形成存储器单元的栅极元件。举例来说，晶体管100具有控制栅极100CG和浮动栅极100FG。晶体管102包含控制栅极102CG和浮动栅极102FG。晶体管104包含控制栅极104CG和浮动栅极104FG。晶体管106包含控制栅极106CG和浮动栅极106FG。控制栅极100CG连接到字线WL3，控制栅极102CG连接到字线WL2，控制栅极104CG连接到字线WL1，且控制栅极106CG连接到字线WL0。  One example of a flash memory system uses a NAND structure sandwiched between two select gates that includes multiple transistors arranged in series. Transistors and select gates connected in series are called NAND strings. Figure 1 is a top view showing a NAND string. Figure 2 is its equivalent circuit. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100 , 102 , 104 , and 106 in series and sandwiched between a first select gate 120 and a second select gate 122 . Select gate 120 connects the NAND string to bit line 126 . Select gate 122 connects the NAND string to source line 128 . Select gate 120 is controlled by applying an appropriate voltage to control gate 120CG via select line SGD. Select gate 122 is controlled by applying an appropriate voltage to control gate 122CG via select line SGS. Each of transistors 100, 102, 104, and 106 includes a control gate and a floating gate, forming the gate element of the memory cell. For example, transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes control gate 102CG and floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0. the

应注意，尽管图1和2展示NAND串中的四个存储器单元，但仅提供四个晶体管的使用作为实例。NAND串可具有少于四个存储器单元或四个以上存储器单元。举例来说，一些NAND串将包含8个存储器单元、16个存储器单元、32个存储器单元等。本文的论述不限于NAND串中的任何特定数目的存储器单元。  It should be noted that although Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string. the

用于使用NAND结构的快闪存储器系统的典型结构将包含若干NAND串。举例来说，图3展示具有更多NAND串的存储器阵列的三个NAND串202、204和206。图3的NAND串中的每一者均包含两个选择晶体管或栅极和四个存储器单元。举例来说，NAND串202包含选择晶体管220和230，以及存储器单元222、224、226和228。NAND串204包含选择晶体管240和250，以及存储器单元242、244、246和248。每一串通过一个选择栅极(例如，选择栅极230和选择栅极250)连接到源极线。选择线SGS用于控制源极侧选择栅极。各个NAND串通过由选择线SGD控制的选择栅极220、240等连接到相应的 位线。在其它实施例中，选择线不一定需要共用。字线WL3连接到用于存储器单元222和存储器单元242的控制栅极。字线WL2连接到用于存储器单元224和存储器单元244的控制栅极。字线WL1连接到用于存储器单元226和存储器单元246的控制栅极。字线WL0连接到用于存储器单元228和存储器单元248的控制栅极。可见，位线和相应的NAND串包括存储器单元阵列的列。字线(WL3、WL2、WL1和WL0)包括阵列的行。每一字线连接行中的每一存储器单元的控制栅极。举例来说，字线WL2连接到用于存储器单元224、244和252的控制栅极。  A typical structure for a flash memory system using a NAND structure will contain several NAND strings. For example, Figure 3 shows three NAND strings 202, 204, and 206 of a memory array with more NAND strings. Each of the NAND strings of Figure 3 includes two select transistors or gates and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 , and memory cells 222 , 224 , 226 and 228 . NAND string 204 includes select transistors 240 and 250 , and memory cells 242 , 244 , 246 and 248 . Each string is connected to a source line through a select gate (eg, select gate 230 and select gate 250). The select line SGS is used to control the source side select gates. Each NAND string is connected to a corresponding bit line through select gates 220, 240, etc. controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be shared. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242 . Word line WL2 is connected to the control gates for memory cell 224 and memory cell 244 . Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246 . Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248 . It can be seen that the bit lines and corresponding NAND strings comprise the columns of the memory cell array. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. Word line WL2 is connected to the control gates for memory cells 224 , 244 and 252 , for example. the

每一存储器单元可存储数据(模拟或数字)。当存储一位数字数据时，存储器单元的可能阈值电压的范围被划分为两个范围，其指定为逻辑数据“1”和“0”。在NAND型快闪存储器的一个实例中，阈值电压在存储器单元被擦除之后为负，且定义为逻辑“1”。编程操作之后的阈值电压为正且定义为逻辑“0”。当阈值电压为负且通过向控制栅极施加0伏来尝试读取时，存储器单元将接通以指示正存储逻辑1。当阈值电压为正且通过向控制栅极施加0伏来尝试读取操作时，存储器单元将不接通，其指示存储逻辑0。存储器单元也可存储多级信息，例如多位的数字数据。在存储多级数据的情况下，可能阈值电压的范围被划分为数据级的数目。举例来说，如果存储四个级的信息，那么将存在四个阈值电压范围，指定为数据值“11”、“10”、“01”和“00”。在NAND型存储器的一个实例中，擦除操作之后的阈值电压为负且定义为“11”。三个不同的正阈值电压用于状态“10”、“01”和“00”。  Each memory cell can store data (analog or digital). When storing one bit of digital data, the range of possible threshold voltages of a memory cell is divided into two ranges, designated as logical data "1" and "0." In one example of NAND-type flash memory, the threshold voltage is negative and is defined as a logic "1" after the memory cell is erased. The threshold voltage after a program operation is positive and defined as logic "0". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate a logical one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, indicating that a logic zero is stored. Memory cells can also store multiple levels of information, such as multiple bits of digital data. In the case of storing multi-level data, the range of possible threshold voltages is divided into the number of data levels. For example, if four levels of information are stored, there will be four threshold voltage ranges, designated as data values "11", "10", "01" and "00". In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as "11". Three different positive threshold voltages are used for states "10", "01" and "00". the

NAND型快闪存储器及其操作的相关实例在以下美国专利/专利申请案中提供：第5,570,315号美国专利；第5,774,397号美国专利；第6,046,935号美国专利；第6,456,528号美国专利；以及第09/893,277号(公开号US2003/0002348)美国专利申请案，所述专利全部以引用的方式并入本文中。  Relevant examples of NAND-type flash memory and its operation are provided in the following U.S. patents/patent applications: U.S. Patent No. 5,570,315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935; U.S. Patent No. 6,456,528; US Patent Application No. 893,277 (Pub. No. US2003/0002348), which is incorporated herein by reference in its entirety. the

当对快闪存储器单元进行编程时，将编程电压施加到控制栅极(经由选择的字线)且位线接地。来自p阱的电子注入到浮动栅极中。当电子在浮动栅极中积聚时，浮动栅极会变成带负电且单元的阈值电压上升。浮动栅极充电且单元的阈值电压可指示对应于存储的数据的特定状态。  When programming a flash memory cell, a program voltage is applied to the control gate (via a selected word line) and the bit line is grounded. Electrons from the p-well are injected into the floating gate. As electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the cell rises. The floating gate charges and the cell's threshold voltage can indicate a particular state corresponding to the stored data. the

为了擦除NAND型快闪存储器的存储器单元，电子从每一存储器单元的浮动栅极转移到阱区和衬底。通常，将一个或一个以上高电压(例如，～16V-20V)擦除脉冲施加到阱区以将从每一存储器单元的浮动栅极离开的电子吸引到阱区。每一存储器单元的字线接地或供以0V以在隧道氧化物区上产生高电位从而吸引电子。如果在施加擦除电压脉 冲之后未擦除NAND串的每一存储器单元，那么脉冲的大小可增加并再施加到NAND串，直到每一存储器单元被擦除为止。在脉冲之间擦除电压增加的量通常称为擦除电压的步长大小。  To erase the memory cells of a NAND-type flash memory, electrons are transferred from the floating gate of each memory cell to the well region and the substrate. Typically, one or more high voltage (eg, -16V-20V) erase pulses are applied to the well region to attract electrons exiting the floating gate of each memory cell to the well region. The word line of each memory cell is grounded or supplied with 0V to generate a high potential on the tunnel oxide region to attract electrons. If every memory cell of the NAND string is not erased after applying the erase voltage pulse, the size of the pulse can be increased and reapplied to the NAND string until every memory cell is erased. The amount by which the erase voltage increases between pulses is often referred to as the erase voltage step size. the

使用现有技术的典型的擦除操作可导致NAND串中存储器单元之间的不同擦除速率。一些存储器单元可比其它存储器单元更快或更慢地到达用于擦除状态的目标阈值电压电平。这可导致较快擦除存储器单元的过度擦除，因为其将持续经受经施加以充分擦除NAND串的较慢存储器单元的擦除电压。因此，不同的擦除速率可导致存储器单元或NAND串的较短循环寿命。典型的擦除操作也可导致NAND串的存储器单元之间的完全不同的阈值电压。也就是说，当与所述串或装置的其它存储器单元相比时，NAND串的一个或一个以上存储器单元可在施加一个或一个以上擦除电压脉冲之后具有不同的阈值电压。为克服此效应，已使用通常称为软编程的技术来调节擦除之后一个或一个以上存储器单元的阈值电压。软编程包含向一个或一个以上存储器单元施加相对低的编程电压，其低于用于实际编程的电压。软编程通常包含施加编程电压作为以编程电压脉冲每次施加之间的步长大小增加的一系列脉冲。软编程升高存储器单元的阈值电压，以便使全体经擦除存储器单元的阈值电压分布变窄和/或升高。然而软编程可增加编程和擦除时间。  Typical erase operations using prior art techniques can result in different erase rates between memory cells in a NAND string. Some memory cells may reach the target threshold voltage level for the erased state faster or slower than other memory cells. This can lead to over-erasing of the faster erasing memory cells as they will continue to experience the erase voltage applied to adequately erase the slower memory cells of the NAND string. Therefore, different erase rates can result in a shorter cycle life of the memory cells or NAND strings. Typical erase operations can also result in disparate threshold voltages between memory cells of a NAND string. That is, one or more memory cells of a NAND string may have a different threshold voltage after application of one or more erase voltage pulses when compared to other memory cells of the string or device. To overcome this effect, a technique commonly referred to as soft programming has been used to adjust the threshold voltage of one or more memory cells after erasure. Soft programming involves applying a relatively low programming voltage to one or more memory cells, which is lower than the voltage used for actual programming. Soft programming generally involves applying the programming voltage as a series of pulses increasing in step size between each application of the programming voltage pulse. Soft programming raises the threshold voltage of memory cells so that the threshold voltage distribution of the population of erased memory cells is narrowed and/or raised. Soft programming, however, can increase program and erase times. the

另外，传统的软编程可经受不同的存储器单元之间完全不同的性质的相同影响中的某些影响。可能擦除缓慢的相同存储器单元也可能软编程缓慢。在软编程结束时这些较慢软编程单元可比NAND串的其它单元具有更低的擦除阈值电压。  In addition, traditional soft programming may suffer from some of the same effects of disparate properties between different memory cells. The same memory cells that may be slow to erase may also be slow to soft program. These slower soft programmed cells may have a lower erased threshold voltage than other cells of the NAND string at the end of soft programming. the

发明内容 Contents of the invention

本文描述的技术属于用于以提供更一致的擦除阈值电压的方式对非易失性存储器装置进行擦除和/或软编程的技术。根据一个实施例，提供一种系统，其考虑在擦除和软编程操作期间一个或一个以上存储器单元的个别特性、擦除行为和软编程行为。  Techniques described herein are techniques for erasing and/or soft programming non-volatile memory devices in a manner that provides more consistent erase threshold voltages. According to one embodiment, a system is provided that takes into account individual characteristics, erase behavior, and soft programming behavior of one or more memory cells during erase and soft programming operations. the

可将一组非易失性存储元件(例如，NAND串)划分为子组进行擦除，以便避免过度擦除较快擦除存储元件。整个所述组元件经擦除，直到所述组元件的第一子组被验证为经擦除为止。所述第一子组可包含较快擦除元件。验证所述第一子组包含从验证中排除第二子组。在所述第一子组被验证为经擦除之后，其被抑制擦除，同时所述第二子组经进一步擦除。当所述第二子组被验证为经擦除时，所述组元件被验证为经擦除。验证所述组元件经擦除可包含从验证中排除所述第一子组或一起验证所述第一和第二子组两者。取决于哪个子组正被擦除和验证而使用不同的步长大小，以便更有效且准确地擦除所述组元件。  A group of non-volatile storage elements (eg, NAND strings) can be divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include faster erasing elements. Validating the first subset includes excluding the second subset from validation. After the first subset is verified as erased, it is inhibited from being erased while the second subset is further erased. The group elements are verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased may include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used depending on which subgroup is being erased and verified in order to more efficiently and accurately erase the group of elements. the

可将一组非易失性存储元件划分为子组进行软编程，以便更完全地对较慢的软编程元件进行软编程。整个所述组元件经软编程，直到被验证为经软编程为止(或直到第一子组元件被验证为经软编程，同时从验证中排除第二子组为止)。在所述组被验证为经软编程之后，第一子组元件被抑制进一步软编程，同时对第二子组元件实施额外的软编程。第二子组可包含较慢的软编程元件。第二子组可接着经历软编程验证，同时从验证中排除第一子组。针对第二子组的软编程和验证可持续，直到其被验证为经软编程为止。取决于哪一子组正被软编程和验证，可使用不同的步长大小以增加软编程信号的大小。在一个实施例中，在根据本文描述的技术的擦除之后执行根据本文描述的技术的软编程。  A group of non-volatile storage elements can be divided into subgroups for soft programming to more completely soft program slower soft programming elements. The entire set of elements is soft programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, the first subset of elements are inhibited from further soft programming while additional soft programming is performed on the second subset of elements. The second subset may contain slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verification for the second subset continues until it is verified as soft programmed. Depending on which subset is being soft programmed and verified, different step sizes can be used to increase the size of the soft programming signal. In one embodiment, soft programming according to the techniques described herein is performed after erasing according to the techniques described herein. the

在一个实施例中，提供一种擦除非易失性存储器的方法，其包含启用一组非易失性存储元件的擦除。启用所述组非易失性存储元件的第一和第二子组进行擦除。接着向所述组施加一个或一个以上擦除电压脉冲，同时启用所述第一和第二子组的非易失性存储元件进行擦除。施加脉冲直到所述第一子组被验证为经擦除为止。在所述第一子组被验证为经擦除之后，抑制所述第一子组进一步擦除，同时再次启用所述第二子组进行擦除。接着向所述组施加一个或一个以上额外擦除电压脉冲，同时抑制所述第一子组且启用所述第二子组。施加额外脉冲直到所述第二子组被验证为经擦除为止。  In one embodiment, a method of erasing non-volatile memory is provided that includes enabling erasure of a set of non-volatile storage elements. First and second subsets of the set of non-volatile storage elements are enabled for erasure. One or more erase voltage pulses are then applied to the group, simultaneously enabling the first and second subsets of non-volatile storage elements to be erased. A pulse is applied until the first subset is verified as erased. After the first subset is verified as erased, the first subset is inhibited from further erasure while the second subset is re-enabled for erasure. One or more additional erase voltage pulses are then applied to the groups while inhibiting the first subset and enabling the second subset. Additional pulses are applied until the second subset is verified as erased. the

在一个实施例中，提供一种非易失性存储器系统，其包含一组非易失性存储元件以及与所述组非易失性存储元件通信的管理电路。所述组包含第一子组和第二子组的非易失性存储元件。所述管理电路使用一种技术来擦除所述组，所述技术包含：向所述组施加擦除电压，同时启用所述组中的每一非易失性存储元件进行擦除；验证所述第一子组是否经擦除，同时从验证中排除第二子组；以及重复施加和验证，直到第一子组被验证为经擦除为止。在验证所述第一子组为经擦除之后，管理电路抑制所述第一子组的擦除，且启用所述第二子组的擦除。管理电路接着向所述组施加擦除电压，同时启用所述第二子组进行擦除且抑制所述第一子组进行擦除，并通过验证第二子组是否经擦除来验证所述组非易失性存储元件是否经擦除。  In one embodiment, a non-volatile memory system is provided that includes a set of non-volatile storage elements and a management circuit in communication with the set of non-volatile storage elements. The set includes a first subset and a second subset of non-volatile storage elements. The management circuit erases the bank using a technique comprising: applying an erase voltage to the bank while enabling each non-volatile storage element in the bank for erasing; verifying that all determining whether the first subset is erased while excluding the second subset from verification; and repeating applying and verifying until the first subset is verified as erased. After verifying that the first subset is erased, management circuitry inhibits erasure of the first subset and enables erasure of the second subset. The management circuit then applies an erase voltage to the bank while enabling the second subset for erasing and inhibiting the first subset for erasing, and verifies that the second subset is erased by verifying that the second subset is erased. Whether the set of non-volatile storage elements is erased. the

在一个实施例中，提供一种软编程非易失性存储器的方法，其包括向一组非易失性存储元件施加一个或一个以上软编程脉冲，直到所述组被验证为经软编程为止。在验证所述组为经软编程之后，抑制所述组非易失性存储元件的第一子组进行软编程，且向所述组非易失性存储元件的第二子组施加一个或一个以上额外软编程脉冲，同时抑制所述第一子组的软编程。在一个实施例中，在如上所述的擦除之后执行软编程。  In one embodiment, a method of soft programming a nonvolatile memory is provided that includes applying one or more soft programming pulses to a group of nonvolatile storage elements until the group is verified as soft programmed . After verifying that the set is soft programmed, inhibiting a first subset of the set of non-volatile storage elements from soft programming and applying one or a second subset of the set of non-volatile storage elements above additional soft programming pulses while inhibiting the soft programming of the first subset. In one embodiment, soft programming is performed after erasing as described above. the

根据另一实施例，提供一种非易失性存储器系统，其包含一组非易失性存储元件以 及与所述组非易失性存储元件通信的管理电路。所述组包含第一子组的非易失性存储元件和第二子组的非易失性存储元件。管理电路通过向所述组中的每一非易失性存储元件施加软编程电压并验证所述组是否经软编程来对所述组非易失性存储元件进行软编程。管理电路重复施加和验证，直到所述组非易失性存储元件被验证为经软编程为止。在验证所述组经软编程之后，管理电路向第一子组的非易失性存储元件中的每一非易失性存储元件施加软编程电压，并验证第一子组的非易失性存储元件是否经软编程，同时从验证中排除第二子组。  According to another embodiment, a non-volatile memory system is provided that includes a set of non-volatile storage elements and a management circuit in communication with the set of non-volatile storage elements. The set includes a first subset of non-volatile storage elements and a second subset of non-volatile storage elements. A management circuit soft programs the set of non-volatile storage elements by applying a soft programming voltage to each non-volatile storage element in the set and verifying whether the set is soft programmed. The management circuit repeats applying and verifying until the set of non-volatile storage elements is verified as soft programmed. After verifying that the group is soft programmed, the management circuit applies a soft programming voltage to each of the nonvolatile storage elements of the first subset and verifies the nonvolatile memory elements of the first subset Whether the storage elements are soft programmed while excluding the second subset from verification. the

从对说明书、附图和权利要求书的审阅可获得本发明的其它特征、方面和目的。  Other features, aspects and objects of the invention can be obtained from a review of the specification, drawings and claims. the

附图说明 Description of drawings

图1是NAND串的顶视图。  Figure 1 is a top view of a NAND string. the

图2是图1描绘的NAND串的等效电路图。  FIG. 2 is an equivalent circuit diagram of the NAND string depicted in FIG. 1 . the

图3是描绘三个NAND串的电路图。  Figure 3 is a circuit diagram depicting three NAND strings. the

图4是可实施本发明的各个方面的非易失性存储器系统的一个实施例的方框图。  Figure 4 is a block diagram of one embodiment of a non-volatile memory system in which various aspects of the present invention may be implemented. the

图5说明存储器阵列的示范性组织。  Figure 5 illustrates an exemplary organization of a memory array. the

图6描绘根据实施例的可施加到经选择字线的示范性编程/验证电压信号。  6 depicts exemplary program/verify voltage signals that may be applied to selected word lines according to an embodiment. the

图7是用于执行编程操作的示范性流程图。  FIG. 7 is an exemplary flowchart for performing a programming operation. the

图8描绘存储器单元群组的示范性阈值分布。  8 depicts exemplary threshold distributions for groups of memory cells. the

图9描绘存储两位数据的存储器单元群组的示范性阈值分布。  9 depicts an exemplary threshold distribution for a group of memory cells storing two bits of data. the

图10是描绘根据现有技术的用于执行擦除操作的示范性偏置条件的表。  10 is a table depicting exemplary bias conditions for performing an erase operation according to the prior art. the

图11是描绘在理想擦除操作期间NAND串的各个部分的电压的曲线图。  11 is a graph depicting the voltages of various portions of a NAND string during an ideal erase operation. the

图12是NAND串的横截面图，其描绘所述NAND串内的各个电容性耦合电压。  12 is a cross-sectional view of a NAND string depicting various capacitively coupled voltages within the NAND string. the

图13是描绘在擦除操作期间NAND串的末端存储器单元的各个电压的曲线图。  13 is a graph depicting various voltages of end memory cells of a NAND string during an erase operation. the

图14A和图14B描绘在完成擦除操作之后NAND串的末端和内部存储器单元的示范性个别阈值电压分布。  14A and 14B depict exemplary individual threshold voltage distributions of the end and interior memory cells of a NAND string after completion of an erase operation. the

图15是根据一个实施例的用于擦除一组非易失性存储元件的流程图。  Figure 15 is a flow diagram for erasing a group of non-volatile storage elements, according to one embodiment. the

图16是描绘根据一个实施例的用于擦除和验证一组非易失性存储元件的擦除的偏置条件的表。  Figure 16 is a table depicting bias conditions for erasing and verifying erasure of a set of non-volatile storage elements according to one embodiment. the

图17A-17C描绘根据一个实施例的在擦除操作期间NAND串的末端存储器单元和内部存储器单元在各个点处的阈值电压分布。  17A-17C depict threshold voltage distributions at various points for end and interior memory cells of a NAND string during an erase operation, according to one embodiment. the

图18A-18B是描绘根据一个实施例的擦除电压信号的曲线图。  18A-18B are graphs depicting erase voltage signals according to one embodiment. the

图19是根据一个实施例的用于执行图15的步骤456的流程图。  Figure 19 is a flowchart for performing step 456 of Figure 15, according to one embodiment. the

图20描绘根据现有技术的在软编程之后NAND串的末端存储器单元和内部存储器单元的示范性阈值电压分布。  20 depicts exemplary threshold voltage distributions of end memory cells and interior memory cells of a NAND string after soft programming according to the prior art. the

图21是根据一个实施例的用于软编程一组非易失性存储元件的流程图。  Figure 21 is a flow diagram for soft programming a group of non-volatile storage elements, according to one embodiment. the

图22是描绘根据一个实施例的用于软编程和验证一组非易失性存储元件的软编程的偏置条件的表。  Figure 22 is a table depicting bias conditions for soft programming and verifying soft programming of a set of non-volatile storage elements according to one embodiment. the

图23描绘根据一个实施例的在软编程之后NAND串的末端存储器单元和内部存储器单元的示范性阈值电压分布。  Figure 23 depicts exemplary threshold voltage distributions of end and interior memory cells of a NAND string after soft programming, according to one embodiment. the

具体实施方式 Detailed ways

图4是可用于实施本发明内容的一个或一个以上实施例的快闪存储器的一个实施例的方框图。可使用其它系统和实施方案。存储器单元阵列302由列控制电路304、行控制电路306、c源极控制电路310和p阱控制电路308控制。列控制电路304连接到存储器单元阵列302的位线，以用于读取存储在存储器单元中的数据，用于确定编程操作期间存储器单元的状态，且用于控制位线的电位电平以促进或抑制编程和擦除。行控制电路306连接到字线以选择字线中的一者、施加读取电压、施加与由列控制电路304控制的位线电位电平组合的编程电压、以及施加擦除电压。C源极控制电路310控制连接到存储器单元的共用源极线(图6中标为“C源极”)。P阱控制电路308控制p阱电压。  Figure 4 is a block diagram of one embodiment of flash memory that may be used to implement one or more embodiments of this disclosure. Other systems and implementations may be used. Memory cell array 302 is controlled by column control circuitry 304 , row control circuitry 306 , c-source control circuitry 310 and p-well control circuitry 308 . A column control circuit 304 is connected to the bit lines of the memory cell array 302 for reading data stored in the memory cells, for determining the state of the memory cells during a program operation, and for controlling the potential levels of the bit lines to facilitate or inhibit programming and erasing. Row control circuit 306 is connected to the word lines to select one of the word lines, apply a read voltage, apply a program voltage combined with the bit line potential level controlled by column control circuit 304, and apply an erase voltage. C-source control circuit 310 controls the common source line (labeled "C-source" in FIG. 6) connected to the memory cells. P-well control circuit 308 controls the p-well voltage. the

存储在存储器单元中的数据可由列控制电路304读出并经由数据输入/输出缓冲器312输出到外部I/O线。将存储在存储器单元中的编程数据经由外部I/O线输入到数据输入/输出缓冲器312，且传递到列控制电路304。外部I/O线连接到控制器318。  Data stored in the memory cells can be read out by the column control circuit 304 and output to external I/O lines via the data input/output buffer 312 . The program data stored in the memory cells is input to the data input/output buffer 312 via external I/O lines and passed to the column control circuit 304 . External I/O lines are connected to the controller 318 . the

用于控制快闪存储器装置的命令数据输入到控制器318。命令数据通知快闪存储器请求何种操作。输入命令传递到作为控制电路315的一部分的状态机316。状态机316控制列控制电路304、行控制电路306、c源极控制310、p阱控制电路308和数据输入/输出缓冲器312。状态机316也可输出快闪存储器的状态数据，例如就绪/忙或通过/失败。  Command data for controlling the flash memory device is input to the controller 318 . The command data informs the flash memory of what operation is requested. The input commands are passed to a state machine 316 which is part of the control circuit 315 . State machine 316 controls column control circuit 304 , row control circuit 306 , c-source control 310 , p-well control circuit 308 and data input/output buffer 312 . The state machine 316 can also output flash memory status data, such as ready/busy or pass/fail. the

控制器318连接到或可与例如个人计算机、数码相机或个人数字助理等的主机系统连接。其与起始例如将数据存储到存储器阵列302或从存储器阵列302读取数据的命令的主机通信，并提供或接收所述数据。控制器318将所述命令转换为可由作为控制电路315的一部分的命令电路314解译和执行的命令信号。命令电路314与状态机316通信。控制器318通常含有缓冲存储器，用于用户数据写入存储器阵列或从存储器阵列中读取。  Controller 318 is connected or connectable to a host system such as a personal computer, digital camera, or personal digital assistant. It communicates with a host that initiates commands, such as to store data to or read data from memory array 302, and provides or receives the data. Controller 318 converts the commands into command signals that can be interpreted and executed by command circuitry 314 that is part of control circuitry 315 . Command circuitry 314 communicates with state machine 316 . Controller 318 typically contains buffer memory for user data to be written to or read from the memory array. the

一个示范性存储器系统包括包含控制器318的一个集成电路，和一个或一个以上集 成电路芯片，其每一者均含有存储器阵列和相关联的控制、输入/输出和状态机电路。存在着将系统的存储器阵列和控制器电路一起集成在一个或一个以上集成电路芯片上的趋势。存储器系统可嵌入作为主机系统的一部分，或可包含在可移除地插入主机系统中的存储卡(或其它封装)中。所述卡可包含整个存储器系统(例如，包含控制器)或仅包含具有相关联外围电路的存储器阵列(其中控制器或控制功能嵌入在主机中)。因此，控制器可嵌入在主机中或包含在可移除存储器系统内。  An exemplary memory system includes one integrated circuit including controller 318, and one or more integrated circuit chips, each of which contains a memory array and associated control, input/output, and state machine circuits. There is a trend to integrate a system's memory array and controller circuitry together on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be contained in a memory card (or other package) that is removably inserted into the host system. The card may include the entire memory system (eg, including the controller) or just the memory array with associated peripheral circuitry (with the controller or control functions embedded in the host). Accordingly, the controller may be embedded in the host or contained within a removable memory system. the

参看图5，描述存储器单元阵列302的示范性结构。作为一个实例，描述被分割为1024个区块的NAND快闪EEPROM。可同时擦除存储在每一区块中的数据。在一个实施例中，区块是同时擦除的单元的最小单位。在每一区块中，在此实例中，存在8512个列。每一区块通常划分为可为编程的单位的许多页。用于编程的其它数据单位也是可能和预期的。在一个实施例中，个别页可划分为多个段且所述段可含有作为基本编程操作的一次写入的最少数目的单元。一个或一个以上数据页通常存储在一行存储器单元中。  Referring to FIG. 5, an exemplary structure of memory cell array 302 is described. As an example, a NAND flash EEPROM divided into 1024 blocks is described. Data stored in each block can be erased simultaneously. In one embodiment, a block is the smallest unit of cells that are erased simultaneously. In each block, in this example, there are 8512 columns. Each block is typically divided into a number of pages that can be programmed units. Other data units for programming are also possible and contemplated. In one embodiment, individual pages may be divided into segments and the segments may contain the minimum number of cells written at one time as a basic programming operation. One or more pages of data are typically stored in a row of memory cells. the

在图5的实例的每一区块中，存在8512个列，其划分为偶数列和奇数列。位线划分为偶数位线(BLe)和奇数位线(BLo)。在奇/偶位线结构中，沿着共用字线且连接到奇数位线的存储器单元在一个时间编程，而沿着共用字线且连接到偶数位线的存储器单元在另一时间编程。图5展示四个存储器单元，其串联连接以形成NAND串。尽管展示四个单元为包含在每一NAND串中，但可使用多于或少于四个(例如，16、32或其它数目)存储器单元。NAND串的一个端子经由第一选择晶体管或栅极(连接到选择栅极漏极线SGD)连接到相应的位线，且另一端子经由第二选择晶体管(连接到选择栅极源极线SGS)连接到c源极。  In each block of the example of FIG. 5, there are 8512 columns divided into even and odd columns. The bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd/even bit line configuration, memory cells along a common word line connected to odd bit lines are programmed at one time, while memory cells along a common word line connected to even bit lines are programmed at another time. Figure 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown as being included in each NAND string, more or less than four (eg, 16, 32, or other numbers) of memory cells can be used. One terminal of the NAND string is connected to the corresponding bit line via a first select transistor or gate (connected to select gate drain line SGD), and the other terminal is connected via a second select transistor (connected to select gate source line SGS ) to c source. the

在其它实施例中，位线没有划分为奇数和偶数位线。此类结构通常称为全位线结构。在全位线结构中，在读取和编程操作期间同时选择区块的全部位线。沿着共用字线且连接到任何位线的存储器单元同时编程。  In other embodiments, the bit lines are not divided into odd and even bit lines. Such structures are often referred to as all bit line structures. In an all-bit-line architecture, all bit-lines of a block are selected simultaneously during read and program operations. Memory cells along a common word line and connected to any bit line are programmed simultaneously. the

在一个实施例的读取和编程操作期间，同时选择4256个存储器单元。选择的存储器单元具有相同的字线(例如，WL2-i)和相同种类的位线(例如，偶数位线)。因此，可同时编程532个字节的数据。同时读取或编程的这532个字节的数据形成逻辑页。因此，在此实例中，一个区块可存储至少8个页。当每一存储器单元存储两位数据(例如，多级单元)时，一个区块存储16个页。其它大小的区块和页也可用于实施例。另外，不同于图4和5的结构的结构也可用于实施实施例。  During read and program operations of one embodiment, 4256 memory cells are selected simultaneously. The selected memory cells have the same word line (eg, WL2-i) and the same kind of bit line (eg, even bit line). Therefore, 532 bytes of data can be programmed simultaneously. These 532 bytes of data that are read or programmed simultaneously form a logical page. Therefore, in this example, a block can store at least 8 pages. When each memory cell stores two bits of data (eg, multi-level cells), one block stores 16 pages. Other sizes of blocks and pages may also be used in embodiments. In addition, structures other than those of FIGS. 4 and 5 may also be used to implement the embodiments. the

在读取和验证操作中，将选择的区块的选择栅极升高到一个或一个以上选择电压且 将选择的区块的未经选择的字线(例如，WL0、WL1和WL3)升高到读取通过电压(例如，4.5伏)以使晶体管作为通过栅极操作。选择的区块的选择字线(例如，WL2)连接到参考电压，其电平经指定用于每一读取和验证操作，以便确定关注的存储器单元的阈值电压是高于还是低于此电平。举例来说，在一位存储器单元的读取操作中，将选择的字线WL2接地，以便检测阈值电压是否高于0V。在一位存储器单元的验证操作中，将选择的字线WL2连接到例如0.8V，以便在编程进行中验证阈值电压是否已达到0.8V。源极和p阱在读取和验证期间处于零伏。将选择的位线(BLe)预充电到例如0.7V的电平。如果阈值电压高于读取或验证电平，那么关注的位线(BLe)的电位电平由于相关联的非传导性存储器单元而维持高电平。另一方面，如果阈值电压低于读取或验证电平，那么关注的位线(BLe)的电位电平由于传导性存储器单元而降低到低电平，例如小于0.5V。存储器单元的状态由连接到位线且读出所得的位线电压的读出放大器检测。是编程还是擦除存储器单元之间的差异取决于净负电荷是否被存储在浮动栅极中。举例来说，如果负电荷存储在浮动栅极中，那么阈值电压变得较高且晶体管可处于增强操作模式。  In read and verify operations, the select gates of the selected blocks are raised to one or more select voltages and the unselected word lines (e.g., WL0, WL1, and WL3) of the selected blocks are raised to read the pass voltage (eg, 4.5 volts) to operate the transistor as a pass gate. The selected word line (eg, WL2) of the selected block is connected to a reference voltage whose level is specified for each read and verify operation in order to determine whether the threshold voltage of the memory cell of interest is above or below this voltage. flat. For example, in a read operation of a one-bit memory cell, the selected word line WL2 is grounded to detect whether the threshold voltage is higher than 0V. In the verification operation of a one-bit memory cell, the selected word line WL2 is connected to, for example, 0.8V in order to verify whether the threshold voltage has reached 0.8V while programming is in progress. Source and p-well are at zero volts during read and verify. The selected bit line (BLe) is precharged to a level of eg 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the bit line of interest (BLe) remains high due to the associated non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) is lowered to a low level, eg, less than 0.5V, due to the conductive memory cell. The state of the memory cell is sensed by a sense amplifier connected to the bit line and sensing the resulting bit line voltage. The difference between whether a memory cell is programmed or erased depends on whether a net negative charge is stored in the floating gate. For example, if negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor may be in an enhancement mode of operation. the

当在一个实例中编程存储器单元时，漏极和p阱接收0伏，而控制栅极接收具有增加量值的一系列编程脉冲。在一个实施例中，所述系列中脉冲的量值范围在12伏到24伏。在其它实施例中，所述系列中脉冲的范围可不同，举例来说，具有高于12伏的开始电平。在存储器单元的编程期间，在编程脉冲之间的周期中实施验证操作。也就是说，在每一编程脉冲之间读取并行编程的单元群组中每一单元的编程电平，以确定其是否已达到或超过其正编程到的验证电平。一种验证编程的方式是在特定比较点测试传导性。例如在NAND单元中，通过针对所有后续的编程脉冲将位线电压从0升高到VDD(例如，2.5伏)以终止用于验证为充分编程的单元的编程过程，来锁定那些单元。在一些情况下，将限制脉冲的数目(例如，20个脉冲)，且如果给定的存储器单元没有被最后的脉冲充分编程，那么假定错误。在一些实施方案中，在编程之前擦除存储器单元(以区块或其它单位)。  When programming a memory cell in one example, the drain and p-well receive 0 volts, while the control gate receives a series of programming pulses of increasing magnitude. In one embodiment, the magnitude of the pulses in the series ranges from 12 volts to 24 volts. In other embodiments, the range of pulses in the series may be different, for example, with a starting level above 12 volts. During programming of memory cells, verify operations are performed in periods between programming pulses. That is, the programming level of each cell in the group of cells being programmed in parallel is read between each programming pulse to determine whether it has reached or exceeded the verify level to which it is being programmed. One way to verify programming is to test conductivity at specific comparison points. In NAND cells, for example, those cells are locked by raising the bit line voltage from 0 to VDD (eg, 2.5 volts) for all subsequent programming pulses to terminate the programming process for cells verified as fully programmed. In some cases, the number of pulses will be limited (eg, 20 pulses), and if a given memory cell was not sufficiently programmed by the last pulse, then an error is assumed. In some implementations, memory cells (in blocks or other units) are erased prior to programming. the

图6描绘根据一个实施例的编程电压信号。此信号具有一组带增加量值的脉冲。脉冲的量值随每一脉冲增加预定的步长大小。在包含存储多位数据的存储器单元的一个实施例中，示范性步长大小为0.2伏(或0.4伏)。在编程脉冲的每一者之间的是验证脉冲。图6的信号假定四状态存储器单元，因此其包含三个验证脉冲。举例来说，在编程脉冲330与332之间的是三个连续的验证脉冲。第一验证脉冲334描绘为处于零伏验证电压电平。第二验证脉冲336以第二验证电压电平跟随第一验证脉冲。第三验证脉冲338以 第三验证电压电平跟随第二验证脉冲336。能够在八个状态中存储数据的多状态存储器单元可能需要在七个比较点处执行验证操作。因此，依次施加七个验证脉冲以在两个连续的编程脉冲之间以七个验证电平执行七个验证操作。基于七个验证操作，系统可确定存储器单元的状态。一种用于减少验证的时间负担的方法是使用更有效的验证过程，例如在以下申请案中所揭示：2002年12月5日申请的题为“Smart Verify for Multi-StateMemories”的第10/314,055号美国专利申请案；2005年10月27日申请的题为“Methodfor Programming of Multi-State Non-Volatile Memory Using Smart Verify”的第__________号(代理人案号SAND-1051US1)美国专利申请案；以及2005年10月27日申请的题为“Apparatus for Programming of Multi-State Non-Volatile Memory Using Smart Verify”的第__________号(代理人案号SAND-105IUS0)的美国专利申请案，所述申请案全部以全文引用的方式并入本文中。  Figure 6 depicts programming voltage signals according to one embodiment. This signal has a set of pulses with increasing magnitudes. The magnitude of the pulses increases with each pulse by a predetermined step size. In one embodiment including memory cells storing multiple bits of data, an exemplary step size is 0.2 volts (or 0.4 volts). Between each of the programming pulses are verify pulses. The signal of Figure 6 assumes a four-state memory cell, so it contains three verify pulses. For example, between programming pulses 330 and 332 are three consecutive verify pulses. The first verify pulse 334 is depicted at a verify voltage level of zero volts. A second verify pulse 336 follows the first verify pulse with a second verify voltage level. A third verify pulse 338 follows the second verify pulse 336 with a third verify voltage level. A multi-state memory cell capable of storing data in eight states may require verify operations to be performed at seven compare points. Accordingly, seven verify pulses are sequentially applied to perform seven verify operations at seven verify levels between two consecutive program pulses. Based on the seven verify operations, the system can determine the state of the memory cells. One method for reducing the time burden of verification is to use a more efficient verification process, such as disclosed in the following application: 10/2002, entitled "Smart Verify for Multi-State Memories", filed December 5, 2002 U.S. Patent Application No. 314,055; U.S. Patent Application No. __________ (Attorney Docket No. SAND-1051US1), filed October 27, 2005, and entitled "Method for Programming of Multi-State Non-Volatile Memory Using Smart Verify" and U.S. Patent Application No. __________ (Attorney Docket No. SAND-105IUS0) entitled "Apparatus for Programming of Multi-State Non-Volatile Memory Using Smart Verify" filed on October 27, 2005, Said applications are hereby incorporated by reference in their entirety. the

根据现有技术中已知的技术来执行上文描述的读取和验证操作。因此，所属领域的技术人员可改变所解释细节中的许多细节。  The read and verify operations described above are performed according to techniques known in the art. Accordingly, many of the details explained may vary by one skilled in the art. the

图7是描述用于对非易失性存储器进行编程的方法的一个实施例的流程图。在步骤340擦除将编程的存储器单元。步骤340可包含擦除比将编程的存储器单元更多的存储器单元(例如，以区块或其它单位)。在步骤342，执行软编程以使经擦除存储器单元的擦除阈值电压的分布变窄。一些存储器单元可能由于擦除过程而处于比必要擦除状态更深的擦除状态。软编程可施加小编程脉冲以移动经擦除存储器单元的阈值电压使其更接近擦除验证电平。在图7的步骤350，“数据加载”命令由控制器318发出并输入到命令电路314中，允许数据输入到数据输入/输出缓冲器312。输入数据被认为是命令且经由输入到命令电路314的命令锁存信号(未说明)由状态机316锁存。在步骤352，将指定页地址的地址数据从控制器或主机输入到行控制器或解码器306。输入数据被认为是页地址且在输入到命令电路314的地址锁存信号影响下经由状态机316被锁存。在步骤354，将用于经定址页的编程数据页输入到数据输入/输出缓冲器312以用于编程。举例来说，在一个实施例中可输入532个字节的数据。所述数据锁存在用于选择的位线的适当寄存器中。在一些实施例中，数据还锁存在用于选择的位线的第二寄存器中以用于验证操作。在步骤356，“编程”命令由控制器发出并输入到数据输入/输出缓冲器312。命令经由输入到命令电路314的命令锁存信号由状态机316锁存。  Figure 7 is a flowchart describing one embodiment of a method for programming non-volatile memory. In step 340 the memory cells to be programmed are erased. Step 340 may include erasing more memory cells (eg, in blocks or other units) than will be programmed. In step 342, soft programming is performed to narrow the distribution of erased threshold voltages of the erased memory cells. Some memory cells may be in a deeper erased state than necessary due to the erase process. Soft programming can apply small programming pulses to move the threshold voltage of erased memory cells closer to the erase verify level. At step 350 of FIG. 7 , a "data load" command is issued by controller 318 and input into command circuit 314 , allowing data to be input to data input/output buffer 312 . Input data is considered a command and is latched by state machine 316 via a command latch signal (not shown) input to command circuit 314 . In step 352, address data specifying the page address is input to the row controller or decoder 306 from the controller or host. The input data is considered a page address and is latched via state machine 316 under the influence of an address latch signal input to command circuit 314 . At step 354, the page of programming data for the addressed page is input to data input/output buffer 312 for programming. For example, 532 bytes of data may be input in one embodiment. The data is latched in the appropriate register for the selected bit line. In some embodiments, data is also latched in a second register for the selected bit line for verify operations. At step 356 , a "program" command is issued by the controller and input to the data input/output buffer 312 . Commands are latched by state machine 316 via a command latch signal input to command circuit 314 . the

通过“编程”命令触发，将使用施加到适当字线的图6的步进脉冲将在步骤354中锁存的数据编程到由状态机316控制的经选择存储器单元中。在步骤358，将施加到经 选择字线的编程脉冲电压电平Vpgm初始化为开始脉冲(例如，12V)并将由状态机316维持的程序计数器PC初始化于0。在步骤360，将第一Vpgm脉冲施加于经选择字线。如果逻辑“0”存储在特定数据锁存器中，指示应编程相应的存储器单元，那么将相应的位线接地。另一方面，如果逻辑“1”存储在特定锁存器中，指示相应存储器单元应保持在其当前数据状态，那么将相应的位线连接到VDD以抑制编程。  Triggered by a "program" command, the data latched in step 354 will be programmed into the selected memory cells controlled by state machine 316 using the stepping pulses of FIG. 6 applied to the appropriate word line. In step 358, the program pulse voltage level Vpgm applied to the selected word line is initialized as a start pulse (e.g., 12V) and the program counter PC maintained by state machine 316 is initialized at zero. At step 360, a first Vpgm pulse is applied to the selected word line. If a logic "0" is stored in a particular data latch, indicating that the corresponding memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if a logic "1" is stored in a particular latch, indicating that the corresponding memory cell should remain in its current data state, then the corresponding bit line is connected to VDD to inhibit programming. the

在步骤362，验证经选择存储器单元的状态。如果检测到经选择单元的目标阈值电压已到达适当电平，那么存储在相应数据锁存器中的数据改变为逻辑“1”。如果检测到阈值电压未到达适当电平，那么存储在相应数据锁存器中的数据不改变。以此方式，无需编程具有存储在其相应数据锁存器中的逻辑“1”的位线。当所有数据锁存器存储逻辑“1”时，状态机知道所有经选择单元均已编程。在步骤364，检查是否所有的数据锁存器均在存储逻辑“1”。如果是这样，那么编程过程完成且成功，因为所有经选择存储器单元均经编程且验证到达其目标状态。在步骤366报告“通过”状态。  In step 362, the state of the selected memory cells is verified. If it is detected that the target threshold voltage of the selected cell has reached the appropriate level, then the data stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this way, there is no need to program bit lines that have logic "1" stored in their corresponding data latches. When all data latches store a logic "1," the state machine knows that all selected cells are programmed. At step 364, it is checked whether all data latches are storing logic "1". If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. At step 366 a "pass" status is reported. the

如果在步骤364确定并非所有的数据锁存器都在存储逻辑“I₅”，那么编程过程继续。在步骤368，对照编程限制值检查程序计数器PC。编程限制值的一个实例是20，然而，可在各种实施方案中使用其它值。如果程序计数器PC不小于20，那么在步骤369确定未成功编程的位的数目是否等于或小于预定数目。如果未成功编程的位的数目等于或小于预定数目，那么将编程过程标记为通过且在步骤371报告通过状态。可在读取过程期间使用误差校正来校正未成功编程的位。然而，如果未成功编程的位的数目大于预定数目，那么将编程过程标记为失败且在步骤370报告失败状态。如果程序计数器PC小于20，那么在步骤372使Vpgm电平增加步长大小且递增程序计数器PC。在步骤372，过程循环回到步骤360以施加下一Vpgm脉冲。  If at step 364 it is determined that not all of the data latches are storing logic " _I5 ", then the programming process continues. In step 368, the program counter PC is checked against the program limit value. One example of a programming limit value is 20, however, other values may be used in various implementations. If the program counter PC is not less than 20, then at step 369 it is determined whether the number of unsuccessfully programmed bits is equal to or less than a predetermined number. If the number of unsuccessfully programmed bits is equal to or less than the predetermined number, then the programming process is marked as passed and a passed status is reported at step 371 . Error correction can be used during the read process to correct unsuccessfully programmed bits. However, if the number of unsuccessfully programmed bits is greater than the predetermined number, then the programming process is marked as failed and a failure status is reported at step 370 . If the program counter PC is less than 20, then at step 372 the Vpgm level is increased by the step size and the program counter PC is incremented. At step 372, the process loops back to step 360 to apply the next Vpgm pulse.

图7的流程图描绘可针对二进制存储应用的单次通过编程方法。在可针对例如多级存储应用的二次通过编程方法中，可在流程图的单一重复中使用多个编程或验证步骤。可针对编程操作的每一次通过执行步骤358-372。在第一次通过中，可施加一个或一个以上编程脉冲并验证其结果以确定单元是否处于适当的中间状态。在第二次通过中，可施加一个或一个以上编程脉冲并验证其结果以确定单元是否处于适当的最终状态。  The flowchart of FIG. 7 depicts a single-pass programming method that may be applied for binary storage. In a two-pass programming approach, which may be used for multi-level storage applications, for example, multiple programming or verifying steps may be used in a single iteration of the flowchart. Steps 358-372 may be performed for each pass of the program operation. In the first pass, one or more programming pulses may be applied and their results verified to determine if the cell is in the proper intermediate state. In a second pass, one or more programming pulses may be applied and the results verified to determine if the cell is in the proper final state. the

在成功的编程过程结束时，存储器单元的阈值电压应在用于经编程存储器单元的阈值电压的一个或一个以上分布内或在用于经擦除存储器单元的阈值电压的分布内。图8说明当每一存储器单元存储一个位的数据时用于存储器单元阵列的阈值电压分布。图8展示用于经擦除存储器单元的阈值电压的第一分布380和用于经编程存储器单元的阈值 电压的第二分布382。在一个实施例中，第一分布380中的阈值电压电平为负且对应于逻辑“1”，而第二分布382中的阈值电压电平为正且对应于逻辑“0”。  At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells. 8 illustrates threshold voltage distributions for an array of memory cells when each memory cell stores one bit of data. Figure 8 shows a first distribution 380 of threshold voltages for erased memory cells and a second distribution 382 of threshold voltages for programmed memory cells. In one embodiment, the threshold voltage levels in the first distribution 380 are negative and correspond to a logic "1," while the threshold voltage levels in the second distribution 382 are positive and correspond to a logic "0." the

图9说明当每一存储器单元在四个物理状态中存储两位数据时用于存储器单元阵列的示范性阈值电压分布。分布384表示处于经擦除状态(存储“11”)的单元的阈值电压的分布，其具有负阈值电压电平。分布386表示处于第一编程状态(存储“10”)的单元的阈值电压的分布。分布388表示处于第二编程状态(存储“00”)的单元的阈值电压的分布。分布390表示处于第三编程状态(存储“01”)的单元的阈值电压的分布。在此实例中，存储在单个存储器单元中的两个位中的每一位来自不同的逻辑页。也就是说，存储在每一存储器单元中的两个位的每一位承载不同的逻辑页地址。正方形中显示的位对应于下部页。圆形中显示的位对应于上部页。在一个实施例中，使用格雷码序列将逻辑状态指定到存储器单元的连续物理状态，使得如果浮动栅极的阈值电压错误地移位到最近的相邻阈值电压状态范围内，那么仅一个位将受影响。为了提供改进的可靠性，优选使个别分布变紧密(分布变窄)，因为较紧密的分布会使读取余量(相邻状态阈值分布之间的距离)变宽。  9 illustrates exemplary threshold voltage distributions for an array of memory cells when each memory cell stores two bits of data in four physical states. Distribution 384 represents the distribution of threshold voltages of cells in the erased state (stored "11"), which have negative threshold voltage levels. Distribution 386 represents the distribution of threshold voltages for cells in the first programmed state (stored "10"). Distribution 388 represents the distribution of threshold voltages for cells in the second programmed state (stored "00"). Distribution 390 represents the distribution of threshold voltages for cells in the third programmed state (stored "01"). In this example, each of the two bits stored in a single memory cell is from a different logical page. That is, each of the two bits stored in each memory cell carries a different logical page address. The bits shown in the squares correspond to the lower pages. The bits shown in the circles correspond to the upper pages. In one embodiment, a Gray code sequence is used to assign logical states to successive physical states of a memory cell such that if the threshold voltage of the floating gate is incorrectly shifted to within the nearest adjacent threshold voltage state range, only one bit will Affected. To provide improved reliability, it is preferable to tighten the individual distributions (narrow the distribution), since a tighter distribution widens the read margin (distance between adjacent state threshold distributions). the

当然，如果存储器以四个以上物理状态操作，那么在存储器单元的所界定电压阈值窗内将存在等于状态数目的阈值电压分布数目。此外，尽管已向每一分布或物理状态指定特定的位图案，但可指定不同的位图案。  Of course, if the memory operates in more than four physical states, there will be a number of threshold voltage distributions equal to the number of states within the defined voltage threshold window of the memory cell. Furthermore, although specific bit patterns have been assigned to each distribution or physical state, different bit patterns may be assigned. the

通常，正并行编程的单元是沿着字线的交替单元。举例来说，图3说明沿着一个字线WL2的大得多数目的单元中的三个存储器单元224、244和252。包含单元224和252的一组交替单元存储来自逻辑页0和1(“偶数页”)的位，而包含单元244的另一组交替单元存储来自逻辑页2和3(“奇数页”)的位。  Typically, the cells being programmed in parallel are alternate cells along the word line. For example, FIG. 3 illustrates three memory cells 224, 244, and 252 in a much larger number of cells along one word line WL2. An alternating set of cells containing cells 224 and 252 stores bits from logical pages 0 and 1 ("even pages"), while another set of alternating cells containing cell 244 stores bits from logical pages 2 and 3 ("odd pages"). bit. the

在一个实施例中，通过将p阱升高到擦除电压(例如，20伏)并将经选择区块的字线接地或对其施加0伏，同时源极和位线浮动，来擦除存储器单元。图10描绘用于执行擦除操作的示范性偏置条件。由于电容性耦合，未经选择的字线(例如，未经选择的、将不擦除的区块中的那些字线)、位线、选择线和c源极也升高到高的正电位(例如，20V)。因此将强电场施加到经选择区块的存储器单元的隧道氧化物层，且当浮动栅极的电子发射到衬底时，擦除经选择存储器单元的数据。擦除指通过将电子转移出其浮动栅极来降低存储器单元的阈值电压。在充足的电子从浮动栅极转移到p阱区时，经选择单元的阈值电压变为负。一旦阈值电压到达预定的充分低的值，就可将存储器单元视为经擦除且认为擦除过程完成或成功。因此，擦除存储器单元指降低存储器单元的阈值电压， 且不暗示其完全或成功擦除。可在整个存储器阵列、阵列的一个或一个以上区块或单元的另一单位上执行擦除。擦除电压信号V_erase通常作为一系列擦除电压脉冲而施加，其中在每一脉冲之间实施擦除验证操作。如果在擦除电压脉冲施加之后正擦除的单元的单位未被验证为经擦除，那么可将另一擦除电压脉冲施加到p阱区。在一些实施例中，擦除电压的峰值针对每一后续脉冲而增加(例如，从16V到20V以1V递增)。  In one embodiment, erasing is performed by raising the p-well to an erase voltage (e.g., 20 volts) and grounding or applying 0 volts to the word line of the selected block while the source and bit lines are floating. memory unit. Figure 10 depicts exemplary bias conditions for performing an erase operation. Due to capacitive coupling, unselected word lines (such as those in unselected blocks that will not be erased), bit lines, select lines, and c-source are also raised to a high positive potential (for example, 20V). A strong electric field is thus applied to the tunnel oxide layer of the memory cells of the selected block, and when electrons of the floating gates are emitted to the substrate, the data of the selected memory cells are erased. Erasing refers to lowering the threshold voltage of a memory cell by transferring electrons out of its floating gate. When sufficient electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected cell becomes negative. Once the threshold voltage reaches a predetermined sufficiently low value, the memory cell can be considered erased and the erasing process is considered complete or successful. Thus, erasing a memory cell refers to lowering the threshold voltage of the memory cell and does not imply its complete or successful erasure. Erasing can be performed on the entire memory array, one or more blocks of the array, or another unit of cells. The erase voltage signal _Verase is typically applied as a series of erase voltage pulses, with an erase verify operation performed between each pulse. If the unit of cell being erased is not verified as erased after application of the erase voltage pulse, another erase voltage pulse may be applied to the p-well region. In some embodiments, the peak value of the erase voltage increases for each subsequent pulse (eg, from 16V to 20V in 1V increments).

图11是描绘在用于典型擦除操作的单一擦除电压脉冲施加期间NAND串各部分处电压的曲线图(例如，在图10的偏置条件下)。图11的实例说明理想情况，其忽略了如下文论述的栅极间电容性电荷耦合。曲线410描绘接收擦除电压信号V_erase的p阱区的电压。擦除电压脉冲导致p阱直线上升到20V并接着返回到0V。曲线414和412描绘所述串的存储器单元的控制栅极电压和浮动栅极电压。在施加擦除电压脉冲之前，浮动栅极电压取决于存储器单元的编程状态，且通常低于0V。在图11中，针对第一擦除电压脉冲之前的浮动栅极电压假定-1V的值。控制栅极电压414在整个擦除操作中保持于0V，而浮动栅极电压412与p阱电压成比例地上升。浮动栅极在隧道电介质区上电容性耦合到p阱。在许多NAND串实施方案中，存储器单元的浮动栅极与p阱区之间的电容性耦合比约为40-50％。因此，浮动栅极电压412以与p阱电压的约0.5∶1的比率(当耦合比为50％时)上升到约9V的电压。所得的擦除电位(单元的浮动栅极与p阱区之间的电位)在以下图11的曲线图中给出。擦除电位等于p阱电压(V_erase＝20V)与浮动栅极电压(VF_G＝9V)之间的差。对于图11中描绘的情境，擦除电压在第一擦除电压脉冲开始时等于约11V。应注意，擦除电位在实际的擦除电压脉冲期间随电子从浮动栅极转移到p阱而改变。由此，当p阱在擦除电压脉冲之后返回到0V时，浮动栅极电压将与施加擦除电压脉冲之前不同。通常，浮动栅极电压在第一擦除电压脉冲之后将为正，对应于存储器单元的负(经擦除)阈值电压。  11 is a graph depicting voltages at various portions of a NAND string during application of a single erase voltage pulse for a typical erase operation (eg, under the bias conditions of FIG. 10). The example of FIG. 11 illustrates the ideal case, which ignores inter-gate capacitive charge coupling as discussed below. Curve 410 depicts the voltage of the p-well region receiving the _erase voltage signal Verase. The erase voltage pulse causes the p-well to ramp up to 20V and then return to 0V. Curves 414 and 412 depict the control and floating gate voltages of the memory cells of the string. Prior to application of the erase voltage pulse, the floating gate voltage depends on the programmed state of the memory cell and is typically below 0V. In FIG. 11 , a value of -1V is assumed for the floating gate voltage before the first erase voltage pulse. The control gate voltage 414 remains at 0V throughout the erase operation, while the floating gate voltage 412 rises in proportion to the p-well voltage. The floating gate is capacitively coupled to the p-well over the tunnel dielectric region. In many NAND string implementations, the capacitive coupling ratio between the floating gate of the memory cell and the p-well region is about 40-50%. Thus, the floating gate voltage 412 rises to a voltage of about 9V at a ratio of about 0.5:1 to the p-well voltage (when the coupling ratio is 50%). The resulting erase potential (the potential between the cell's floating gate and the p-well region) is given in the graph of Figure 11 below. The erase potential is equal to the difference between the p-well voltage (V _erase =20V) and the floating gate voltage (VF _G =9V). For the scenario depicted in Figure 11, the erase voltage is equal to about 11V at the beginning of the first erase voltage pulse. It should be noted that the erase potential changes during the actual erase voltage pulse as electrons are transferred from the floating gate to the p-well. Thus, when the p-well returns to 0V after the erase voltage pulse, the floating gate voltage will be different than before the erase voltage pulse was applied. Typically, the floating gate voltage will be positive after the first erase voltage pulse, corresponding to the negative (erased) threshold voltage of the memory cell.

NAND串中的实际电压电平将不同于相对于图11的理想情况描述的电压电平。由于相邻浮动栅极之间以及选择栅极与相邻浮动栅极之间的电容性电荷耦合，NAND串的不同存储器单元在相同擦除偏置条件下可能经历不同的擦除电位。  The actual voltage levels in the NAND string will be different than those described with respect to the ideal case of FIG. 11 . Due to capacitive charge coupling between adjacent floating gates and between select gates and adjacent floating gates, different memory cells of a NAND string may experience different erase potentials under the same erase bias conditions. the

图12提供包含8个存储器单元的NAND串的横截面图。尽管相对于图12和8单元NAND结构呈现实施例，但本发明不限于此，且可根据包含更少或8个以上存储器单元(例如，4、12、16或更多)的许多NAND结构来使用。如图12中描绘，NAND串的存储器单元形成在p阱区540中。每一存储器单元(502、504、506、508、510、512、514和516)包含由控制栅极(502c、504c、506c、508c、510c、512c、514c和516c)和浮 动栅极(502f、504f、506f、510f、512f、514f和516f)组成的堆叠栅极结构。浮动栅极形成于氧化物或其它电介质复合膜顶部上的p阱的表面上。控制栅极在浮动栅极上，其中氧化物或其它隔离电介质层分离控制栅极和浮动栅极。存储器单元的控制栅极连接到或形成字线WL0、WL1、WL2、WL3、WL4、WL5、WL6和WL7。N+扩散区542在相邻单元之间共用，藉此所述单元彼此串联连接以形成NAND串。这些N+扩散区形成单元中每一者的源极和漏极。N+扩散区526连接到用于NAND串的位线，而N+扩散区528连接到用于多个NAND串的共用源极线。选择栅极520和522由与存储器单元相同的结构形成，然而，栅极区电连接。  Figure 12 provides a cross-sectional view of a NAND string containing 8 memory cells. Although embodiments are presented with respect to Figures 12 and 8-cell NAND structures, the invention is not so limited and may be implemented in accordance with many NAND structures containing fewer or more than 8 memory cells (e.g., 4, 12, 16, or more). use. As depicted in FIG. 12 , the memory cells of the NAND string are formed in p-well region 540 . Each memory cell (502, 504, 506, 508, 510, 512, 514, and 516) comprises a control gate (502c, 504c, 506c, 508c, 510c, 512c, 514c, and 516c) and a floating gate (502f , 504f, 506f, 510f, 512f, 514f and 516f) a stacked gate structure. The floating gate is formed on the surface of the p-well on top of an oxide or other dielectric composite film. The control gate is on the floating gate, with an oxide or other isolating dielectric layer separating the control gate and the floating gate. The control gates of the memory cells are connected to or form word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7. N+ diffusion region 542 is shared between adjacent cells whereby the cells are connected in series with each other to form a NAND string. These N+ diffused regions form the source and drain of each of the cells. N+ diffusion region 526 is connected to the bit line for the NAND string, while N+ diffusion region 528 is connected to the common source line for multiple NAND strings. Select gates 520 and 522 are formed from the same structure as the memory cells, however, the gate regions are electrically connected. the

由于电容性耦合，当擦除操作期间将高擦除电压施加于p阱时，浮动选择栅极522和520升高到较高正电位。施加到p阱或其某个部分的擦除电压从阱区耦合到选择栅极中的每一者。在许多NAND结构中约90-100％的p阱电压可预期耦合到每一选择栅极。因此，如果20V的擦除电压脉冲施加于p阱，那么每一选择栅极上的电压将上升约18V-20V而到达18V-20V的电压。在图12中，从p阱540到选择栅极522和520的耦合由箭头530说明。尽管程度较小，但所述串的存储器单元中的每一者也经历类似的耦合效应。存储器单元的p阱与浮动栅极之间的耦合通常约为40-50％。每一浮动栅极还耦合到其相应的控制栅极，其中耦合约为50-60％。在较小程度上，每一浮动栅极耦合到相邻的浮动栅极和控制栅极。所有不同的耦合加在一起达到总共100％。假定从p阱到浮动栅极的50％耦合，每一存储器单元的浮动栅极电压在施加20V擦除电压脉冲下升高约10V。此耦合效应由箭头532说明。耦合到每一存储器单元的浮动栅极的电压实现在隧道氧化层上产生的V_erase电位。举例来说，针对在擦除之前具有-1V的浮动栅极电压的存储器单元，在对p阱施加20V擦除电压脉冲下产生约11V(20V-9V)的擦除电位。  Due to capacitive coupling, floating select gates 522 and 520 rise to a higher positive potential when a high erase voltage is applied to the p-well during an erase operation. An erase voltage applied to the p-well, or some portion thereof, is coupled from the well region to each of the select gates. In many NAND structures about 90-100% of the p-well voltage can be expected to be coupled to each select gate. Therefore, if an erase voltage pulse of 20V is applied to the p-well, the voltage on each select gate will rise by approximately 18V-20V to a voltage of 18V-20V. In FIG. 12 , the coupling from p-well 540 to select gates 522 and 520 is illustrated by arrow 530 . Each of the memory cells of the string also experience similar coupling effects, albeit to a lesser extent. The coupling between the p-well and the floating gate of a memory cell is typically about 40-50%. Each floating gate is also coupled to its corresponding control gate, where the coupling is about 50-60%. To a lesser extent, each floating gate is coupled to adjacent floating and control gates. All the different couplings add up to a total of 100%. Assuming 50% coupling from the p-well to the floating gate, the floating gate voltage of each memory cell rises by approximately 10V upon application of a 20V erase voltage pulse. This coupling effect is illustrated by arrow 532 . The voltage coupled to the floating gate of each memory cell implements the _Verase potential developed across the tunnel oxide. For example, applying a 20V erase voltage pulse to the p-well produces an erase potential of about 11V (20V-9V) for a memory cell with a floating gate voltage of -1V prior to erasing.

所述串的每一存储器单元将经历来自相邻存储器单元和/或晶体管的一些电容性电荷耦合。此耦合可影响单元的浮动栅极的电位，且因此影响单元的擦除电位。NAND串的最后的存储器单元(例如，图12中的存储器单元502和516)——连接到NAND串的第一和最后字线(末端字线)且邻近于NAND串的选择栅极的那些存储器单元——将经历来自相邻选择栅极的电容性电荷耦合。在图12中，此电容性耦合由从存储器单元520的选择栅极520到浮动栅极502f的箭头534以及从存储器单元516的选择栅极522到浮动栅极516f的箭头538描绘。耦合到存储器单元502和516的电压将与代表性选择栅极处的电压量成比例地减少那些单元的隧道电介质区(例如，隧道氧化物)上存在的电场。  Each memory cell of the string will experience some capacitive charge coupling from neighboring memory cells and/or transistors. This coupling can affect the potential of the cell's floating gate, and thus the cell's erase potential. Last memory cells of a NAND string (e.g., memory cells 502 and 516 in FIG. 12 )—those memories connected to the first and last word lines (end word lines) of the NAND string and adjacent to the select gates of the NAND string Cell - will experience capacitive charge coupling from adjacent select gates. In FIG. 12, this capacitive coupling is depicted by arrow 534 from select gate 520 of memory cell 520 to floating gate 502f and arrow 538 from select gate 522 of memory cell 516 to floating gate 516f. The voltage coupled to memory cells 502 and 516 will reduce the electric field present on the tunnel dielectric region (eg, tunnel oxide) of those cells in proportion to the amount of voltage at the representative select gate. the

由箭头538和534表示的耦合在两个方向上发生，因为在擦除操作期间，选择栅极 同样处于浮动状态。由此，存储器单元516和502的浮动栅极电压将对选择栅极522和520上的电压有一些影响。然而，从浮动栅极到选择栅极的耦合比从p阱到选择栅极的耦合小得多，且因此几乎完全由p阱电压确定选择栅极电压。  Coupling, represented by arrows 538 and 534, occurs in both directions because the select gates are also in a floating state during the erase operation. Thus, the floating gate voltage of memory cells 516 and 502 will have some effect on the voltage on select gates 522 and 520 . However, the coupling from the floating gate to the select gate is much smaller than from the p-well to the select gate, and thus the select gate voltage is almost entirely determined by the p-well voltage. the

在许多NAND实施方案中，从NAND串的末端存储器单元的选择栅极到浮动栅极的电容性耦合可预期为约2％到5％的数量级。如果将20伏的擦除电压施加到p阱区，那么在90％p阱到选择栅极的耦合的情况下，每一选择栅极的电压将上升约18V。随后由于从选择栅极到相邻浮动栅极的2-5％的耦合，相邻浮动栅极(例如，516f和502f)上的电压将上升约0.4-1V。所述串的末端存储器单元的隧道氧化物上的所得电压将比图11所示的理想情况的电压小约0.4到1V。应注意，上文提到的电容性耦合可取决于存储器单元和选择栅极的物理尺寸、存储器单元与选择栅极之间的间距、以及在构造此类组件中使用的例如隧道电介质、控制与浮动栅极之间的电介质以及选择栅极与存储器单元之间的电介质的材料的电介质性质而较大程度地改变。例如在一些情况下，上文提到的耦合可大于或小于上文提到的2-5％范围。  In many NAND implementations, the capacitive coupling from the select gates to the floating gates of the end memory cells of a NAND string can be expected to be on the order of about 2% to 5%. If an erase voltage of 20 volts is applied to the p-well region, then with 90% p-well to select gate coupling, the voltage of each select gate will rise by approximately 18V. The voltage on the adjacent floating gates (eg, 516f and 502f) will then rise by about 0.4-1V due to the 2-5% coupling from the select gate to the adjacent floating gate. The resulting voltage on the tunnel oxide of the end memory cell of the string will be about 0.4 to IV less than the ideal case shown in FIG. 11 . It should be noted that the capacitive coupling mentioned above may depend on the physical dimensions of the memory cells and select gates, the spacing between the memory cells and the select gates, and factors such as tunnel dielectrics, control and gates used in constructing such components. The dielectric properties of the material of the dielectric between the floating gates and the dielectric between the select gate and the memory cell vary considerably. For example, in some cases, the coupling mentioned above may be greater or less than the 2-5% range mentioned above. the

除了相邻浮动栅极之间的耦合之外，另一因素是浮动栅极与相邻字线或控制栅极之间的耦合。此耦合也可为2-5％的数量级，但可取决于存储器单元的尺寸和形状而更小或更大。在一些情况下，尤其是选择栅极与相邻存储器单元之间的物理距离类似于两个内部存储器单元之间的距离时，从选择栅极到相邻浮动栅极的耦合将处在与来自相邻控制栅极(字线)和浮动栅极的耦合类似的范围内。然而在擦除操作期间，由于选择栅极与控制栅极和浮动栅极相比被不同地偏置，因此末端存储器单元的浮动栅极电压将高于内部存储器单元的浮动栅极电压，且因此用于末端存储器单元的擦除电位将较低，如下文描述。  In addition to the coupling between adjacent floating gates, another factor is the coupling between the floating gates and adjacent word lines or control gates. This coupling can also be on the order of 2-5%, but can be smaller or larger depending on the size and shape of the memory cell. In some cases, especially when the physical distance between the select gate and the adjacent memory cell is similar to the distance between two internal memory cells, the coupling from the select gate to the adjacent floating gate will be at the same level as that from Adjacent control gates (word lines) and floating gates are coupled within similar ranges. However, during an erase operation, since the select gate is biased differently compared to the control and floating gates, the floating gate voltage of the end memory cells will be higher than the floating gate voltage of the inner memory cells, and thus The erase potential for the end memory cells will be lower, as described below. the

图13描绘在图10的偏置条件下在用于擦除操作的单个擦除电压脉冲施加期间，NAND串的典型末端存储器单元的p阱电压420、浮动栅极电压422和控制栅极电压424。P阱电压420从0V上升到20V的峰值并接着返回到0V。控制栅极电压424保持在0V，因为连接到每一存储器单元的字线被供以0V。如同所有的单元，末端存储器单元的浮动栅极在约40-50％的数量级上电容性耦合到p阱区。在p阱区电压增加到20V时，此电容性耦合促使浮动栅极电压在假定50％耦合时上升约10V。末端存储器单元另外具有处于与其耦合的相邻选择栅极处的一部分电压。因此，这些浮动栅极上的电压将不仅与和其电容性耦合的p阱电压成比例地增加，而且还由于来自选择栅极的2-5％耦合而增加。在图13中，假定来自选择栅极的耦合向浮动栅极电压增加额外的1V。因此，与图11 中描绘的理想情况的9V的最大值成对比，浮动栅极电压422在擦除电压脉冲的开始时上升到10V的最大值。末端存储器单元的隧道电介质区上的擦除电位在以下图13的曲线图中给出。擦除电压脉冲开始时的擦除电位为约10V，或比理想情况的11V擦除电位小约1V。  13 depicts the p-well voltage 420, floating gate voltage 422, and control gate voltage 424 of a typical end memory cell of a NAND string during application of a single erase voltage pulse for an erase operation under the bias conditions of FIG. . The P-well voltage 420 rises from 0V to a peak of 20V and then returns to 0V. The control gate voltage 424 remains at 0V because the word line connected to each memory cell is supplied with 0V. As with all cells, the floating gates of the end memory cells are capacitively coupled to the p-well region on the order of about 40-50%. As the p-well voltage increases to 20V, this capacitive coupling causes the floating gate voltage to rise by about 10V assuming 50% coupling. The end memory cells additionally have a portion of the voltage at the adjacent select gate coupled thereto. Therefore, the voltage on these floating gates will not only increase proportionally to the p-well voltage that is capacitively coupled to it, but also due to the 2-5% coupling from the select gate. In Figure 13, it is assumed that the coupling from the select gate adds an additional IV to the floating gate voltage. Thus, the floating gate voltage 422 rises to a maximum of 10V at the beginning of the erase voltage pulse, as compared to the 9V maximum for the ideal case depicted in FIG. 11 . The erase potential on the tunnel dielectric region of the end memory cells is given in the graph of Figure 13 below. The erase potential at the beginning of the erase voltage pulse is about 10V, or about 1V less than the ideal 11V erase potential. the

NAND串的不邻近于选择栅极的存储器单元(即，除了NAND串的末端存储器单元以外的所有存储器单元)在本文中可称为所述串的内部存储器单元。在图12中，NAND串的内部存储器单元是存储器单元504、506、508、510、512和514。尽管内部存储器单元将经历将减少其擦除电位的来自相邻浮动栅极的电容性耦合(下文论述)，但其程度比末端存储器单元的程度小。因此，内部存储器单元将大体上如早先描述的理想情况而表现，且具有约11V的擦除电位(假定单元处于编程状态，其中在擦除电压脉冲之前浮动栅极电压约-1V)。由于与内部存储器单元相比，末端存储器单元的隧道氧化物层上的电位较低，因此末端存储器单元在施加一个或一个以上擦除电压脉冲之后将较缓慢地擦除且不会与内部存储器单元一样深地擦除(将具有较少的从其浮动栅极转移的电子)。  The memory cells of a NAND string that are not adjacent to the select gate (ie, all but the end memory cells of the NAND string) may be referred to herein as internal memory cells of the string. In FIG. 12 , the internal memory cells of the NAND string are memory cells 504 , 506 , 508 , 510 , 512 , and 514 . Although inner memory cells will experience capacitive coupling from adjacent floating gates (discussed below) that will reduce their erase potential, but to a lesser extent than end memory cells. Thus, the internal memory cell will behave substantially as the ideal case described earlier, with an erase potential of about 11V (assuming the cell is in a programmed state with a floating gate voltage of about -1V prior to the erase voltage pulse). Due to the lower potential on the tunnel oxide layer of the end memory cells compared to the inner memory cells, the end memory cells will erase more slowly after one or more erase voltage pulses are applied and will not separate from the inner memory cells. erases as deeply (will have fewer electrons transferred from its floating gate). the

当浮动栅极上的电荷高于预定电平(低于预定电平的阈值电压)时，NAND串的存储器单元被验证为经擦除。由于对末端存储器单元的浮动栅极的额外耦合，擦除操作的总时间增加，以便充分擦除这些末端存储器单元。内部存储器单元可施加在数目N的擦除电压脉冲之后充分擦除，而NAND串的末端存储器单元可能不会充分擦除，直到施加N+1或N+1以上的擦除电压脉冲为止。  The memory cells of the NAND string are verified as erased when the charge on the floating gate is above a predetermined level (threshold voltage below the predetermined level). Due to the additional coupling to the floating gates of the end memory cells, the total time of the erase operation is increased in order to fully erase these end memory cells. Internal memory cells may be fully erased after application of a number N of erase voltage pulses, whereas end memory cells of a NAND string may not be fully erased until N+1 or more erase voltage pulses are applied. the

图12通过箭头536说明NAND串的个别存储器单元的浮动栅极之间的额外电容性耦合效应。举例来说，WL0和WL1上相邻浮动栅极之间的耦合可为2-5％的数量级，但可取决于存储器单元的尺寸和形状而更小或更大。由此，存储器单元516的浮动栅极上存在的电压将影响存储器单元514的浮动栅极的电压，反过来也是这样。类似的耦合将存在于连接到WL2的存储器单元514和512的浮动栅极之间，以此类推。此耦合在两个方向上存在，如箭头536上的双头所指示。这些耦合效应将在各种电平下的NAND串的所有存储器单元之间看见，但耦合影响将小于对末端存储器单元的影响，因为相邻控制栅极和浮动栅极上的偏置电压不同于选择栅极上的偏置条件。在擦除电压脉冲存在期间，每一浮动栅极的电压显著小于选择栅极处存在的电压。因此，由于个别存储器单元的浮动栅极之间的耦合而在每一浮动栅极中诱发的电压量将小于由于耦合到邻近选择栅极而在末端存储器单元的浮动栅极中诱发的电压。然而，NAND串的每一存储器单元可预期具有在其浮动栅极处存在的略微不同的净电荷以及由于此耦合而带来的相应不同的擦除 行为。  FIG. 12 illustrates by arrow 536 the effect of additional capacitive coupling between the floating gates of individual memory cells of a NAND string. For example, the coupling between adjacent floating gates on WL0 and WL1 can be on the order of 2-5%, but can be less or greater depending on the size and shape of the memory cell. Thus, the voltage present on the floating gate of memory cell 516 will affect the voltage of the floating gate of memory cell 514, and vice versa. Similar coupling will exist between the floating gates of memory cells 514 and 512 connected to WL2, and so on. This coupling exists in both directions, as indicated by the double head on arrow 536 . These coupling effects will be seen between all memory cells of a NAND string at various levels, but the coupling effects will be smaller than for the end memory cells because the bias voltages on adjacent control and floating gates are different from Selects the bias conditions on the gate. During the presence of the erase voltage pulse, the voltage at each floating gate is significantly less than the voltage present at the select gate. Thus, the amount of voltage induced in each floating gate due to coupling between the floating gates of individual memory cells will be less than the voltage induced in the floating gates of end memory cells due to coupling to adjacent select gates. However, each memory cell of a NAND string can be expected to have a slightly different net charge present at its floating gate and a correspondingly different erase behavior due to this coupling. the

图14A展示在数据已写入存储器阵列之后四状态或四级存储器装置的擦除(E)和编程(A、B、C)阈值电压VT分布。图14B描绘在擦除操作已完成之后的同一四状态存储器装置。单独描绘用于内部字线和末端字线的存储器单元的阈值电压分布。分布430展示用于内部字线的阈值电压分布，内部字线比由分布432描绘的末端字线更深地擦除。在一些NAND存储器装置实施方案中，由于来自选择栅极的电容性电荷耦合，内部存储器单元将比末端存储器单元深约0.5-1V而擦除。内部和末端字线两者的存储器单元大体上均相比所需来说更深地擦除。为保证在许多写入/擦除循环之后可以一个擦除电压脉冲擦除所有或大多数存储器单元，第一擦除电压脉冲的经选择大小一般将大于在一个脉冲中擦除新装置(未经历许多写入/擦除循环)的所有单元所需的大小。因此，新存储器装置在经历擦除操作之后可具有如图14B所示的阈值电压分布。  Figure 14A shows erased (E) and programmed (A, B, C) threshold voltage VT distributions for a four-state or four-level memory device after data has been written into the memory array. Figure 14B depicts the same four-state memory device after the erase operation has completed. Threshold voltage distributions of memory cells for inner word lines and end word lines are depicted separately. Distribution 430 shows the threshold voltage distribution for interior word lines that are more deeply erased than the end word lines depicted by distribution 432 . In some NAND memory device implementations, the inner memory cells will be erased about 0.5-1V deeper than the end memory cells due to capacitive charge coupling from the select gate. The memory cells of both the inner and end word lines are generally erased deeper than needed. To ensure that all or most of the memory cells can be erased with one erase voltage pulse after many write/erase cycles, the selected size of the first erase voltage pulse will generally be larger than that for erasing new devices (unexperienced) in one pulse. required size of all cells for many write/erase cycles). Accordingly, a new memory device may have a threshold voltage distribution as shown in FIG. 14B after undergoing an erase operation. the

当在NAND串级或更高处(例如，在区块或串的其它单位上)执行许多存储器单元的擦除验证时，存储器单元之间完全不同的擦除时间或行为可导致过度压紧和过度擦除某些存储器单元。举例来说，在尝试充分擦除所述串的末端存储器单元同时可能过度擦除NAND串的内部存储器单元。如先前描述，内部存储器单元将比末端存储器单元更快地擦除。如果在NAND串级处执行验证，那么NAND串将继续在p阱处接收擦除电压脉冲，直到擦除所述串的每一存储器单元为止。因此，即使内部存储器单元可在比末端存储器单元更少数目的擦除电压脉冲之后充分擦除，但内部存储器单元将接收额外的擦除电压脉冲，直到所述串的每一存储器单元被验证为经擦除为止。  When performing erase-verify of many memory cells at the NAND string level or higher (e.g., on a block or other unit of string), disparate erase times or behaviors between memory cells can lead to over compaction and Some memory cells are over-erased. For example, the interior memory cells of a NAND string may be over-erased while attempting to fully erase the end memory cells of the string. As previously described, interior memory cells will erase faster than end memory cells. If verify is performed at the NAND string level, the NAND string will continue to receive erase voltage pulses at the p-well until every memory cell of the string is erased. Thus, even though an interior memory cell can be fully erased after a fewer number of erase voltage pulses than an end memory cell, the interior memory cell will receive additional erase voltage pulses until each memory cell of the string is verified as verified. until erased. the

由于过度擦除而在内部存储器单元上放置比必要压力更大的压力。由于末端存储器单元的较慢擦除时间而带来的过度擦除内部存储器单元可减少内部存储器单元和整个非易失性存储器系统的使用寿命。如此项技术中理解，在晶体管的隧道氧化物层上施加较大的电位压紧氧化物材料。隧道氧化物层上足够高的电位的施加以及许多次较低电位的施加可最终导致氧化物层的损坏。  Putting more stress than necessary on the internal memory cells due to over-erasing. Excessive erasure of internal memory cells due to slower erase times of end memory cells can reduce the lifetime of the internal memory cells and the entire non-volatile memory system. As understood in the art, applying a large potential across the tunnel oxide layer of a transistor compacts the oxide material. Application of a sufficiently high potential on the tunnel oxide layer and many applications of lower potentials can eventually lead to damage to the oxide layer. the

由于可执行额外操作来改变擦除之后存储器单元的阈值电压，所以存储器单元之间完全不同的擦除行为也可导致擦除操作时间增加。当擦除快闪存储器单元时，目标是所有经擦除单元均具有在预定负阈值电压范围内的负阈值电压。然而如所说明，擦除过程可能导致一些单元具有低于预定范围的负阈值电压。具有过低的阈值电压的存储器单元可能随后不能正确编程，或可能导致其它单元不能正确编程(例如，通过增加程序干扰发生的概率)。因此，过度擦除的装置将常常经历所谓的软编程。具有显著低于预定范围 内的值的阈值电压的存储器单元将接收少量的编程，使得阈值电压升高到处于预定范围内。软编程过程要求执行额外的操作且由于增加的擦除时间而降低存储器性能，因为软编程通常认为是擦除操作的一部分。  Disparate erase behaviors between memory cells may also result in increased erase operation times since additional operations may be performed to change the threshold voltage of the memory cells after erasure. When erasing flash memory cells, the goal is for all erased cells to have a negative threshold voltage within a predetermined range of negative threshold voltages. However, as illustrated, the erase process may result in some cells having negative threshold voltages below the predetermined range. Memory cells with threshold voltages that are too low may subsequently not program properly, or may cause other cells to program incorrectly (eg, by increasing the probability of program disturb occurring). Consequently, over-erased devices will often undergo so-called soft programming. Memory cells with a threshold voltage significantly lower than a value within the predetermined range will receive a small amount of programming such that the threshold voltage is raised to be within the predetermined range. The soft programming process requires additional operations to be performed and degrades memory performance due to increased erase time since soft programming is generally considered a part of the erase operation. the

根据一个实施例，将正擦除的一组存储器单元的字线划分为独立验证的子组，使得可将额外的擦除脉冲提供到具有较慢擦除存储器单元的选择字线。以此方式，较快擦除字线不会过度擦除，且组中的所有字线的存储器单元在擦除操作之后将具有相同(或大体上相同)的阈值电压分布。  According to one embodiment, the word lines of a group of memory cells being erased are divided into independently verified subsets so that additional erase pulses can be provided to selected word lines with slower erasing memory cells. In this way, faster erasing word lines will not be over-erased, and the memory cells of all word lines in the group will have the same (or substantially the same) threshold voltage distribution after the erase operation. the

图15是描绘根据一个实施例的擦除一组存储器单元的方法的流程图。所属领域的技术人员将了解，根据图15的方法可并行地在多个NAND串上操作，例如以擦除存储器单元的区块。另外，根据所述实施例，也可在单元的其它单位上操作。在一个实施例中，可针对图7的擦除步骤340执行根据图15的流程图的擦除。在一个实施例中，在控制器318从主机接收到擦除或编程一组存储器单元的请求之后执行根据图15的擦除。  Figure 15 is a flowchart depicting a method of erasing a group of memory cells according to one embodiment. Those skilled in the art will appreciate that the method according to FIG. 15 can operate on multiple NAND strings in parallel, eg, to erase blocks of memory cells. Additionally, according to the described embodiments, operations may also be performed on other units of the unit. In one embodiment, erasing according to the flowchart of FIG. 15 may be performed for the erasing step 340 of FIG. 7 . In one embodiment, erasing according to FIG. 15 is performed after the controller 318 receives a request from the host to erase or program a group of memory cells. the

在步骤440使NAND串的位线、源极线、源极选择栅极线和漏极选择栅极线浮动。在步骤442，将零伏(或接地)施加于NAND串的每一字线。步骤440和442实现可包含NAND串或并联的多个NAND串的整个组存储器单元的擦除。在步骤444，将擦除电压脉冲V_erase施加于NAND串的p阱区。在步骤446，针对擦除状态验证连接到内部字线的存储器单元。将连接到末端字线的存储器单元从验证排除，使得仅验证内部存储器单元。通过向末端字线施加足以接通存储器单元(无论其是否被擦除)的电压来从验证中排除末端字线。此电压可大于施加到内部字线的擦除验证电压E_veri_fy。在步骤446可使用许多电压电平。举例来说，可使用足够大以接通编程到最高状态的存储器单元的电压，但仅略微大于擦除验证电压的电压在多数实施例中将是足够的。重要因素在于，在验证内部字线同时，连接到末端字线的存储器单元为传导的。  At step 440 the bit line, source line, source select gate line and drain select gate line of the NAND string are floated. At step 442, zero volts (or ground) is applied to each word line of the NAND string. Steps 440 and 442 effectuate the erasure of an entire group of memory cells, which may comprise a NAND string or multiple NAND strings connected in parallel. In step 444, an erase voltage pulse _Verase is applied to the p-well region of the NAND string. In step 446, the memory cells connected to the internal word lines are verified for an erased state. Memory cells connected to end word lines are excluded from verification so that only interior memory cells are verified. End word lines are excluded from verification by applying a voltage to the end word lines sufficient to turn on the memory cell (whether it is erased or not). This voltage may be greater than the erase verify voltage E _{verif y} applied to the internal word lines. Many voltage levels may be used at step 446 . For example, a voltage large enough to turn on memory cells programmed to the highest state can be used, but a voltage only slightly greater than the erase verify voltage will be sufficient in most embodiments. The important factor is that the memory cells connected to the end word lines are conductive while the inner word lines are being verified.

在步骤448，确定每一NAND串在步骤446是否成功验证为已擦除其内部存储器单元。在一个实施例中，仅在每个NAND串成功验证为已擦除其内部存储器单元时认为步骤448和内部存储器单元擦除成功。在另一实施例中，如果仅预定数目的NAND串成功验证为已擦除其内部存储器单元，那么认为步骤448和内部存储器单元擦除成功。通过基于预定数目的NAND串而不是每个NAND串来确定内部存储器单元擦除成功，验证过程可在达到最大擦除循环数目之前停止(步骤450)。这可避免由于一个或少量难以擦除或有缺陷的NAND串而过度擦除NAND串。  At step 448, it is determined whether each NAND string was successfully verified at step 446 as having its internal memory cells erased. In one embodiment, step 448 and the internal memory cell erase are considered successful only if each NAND string successfully authenticates as having its internal memory cells erased. In another embodiment, step 448 and the internal memory cell erasure is considered successful if only a predetermined number of NAND strings are successfully verified as having their internal memory cells erased. By determining internal memory cell erase success based on a predetermined number of NAND strings rather than each NAND string, the verification process can stop before reaching the maximum number of erase cycles (step 450). This avoids over-erasing of NAND strings due to one or a small number of hard-to-erase or defective NAND strings. the

如果在步骤448没有成功验证所有或预定数目的NAND串，那么方法分支到步骤 450，其中针对擦除限制值检查验证计数器VC。验证计数器用于限制擦除循环的重复的数目。擦除限制的一个实例是8，然而可使用其它值。如果验证计数器小于擦除限制值，那么VC递增1，且擦除电压脉冲的值V_erase步进增加第一步长大小或递增值ΔVERAI。在一个实施例中，ΔVERAI约为0.5V到1V。  If at step 448 all or a predetermined number of NAND strings are not successfully verified, then the method branches to step 450 where the verify counter VC is checked against an erase limit value. A verify counter is used to limit the number of repetitions of the erase cycle. One example of an erasure limit is 8, however other values may be used. If the verify counter is less than the erase limit value, then VC is incremented by 1, and the value Verase of the _erase voltage pulse is incremented stepwise by a first step size or increment value ΔVERAI. In one embodiment, ΔVERAI is approximately 0.5V to 1V.

在一个实施例中选择在步骤444施加的第一擦除电压脉冲为具有一量值，使得在写入擦除循环之前和之后，连接到内部字线的单元恰好在施加第一脉冲之后擦除而不会过度擦除。以此方式，可在一个脉冲中擦除内部存储器单元，使得对于大部分时间，将在步骤440到446的恰好一次重复之后验证内部字线。因此，ΔVERAI可为相对小的值，以便在需要进一步重复的那些情况下(例如，许多写入擦除循环之后)恰好擦除内部存储器单元。将参看图18A和18B论述关于可根据实施例使用的各种步长大小的更多细节。  In one embodiment, the first erase voltage pulse applied at step 444 is selected to have a magnitude such that cells connected to internal word lines are erased just after the first pulse is applied, before and after the write-erase cycle. without over-erasing. In this way, the internal memory cells can be erased in one pulse, so that for most of the time, the internal word line will be verified after exactly one iteration of steps 440-446. Thus, ΔVERAI may be a relatively small value so that the internal memory cells are just erased in those cases where further repetition is required (eg, after many write-erase cycles). More details on the various step sizes that may be used in accordance with embodiments will be discussed with reference to Figures 18A and 18B. the

如果验证计数器不小于8，那么方法进行到步骤452，其中将未验证NAND串的数目与预定数目进行比较。如果未验证的数目小于或等于预定数目，那么方法进行到步骤458。如果未验证的串的数目不小于预定数目，那么在步骤454针对操作报告失败状态。步骤452是可选的。举例来说，在基于少于全部NAND串认为步骤448成功的实施例中，可省略步骤448。  If the verification counter is not less than 8, then the method proceeds to step 452 where the number of unverified NAND strings is compared to a predetermined number. If the unverified number is less than or equal to the predetermined number, then the method proceeds to step 458 . If the number of unverified strings is not less than the predetermined number, then at step 454 a failure status is reported for the operation. Step 452 is optional. For example, step 448 may be omitted in embodiments where step 448 is considered successful based on less than all NAND strings. the

在步骤448或452的是(yes)分支之后，内部字线的存储器单元已验证为经擦除。另外，连接到正擦除的组的所有字线的所有存储器单元由于步骤440到446而使其浮动栅极电荷增加(电荷随电子移除而增加)。然而，末端存储器单元仍未验证为处于擦除状态。如先前描述，这些末端存储器单元比内部存储器单元更慢地擦除。因此，确认较快的存储器单元现已擦除之后，注意力可指向末端存储器单元以因此提供额外的擦除。以此方式，一组存储器单元的内部和末端存储器单元在擦除操作完成之后将被擦除到约相同的电平。  After the yes branch of step 448 or 452, the memory cells of the inner word line have been verified as erased. Additionally, all memory cells connected to all word lines of the group being erased have their floating gate charge increased (charge increases as electrons are removed) due to steps 440-446. However, the end memory cells have not yet been verified as being in an erased state. As previously described, these end memory cells are erased more slowly than interior memory cells. Thus, after confirming that the faster memory cells have now been erased, attention can be directed to the end memory cells to thus provide additional erasure. In this way, the inner and end memory cells of a group of memory cells will be erased to approximately the same level after the erase operation is complete. the

在步骤458，将验证计数器VC重设为零。另外，擦除电压V_erase步进增加第二递增大小ΔVERA₂。ΔVERA可大于ΔVERAI。在一个实施例中，ΔVERA2可为约1V到2V。ΔV_ER_A2优选经选择以使得在以增加的电平施加单个擦除电压脉冲之后，将在写入/擦除循环之前和之后都擦除末端存储器单元。在步骤460，再次使位线、源极线、源极选择栅极线和漏极选择栅极线浮动。在步骤462，抑制内部字线进一步擦除且启用末端字线用于进一步擦除。可在后续擦除电压脉冲期间通过浮动内部字线来抑制对内部存储器单元的擦除。可通过向末端字线施加0V来启用末端存储器单元以擦除。在设置此条件之后，将处于增加电平的第一擦除电压脉冲施加于所述组存储器单元。在步骤466，针对擦除 状态验证末端字线，同时从验证中排除内部字线。再次，如步骤446中，此可通过向末端字线施加擦除验证电压，同时向内部字线施加足以接通内部字线的存储器单元(不管其状态如何)的电压来完成。此施加于内部字线的电压将大于施加于末端字线的擦除验证电压。然而应注意，在一些实施例中，可针对擦除状态在步骤466验证整个NAND串。内部存储器单元已验证为经擦除，且因此其在擦除验证电压施加下应传导。因此，在此替代实施例中可在步骤466验证所述串的每一存储器单元。然而，可能优选向内部存储器单元施加较大的电压，以便恰好对仍未验证的末端字线实施验证。  At step 458, the verification counter VC is reset to zero. Additionally, _{the erase voltage Verase} is stepped up by a second incremental magnitude ΔVERA ₂ . ΔVERA may be greater than ΔVERAI. In one embodiment, ΔVERA2 may be about 1V to 2V. ΔV _E R _A2 is preferably chosen such that after application of a single erase voltage pulse at an increasing level, the end memory cells will be erased both before and after the write/erase cycle. At step 460, the bit line, source line, source select gate line and drain select gate line are again floated. In step 462, the inner word lines are inhibited from further erasing and the end word lines are enabled for further erasing. Erasing of interior memory cells can be inhibited by floating the interior word lines during subsequent erase voltage pulses. The end memory cells can be enabled for erasing by applying 0V to the end word line. After setting this condition, a first erase voltage pulse at an increasing level is applied to the group of memory cells. In step 466, the end word lines are verified for the erased state while excluding inner word lines from verification. Again, as in step 446, this can be accomplished by applying an erase verify voltage to the end word lines while applying a voltage to the inner word lines sufficient to turn on the memory cells of the inner word lines, regardless of their state. The voltage applied to the inner word lines will be greater than the erase verify voltage applied to the end word lines. It should be noted, however, that in some embodiments, the entire NAND string may be verified at step 466 for the erased state. The internal memory cell has been verified as erased, and therefore it should conduct under erase verify voltage application. Accordingly, each memory cell of the string may be verified at step 466 in this alternate embodiment. However, it may be preferable to apply a larger voltage to the interior memory cells in order to perform verification on just the end word lines that are not yet verified.

在步骤468，确定每一NAND串是否成功验证为已擦除其末端存储器单元。类似于步骤448，当所有或仅预定数目的NAND串成功验证时可作出在步骤468成功的确定。如果所有或预定数目的NAND串成功验证，那么在步骤470报告通过状态。如果所有或预定数目没有成功验证，那么在步骤472针对擦除限制值检查验证计数器。如果验证计数器小于限制，那么方法进行到步骤474，其中验证计数器递增1且擦除电压V_erase步进增加第三递增步长大小ΔVE_RA₃。  In step 468, it is determined whether each NAND string was successfully verified as having its end memory cells erased. Similar to step 448, the determination of success at step 468 may be made when all or only a predetermined number of NAND strings successfully authenticate. If all or a predetermined number of NAND strings are successfully verified, then at step 470 a pass status is reported. If all or a predetermined number are not successfully authenticated, then at step 472 the authentication counter is checked against the erase limit value. If the verify counter is less than the limit, the method proceeds to step 474 where the verify counter is incremented by 1 and the _erase voltage Verase is stepped up by a third increment step size ΔVE _R A ₃ .

在一个实施例中，ΔVERA₃为与ΔVERI相同的值。在其它实施例中，ΔVERA3大于ΔVERAI，因为末端存储器单元擦除较慢且可得益于较大的递增值以加速其擦除。步骤458和474的结果是，在针对向末端存储器单元首先施加擦除电压而验证内部字线之后，擦除电压脉冲增加较大量。如果需要多次重复以便完全擦除末端存储器单元，那么随后在步骤474其将增加较小量。再次，下文将论述用于递增值的更多细节和替代方案。如果验证计数器不小于8，那么在步骤476将未验证NAND串的数目与预定数目进行比较。类似于步骤452，步骤476是可选的。如果未验证串的数目小于预定数目，那么在步骤470报告通过状态。然而，如果未验证NAND串的数目大于预定数目，那么在步骤454报告失败状态。  In one embodiment, ΔVERA ₃ is the same value as ΔVERI. In other embodiments, ΔVERA3 is greater than ΔVERAI because the end memory cells are slower to erase and may benefit from a larger increment value to speed up their erasure. As a result of steps 458 and 474, the erase voltage pulse is increased by a larger amount after the inner word line is verified for first applying the erase voltage to the end memory cells. If multiple iterations are required to completely erase the end memory cells, then at step 474 it will be incremented by a smaller amount. Again, more details and alternatives for incrementing the value are discussed below. If the verification counter is not less than 8, then at step 476 the number of unverified NAND strings is compared to a predetermined number. Similar to step 452, step 476 is optional. If the number of unverified strings is less than the predetermined number, then at step 470 a pass status is reported. However, if the number of unverified NAND strings is greater than the predetermined number, a failure status is reported at step 454 .

图16是展示作为图15的擦除操作的一部分而执行的各种子操作的偏置条件的表。列480陈述用于擦除正擦除的字线组中所有字线的存储器单元的偏置条件。列480对应于图15的步骤440到444。在这些步骤中，每一字线的所有存储器单元通过从其浮动栅极转移电子而使其浮动栅极处的电荷增加。位线和源极线如同源极和漏极选择栅极线一样浮动。每一字线供以0V以便启用其擦除。p阱接收所述擦除电压，且借助于通过向字线施加0V和向p阱施加V_erase而产生的电位来从所述组的每一存储器单元的浮动栅极转移电子。  FIG. 16 is a table showing bias conditions for various sub-operations performed as part of the erase operation of FIG. 15 . Column 480 states the bias conditions for erasing the memory cells of all word lines in the group of word lines being erased. Column 480 corresponds to steps 440 to 444 of FIG. 15 . During these steps, all memory cells of each word line have their charge increased at their floating gates by transferring electrons from their floating gates. The bit and source lines are floating like the source and drain select gate lines. Each word line is powered with 0V to enable its erase. The p-well receives the erase voltage and transfers electrons from the floating gate of each memory cell of the set by means of a potential generated by applying 0V to the word line and _Verase to the p-well.

列482陈述用于针对擦除状态仅验证内部字线的偏置条件。列482对应于图15的步 骤446。位线浮动，而源极线处于V_DD。漏极选择栅极和源极选择栅极线供以足以接通两种选择栅极的正电压V_SG。V_SG通常大于V_DD。举例来说，在一个实施例中V_SG可为约4-4.5V。内部字线具备用于操作的擦除验证电压(例如，0V)。字线WL₀和字线WL_n 具备电压V_use1。V_use1可为如先前所述的电压范围，但通常经选择以便确保连接于字线WL₀和字线WL_n的存储器单元的传导。举例来说，V_usei可为大于经编程存储器单元的电位电压中任一者的电压。然而，在多数情况下使用仅略微大于擦除验证电压的值是足够的，因为在施加第一擦除电压脉冲之后甚至末端存储器单元也在一定程度上擦除。通过使用V_usei作为施加到字线WL₀和字线WL_n的电压，在步骤446将末端存储器单元从内部字线验证操作中排除。为了验证内部存储器单元是否擦除，将列482的偏置条件施加到NAND串并读出位线电压。如果内部存储器单元被充分深地擦除，那么其将处于接通状态且提供从源极线到位线的传导路径。将通过NAND串诱发电流且位线电压将增加。在预定时间量之后，由读出放大器读出或检查位线电压。如果位线电压已达到预定电平，那么内部存储器单元验证为经擦除。如果内部存储器单元没有被充分深地擦除，那么其将不会处于接通状态且因此将不会传导任何电流或将传导极少量的电流。由此，位线电压将不会增加到预定电平。当在预定时间量之后读出位线电压时，其将不会达到预定电平且内部存储器单元将不会验证为经擦除。  Column 482 states the bias conditions for verifying only the internal word lines for the erased state. Column 482 corresponds to step 446 of FIG. 15 . The bit line is floating while the source line is at V _DD . The drain select gate and source select gate lines are supplied with a positive voltage V _SG sufficient to turn on both select gates. V _S G is usually greater than V _DD . For example, V _SG may be about 4-4.5V in one embodiment. The internal word lines have an erase verify voltage (eg, 0V) for operation. Word line WL ₀ and word line WL _n have a voltage V _use1 . _Vuse1 can be a range of voltages as previously described, but is typically selected so as to ensure conduction of memory cells connected to word line WL ₀ and word line WL _n . For example, _Vusei can be a voltage greater than any of the potential voltages of programmed memory cells. However, in most cases it is sufficient to use a value only slightly larger than the erase verify voltage, since even the end memory cells are erased to some extent after application of the first erase voltage pulse. End memory cells are excluded from the internal word line verify operation at step 446 by using _Vusei as the voltage applied to word line WL ₀ and word line WL _n . To verify that the internal memory cells are erased, the bias conditions of column 482 are applied to the NAND strings and the bit line voltages are read. If the interior memory cell is sufficiently deeply erased, it will be in the ON state and provide a conduction path from the source line to the bit line. A current will be induced through the NAND string and the bit line voltage will increase. After a predetermined amount of time, the bit line voltage is sensed or checked by the sense amplifier. If the bit line voltage has reached a predetermined level, the interior memory cell is verified as erased. If an internal memory cell is not sufficiently deeply erased, it will not be in the on state and therefore will not conduct any current or will conduct a very small amount of current. Thus, the bit line voltage will not increase to a predetermined level. When the bit line voltage is sensed after a predetermined amount of time, it will not reach the predetermined level and the internal memory cells will not be verified as erased.

列484陈述用于仅擦除连接到所述正擦除的组的末端字线的存储器单元的偏置条件。列484对应于图15的步骤460到464。如同擦除所有字线，位线、源极线、源极选择栅极线和漏极选择栅极线全部浮动。另外，p阱将供以擦除电压V_erase。为了抑制内部字线(已验证为经擦除)的存储器单元的进一步擦除，内部字线浮动，而末端字线具备0V。以此方式，内部字线将耦合到p阱且在与其连接的存储器单元的隧道电介质区上不产生擦除电位。然而，通过向末端字线供应0V，那些存储器单元将被启用以擦除。因此，当将擦除电压脉冲施加到p阱时仅擦除末端字线的存储器单元。  Column 484 states the bias conditions for erasing only the memory cells connected to the end word line of the group being erased. Column 484 corresponds to steps 460 to 464 of FIG. 15 . Like all word lines are erased, the bit lines, source lines, source select gate lines and drain select gate lines are all floating. Additionally, the p-well will be supplied with an _erase voltage Verase. To inhibit further erasure of the memory cells of the inner word lines (which have been verified as erased), the inner word lines are floated while the end word lines have 0V. In this way, the internal word line will be coupled to the p-well and will not generate an erase potential on the tunnel dielectric region of the memory cell connected to it. However, by supplying 0V to the end word lines, those memory cells will be enabled for erasing. Thus, only the memory cells of the end word lines are erased when an erase voltage pulse is applied to the p-well.

列486陈述用于仅验证末端字线的擦除状态的偏置条件。列486对应于图15的步骤466。如同列482的内部字线验证操作，位线浮动，而源极线处于V_DD。p阱接地且漏极选择栅极和源极选择栅极通过电压V_SG接通。为了验证末端字线同时从验证中排除内部字线，将擦除验证电压E_Veri_fy(例如，0V)施加到字线WL₀和WL_n，同时将V_use1提供  到内部字线。V_CSei将确保内部字线的存储器单元的传导，使得可测试仅末端字线的擦除状态。如果末端存储器单元被充分擦除，那么其将在施加E_veri_fy电压下接通。位线电压将增加到或超过指示末端存储器单元经擦除的预定电平。如果末端存储器单元未被充分 擦除，那么其将保持断开或在施加E_veπfy电压下至少不会充分接通。位线电压将不会增加到指示末端存储器单元仍未擦除的预定电平。如先前论述，可以可选地验证整个NAND串，因为在步骤446已先前验证内部存储器单元。因此，擦除验证电压可施加到内部字线用于末端字线验证，因为其在擦除验证电压下会传导。然而，可能有益的是供应V_use1 以确保传导，以便仅测试末端存储器单元的擦除状态。  Column 486 states the bias conditions for verifying the erased state of only the end word lines. Column 486 corresponds to step 466 of FIG. 15 . As with the internal word line verify operation of column 482, the bit line is floating and the source line is at V _DD . The p-well is grounded and the drain and source select gates are turned on by voltage _VSG . To verify the end word lines while excluding the inner word lines from verification, an erase verify voltage E _Verify (eg, 0V) is applied to the word lines WL ₀ and WL _n while _Vuse1 is supplied to the inner _word lines. V _CSei will ensure conduction of the memory cells of the inner word lines so that only the erased state of the end word lines can be tested. If the end memory cell is sufficiently erased, it will turn on with the _{Ever if voltage} applied. The bit line voltage will increase to or beyond a predetermined level indicating that the end memory cells are erased. If the end memory cell is not sufficiently erased, it will remain off or at least not be fully on under application of the E _veπf y voltage. The bit line voltage will not increase to a predetermined level indicating that the end memory cells have not been erased. As previously discussed, the entire NAND string may optionally be verified since the interior memory cells were previously verified at step 446 . Therefore, an erase verify voltage can be applied to the inner word line for end word line verification because it conducts at the erase verify voltage. However, it may be beneficial to supply _Vuse1 to ensure conduction so that only the erased state of the end memory cells is tested.

图17A到图17C描绘根据实施例擦除的一组存储器单元的改进擦除阈值电压分布。图17A展示在数据已写入存储器阵列之后四级NAND存储器装置的擦除和编程阈值电压分布。图17B展示在单个擦除电压脉冲施加完成之后装置的存储器单元的擦除阈值电压分布。举例来说，图17B可对应于根据图16的偏置条件(列480)完成图15的步骤444的时间。通常，且如图17B所示，在施加第一擦除电压脉冲之后，仅内部字线的存储器单元(分布430所示)将充分擦除。末端字线的存储器单元(分布432所示)使负电荷从其浮动栅极移除，但并不足够，使得其处于实际擦除状态。这是由于末端字线的选择栅极与浮动栅极之间的耦合而带来的不同字线的完全不同的擦除行为。图17C展示在仅将额外擦除脉冲施加到所述正擦除的组的末端字线之后存储器单元的子组的擦除阈值分布。举例来说，图17C可对应于图15的步骤464完成之后的时间。这可在将一个额外擦除脉冲施加到末端字线之后，或在通过步骤460-474的多次重复而施加多个擦除脉冲之后。由于使用图15和16中描绘的方法，内部字线和末端字线使与其连接的存储器单元擦除到相似的阈值电压。因此，防止了由于较慢擦除末端字线带来的内部中间字线的过度擦除。通过划分存储器单元的不同子组的验证，已补偿完全不同的擦除行为，使得所有的存储器单元在大约相同的阈值电压分布中结束。  17A-17C depict improved erased threshold voltage distributions for a set of memory cells erased according to an embodiment. Figure 17A shows erase and program threshold voltage distributions for a four-level NAND memory device after data has been written to the memory array. Figure 17B shows the erased threshold voltage distributions of the memory cells of the device after a single erase voltage pulse application is complete. For example, FIG. 17B may correspond to when step 444 of FIG. 15 is completed according to the bias conditions of FIG. 16 (column 480). Typically, and as shown in Figure 17B, only the memory cells of the inner word line (shown as distribution 430) will be fully erased after application of the first erase voltage pulse. The memory cells of the end word line (shown as distribution 432) have negative charge removed from their floating gates, but not enough so that they are in the actual erased state. This is due to the completely different erase behavior of the different word lines due to the coupling between the select gate and the floating gate of the end word line. Figure 17C shows erase threshold distributions for subsets of memory cells after applying an additional erase pulse to only the end word line of the group being erased. For example, FIG. 17C may correspond to a time after step 464 of FIG. 15 is completed. This may be after applying one additional erase pulse to the end word line, or after applying multiple erase pulses through multiple repetitions of steps 460-474. As a result of using the method depicted in Figures 15 and 16, the inner and end word lines cause memory cells connected to them to be erased to similar threshold voltages. Thus, over-erasing of the inner middle word lines due to slower erasure of the end word lines is prevented. By dividing the verification of different subsets of memory cells, the disparate erase behavior has been compensated for so that all memory cells end up in approximately the same threshold voltage distribution. the

在其它实施例中可以不同方式进行NAND串内字线的划分。举例来说，NAND串的两个最末端字线(例如，WL₀、WL₁、WL_n-1和WL_n)可组合在一起作为末端字线，且其余字线(WL₂-WL_n-2)组合在一起作为内部字线。在此实施例中，图15的步骤446将包含验证字线WL₂-WL_n-2，且步骤462和466将执行以进一步擦除和验证字线WL₀、WL₁、WL_n-1和WL_n。在又一实施例中，六个或六个以上字线可组合在一起作为末端字线。也可实施其它组合。  The partitioning of the word lines within the NAND strings may be done differently in other embodiments. For example, the two endmost word lines of a NAND string (e.g., WL ₀ , WL ₁ , WL _n-1, and WL _n ) can be grouped together as the end word lines, and the remaining word lines (WL ₂ -WL _{n- 2} ) Combined together as internal word lines. In this embodiment, step 446 of FIG. 15 would involve verifying word lines WL ₂ -WL _n-2 , and steps 462 and 466 would be performed to further erase and verify word lines WL ₀ , WL ₁ , WL _n-1 and _WLn . In yet another embodiment, six or more word lines can be grouped together as an end word line. Other combinations can also be implemented.

图18A和18B描绘可根据各种实施例使用的擦除电压信号。图18A展示第一擦除电压脉冲，其为具有量值V_erasei的脉冲。第一脉冲可为施加到图15的步骤444处正擦除的存储器单元组的第一脉冲。此脉冲用于擦除所述组的所有存储器单元。在一些实施例中，擦除脉冲的第一值可为约15V到20V。在一个实施例中，优选以在写入/擦除循环之前 和之后，内部字线上的单元将在施加单个擦除电压脉冲之后恰好擦除(且不会过度擦除)的方式来选择第一擦除脉冲的量值。然而在写入/擦除循环之后，或由于个别构造的存储器装置的完全不同的参数，所有内部存储器单元在第一脉冲之后可能不被擦除。在其它实施例中，第一擦除电压脉冲可经选择以使得仅在写入/擦除循环之前或仅在有限数目的写入/擦除循环期间，内部存储器单元将在施加第一脉冲之后擦除。在扩展的写入/擦除循环之后，可能需要更多的脉冲。此技术可减少写入/擦除循环开始时的过度擦除，其代价是在扩展的写入/擦除循环之后更多的擦除电压脉冲。  18A and 18B depict erase voltage signals that may be used in accordance with various embodiments. Figure 18A shows a first erase voltage pulse, which is a pulse having a magnitude _Verasei . The first pulse may be the first pulse applied to the group of memory cells being erased at step 444 of FIG. 15 . This pulse is used to erase all memory cells of the set. In some embodiments, the first value of the erase pulse may be about 15V to 20V. In one embodiment, it is preferable to select the first bit in such a way that the cells on the internal word line will be just erased (and not over-erased) after applying a single erase voltage pulse before and after the write/erase cycle. The magnitude of an erase pulse. However, after a write/erase cycle, or due to completely different parameters of individually constructed memory devices, all internal memory cells may not be erased after the first pulse. In other embodiments, the first erase voltage pulse may be selected such that only before a write/erase cycle or only during a limited number of write/erase cycles, the internal memory cells will erase. After an extended write/erase cycle, more pulses may be required. This technique reduces over-erase at the beginning of a program/erase cycle at the expense of more erase voltage pulses after an extended program/erase cycle.

如图18A所示，在内部字线成功验证为擦除之前施加第二脉冲pulse₂。擦除电压信号从pulse₁到pulse₂增加步长大小ΔV_ERAI。增加ΔVERAI对应于图15的步骤456。在一个实施例中ΔVE_RAI可为约0.5V到1V。在施加第二擦除电压脉冲之后，所有内部字线被成功验证。这可对应于图15的步骤448。在所有内部字线经验证之后，仅针对末端存储器单元继续擦除。这些存储器单元较慢地擦除，因此针对第三擦除电压脉冲pulse₃的施加，擦除电压信号增加第二较大递增步长大小ΔV_ERA₂。此可对应于图15的步骤458。在一个实施例中优选ΔVERA₂经选择以使得在仅向末端存储器单元施加第一擦除电压脉冲(例如，pulse₃)之后，在写入/擦除循环之前和之后均将擦除所有末端存储器单元。在一个实施例中，ΔVERA₂为约2伏。pulse₃的施加对应于图15的步骤464。随后脉冲增加第三步长大小ΔVE_RA₃。这对应于图15的步骤474。ΔV_ERA₃在一个实施例中可等于ΔV_ERAI，或在其它实施例中可更大或更小。  As shown in FIG. 18A, the second pulse _pulse2 is applied before the internal word line is successfully verified as erased. The erase voltage signal increases step size ΔV _ER AI from pulse ₁ to pulse ₂ . Increasing ΔVERAI corresponds to step 456 of FIG. 15 . ΔVE _R AI may be about 0.5V to 1V in one embodiment. After applying the second erase voltage pulse, all internal word lines are successfully verified. This may correspond to step 448 of FIG. 15 . After all internal word lines are verified, erasing continues only for the end memory cells. These memory cells are erased more slowly, so for application of the third erase voltage pulse pulse ₃ the erase voltage signal is increased by the second larger incremental step size ΔV _ER A ₂ . This may correspond to step 458 of FIG. 15 . In one embodiment it is preferred that _ΔVERA2 is chosen such that after applying the first erase voltage pulse (eg pulse ₃ ) to only the end memory cells, all end memory cells will be erased both before and after the write/erase cycle unit. In one embodiment, ΔVERA ₂ is about 2 volts. The application of pulse ₃ corresponds to step 464 of FIG. 15 . Subsequent pulses increase by a third step size ΔVE _{RA 3} . This corresponds to step 474 of FIG. 15 . ΔV _ER A ₃ may be equal to ΔV _ER AI in one embodiment, or may be larger or smaller in other embodiments.

图18B描绘当执行图15的方法时可使用的擦除电压信号的替代实施例。在此实施例中，第一擦除电压脉冲选择为大于第二脉冲。第一擦除电压脉冲pulse₁₅经选择以引起较大的电压偏移(例如，约6V)。此擦除电压脉冲仍经理想选择以使得在施加单个脉冲之后，在某一数目的写入/擦除循环之前和之后将擦除内部存储器单元。然而认识到，在一些情况下可能使用一个以上脉冲来擦除所有内部存储器单元。在其它实施例中，第一擦除电压脉冲可经选择以使得仅在写入/擦除循环之前或仅在有限数目的写入/擦除循环期间，内部存储器单元将在施加第一擦除电压脉冲之后擦除。在扩展的写入/擦除循环之后，可能需要更多的脉冲。在图18B的实施例中，在所有内部存储器单元验证为经擦除之前需要第二和第三脉冲两者。第二擦除电压脉冲pulse₂比pulse₁小步长大小ΔV_ERA4。擦除电压信号的递减也对应于图15的步骤456。然而，并非递增擦除电压脉冲，其大小减小ΔVERA₄。这确保内部存储器单元在施加第二擦除电压脉冲之后不会过度擦除。使第二脉 冲较小，以在存储器单元的阈值电压中引起较小的偏移。如果需要第三擦除电压脉冲，如pulse₃所示，那么接着可使其增加步长大小ΔVE_RAI，以确保电子从那些存储器单元的浮动栅极持续转移。  FIG. 18B depicts an alternate embodiment of an erase voltage signal that may be used when performing the method of FIG. 15 . In this embodiment, the first erase voltage pulse is selected to be larger than the second pulse. The first erase voltage pulse ₁₅ is selected to cause a large voltage shift (eg, about 6V). This erase voltage pulse is still desirably chosen so that after a single pulse is applied, the internal memory cells will be erased before and after a certain number of write/erase cycles. It is recognized, however, that in some cases more than one pulse may be used to erase all internal memory cells. In other embodiments, the first erase voltage pulse may be selected such that the internal memory cells will be exposed to the first erase voltage pulse only before or only during a limited number of write/erase cycles. Erase after a voltage pulse. After an extended write/erase cycle, more pulses may be required. In the embodiment of Figure 18B, both the second and third pulses are required before all internal memory cells are verified as erased. The second erase voltage pulse pulse ₂ is smaller than pulse ₁ by a step size ΔV _E RA4 . The decrement of the erase voltage signal also corresponds to step 456 of FIG. 15 . However, instead of incrementing the erase voltage pulse, its magnitude is reduced by ΔVERA ₄ . This ensures that the internal memory cells are not over-erased after application of the second erase voltage pulse. The second pulse is made smaller to cause a smaller shift in the threshold voltage of the memory cell. If a third erase voltage pulse is required, as shown by pulse ₃ , it can then be increased by the step size ΔVE _R AI to ensure continued transfer of electrons from the floating gates of those memory cells.

在施加第三擦除电压脉冲之后，内部存储器单元验证为经擦除。图18B的其余部分与图18A相同。经施加以恰好调节末端存储器单元的第一擦除电压脉冲pulse₄从前一擦除电压脉冲大小增加量值ΔV_ERA₂-。这对应于图15的步骤458。在图18B的实施例中，需要额外的擦除电压脉冲来擦除末端存储器单元。因此第五擦除电压脉冲pulse₅增加值ΔVE_RA3超过第四擦除电压脉冲值。在一个实施例中，在施加第一擦除电压脉冲pulse₁之后，第二擦除电压脉冲pulse₂可具有与pulse₁相同的大小而不是大小减小。在此实施例中，随后用以擦除内部存储器单元所需的任何擦除电压脉冲均将增加值ΔVERAI，如图示。  After applying the third erase voltage pulse, the interior memory cells are verified as erased. The rest of Fig. 18B is the same as Fig. 18A. The first erase voltage pulse pulse ₄ applied to just adjust the end memory cells is increased in magnitude ΔV _ER A ₂ − from the previous erase voltage pulse magnitude. This corresponds to step 458 of FIG. 15 . In the embodiment of Figure 18B, an additional erase voltage pulse is required to erase the end memory cells. Therefore, the fifth erase voltage pulse pulse ₅ increases by a value ΔVE _RA3 exceeding the value of the fourth erase voltage pulse. In one embodiment, after the first erase voltage pulse pulse ₁ is applied, the second erase voltage pulse pulse ₂ may have the same magnitude as pulse ₁ instead of being reduced in magnitude. In this embodiment, any subsequent erase voltage pulses required to erase the internal memory cells will increase the value ΔVERAI, as shown.

图19是描绘用于执行图15的步骤456的根据一个实施例的方法的流程图。在图19中，如图示通过图18B的擦除电压脉冲来执行步骤456。在图15的步骤450中，首先在步骤490确定验证计数器VC是否等于零，指示目前为止仅一个擦除电压脉冲施加到存储器单元组。如果验证计数器等于零，指示这是对擦除电压脉冲大小的第一次改变，接着方法进行到步骤492，其中擦除电压脉冲大小步进减小值ΔV_ERA4。这将导致在下一重复期间施加类似于pulse₂的脉冲。然而如果验证计数器不等于零，指示这是对擦除电压信号的第二次或更多次改变，接着方法进行到步骤494，其中擦除电压信号步进增加ΔVERAI，导致类似于图18B的pulse₃的脉冲。从步骤492和494，方法再次进行到图15的步骤440。  FIG. 19 is a flowchart depicting a method according to one embodiment for performing step 456 of FIG. 15 . In FIG. 19, step 456 is performed as illustrated by the erase voltage pulse of FIG. 18B. In step 450 of FIG. 15, it is first determined at step 490 whether the verify counter VC is equal to zero, indicating that only one erase voltage pulse has been applied to the memory cell group so far. If the verify counter is equal to zero, indicating that this is the first change to the erase voltage pulse size, then the method proceeds to step 492, where the erase voltage pulse size is stepped down by a value ΔV _ERA4 . This will cause a pulse similar to pulse ₂ to be applied during the next repetition. However, if the verify counter is not equal to zero, indicating that this is a second or more change to the erase voltage signal, then the method proceeds to step 494, where the erase voltage signal is incremented by ΔVERAI, resulting in pulse ₃ similar to FIG. 18B pulse. From steps 492 and 494, the method proceeds again to step 440 of FIG. 15 .

电容性耦合也可导致在所谓软编程操作期间NAND串的存储器单元之间完全不同的行为。通常通过向经选择区块的所有字线同时施加软编程脉冲来实施软编程操作。在擦除一组存储器单元之后执行软编程。执行软编程以使所述组存储器单元的擦除阈值分布的宽度变窄，且还使所述组内个别存储器单元的擦除阈值分布标准化。软编程脉冲在幅值上低于常规编程脉冲(例如，如图6所示)，以避免单元到达编程状态。作为软编程结果而期望的是单元具有较窄的擦除阈值电压分布。因此，不期望阈值电压偏移到编程状态范围内。  Capacitive coupling can also lead to disparate behavior between memory cells of a NAND string during a so-called soft programming operation. Soft programming operations are typically performed by simultaneously applying soft programming pulses to all word lines of a selected block. Soft programming is performed after erasing a group of memory cells. Soft programming is performed to narrow the width of the distribution of erased thresholds for the group of memory cells and also to normalize the distribution of erased thresholds for individual memory cells within the group. The soft programming pulses are lower in amplitude than regular programming pulses (eg, as shown in FIG. 6 ) to avoid cells from reaching the programmed state. It is desirable as a result of soft programming that cells have a narrower distribution of erased threshold voltages. Therefore, shifting of the threshold voltage into the programmed state range is not expected. the

在施加每一软编程脉冲之后，实施类似于图10所示的典型擦除验证操作的验证操作。在软编程操作的验证期间，通过在其栅极接收擦除验证电压的每一存储器单元测试通过NAND串的传导。一旦经选择区块中的某一数目的NAND串在擦除验证操作期间已 到达非传导状态(指示所述串的至少一个单元已达到擦除验证电平)，那么软编程结束。软编程的结果为所述串中的擦除存储器单元的分布向上偏移而更接近擦除验证电平。通过使用软编程，即使存储器单元初始过度擦除，擦除阈值电压分布也可向上移位到接近擦除验证电平的电平。  After each soft programming pulse is applied, a verify operation similar to the typical erase verify operation shown in FIG. 10 is performed. During the verify of the soft programming operation, conduction through the NAND string is tested by each memory cell receiving an erase verify voltage at its gate. Once a certain number of NAND strings in the selected block have reached a non-conductive state during the erase verify operation (indicating that at least one cell of the string has reached the erase verify level), soft programming ends. The result of soft programming is that the distribution of erased memory cells in the string is shifted upwards closer to the erase verify level. By using soft programming, even if memory cells are initially over-erased, the erased threshold voltage distribution can be shifted upwards to a level close to the erase verify level. the

由于从选择栅极到NAND串的末端字线的存储器单元的电容性耦合，所述串的存储器单元的软编程行为不同。选择栅极与末端存储器单元之间的电容性耦合在软编程操作期间使这些单元变慢。因此，可预期末端字线的存储器单元在软编程之后将处于比内部字线的擦除状态更深的擦除状态。  The soft programming behavior of the memory cells of a NAND string differs due to the capacitive coupling from the select gates to the memory cells of the end word line of the string. Capacitive coupling between the select gates and the end memory cells slows down these cells during soft programming operations. Therefore, it is expected that the memory cells of the end word lines will be in a deeper erased state than the inner word lines after soft programming. the

图20展示在经历软编程之后NAND串的存储器单元的擦除阈值电压分布。分布430描绘在经历软编程之后内部字线存储器单元的擦除阈值分布。软编程已使此擦除阈值电压分布偏移而更接近擦除验证电平。由于当预定数目的NAND串在施加擦除验证电压下为非传导时用于软编程的验证将单元群组验证为成功软编程，因此某一数目的单元将使其阈值电压偏移超过擦除验证电平。具有高于擦除验证电平的阈值电压的实际数目将取决于采用的实际验证方案。举例来说，如果方案在单个串变为非传导时将软编程验证为完成，那么群组中的仅一个单元可高于验证电平。在其它方案中，群组内的数以千计的单元可使其阈值电压偏移恰好超过擦除验证电平。分布432描绘末端存储器单元的阈值电压。由于末端存储器单元的较慢的软编程时间，其阈值电压随着接近擦除验证电平而没有偏移。  Figure 20 shows erased threshold voltage distributions of memory cells of a NAND string after undergoing soft programming. Distribution 430 depicts the erased threshold distribution of interior word line memory cells after undergoing soft programming. Soft programming has shifted this erase threshold voltage distribution closer to the erase verify level. Since verification for soft programming verifies a group of cells as successfully soft programmed when a predetermined number of NAND strings are non-conductive under the applied erase verify voltage, a certain number of cells will have their threshold voltages shifted beyond the erased verify level. The actual number of threshold voltages with a higher erase verify level will depend on the actual verify scheme employed. For example, if a scheme verifies soft programming as complete when a single string becomes non-conductive, only one cell in a group may be above the verify level. In other schemes, thousands of cells within a group may have their threshold voltages shifted just beyond the erase verify level. Distribution 432 depicts the threshold voltages of the end memory cells. Due to the slower soft programming time of the end memory cells, their threshold voltages do not shift as they approach the erase verify level. the

根据一个实施例，将一组存储器单元的字线再次划分为子组，使得可以适合于字线的个别子组需要的方式实施软编程。方法类似于图15中描绘的擦除验证方法。所述组中的正软编程的所有字线均经历某种初始软编程。在验证所述组存储器单元或其子组已成功软编程之后，可仅针对末端字线执行额外软编程，以便将其移出其较深的擦除状态并更接近擦除验证电平。  According to one embodiment, the word lines of a group of memory cells are subdivided into subsets so that soft programming can be performed in a manner appropriate to the needs of individual subsets of word lines. The method is similar to the erasure verification method depicted in FIG. 15 . All word lines in the set that are being soft programmed undergo some initial soft programming. After verifying that the group of memory cells or a subset thereof has been successfully soft programmed, additional soft programming can be performed only for the end word lines in order to move them out of their deeper erased states and closer to the erase verify level. the

图21描绘在一个实施例中用于软编程的方法。举例来说，图21的方法可用于对存储器单元的区块的多个NAND串进行软编程。在一个实施例中，可针对图7的软编程步骤342执行根据图21的软编程。在步骤602，将软编程电压信号V_SP_GM设定为其初始值并将软编程计数器SPC设定为零。在步骤604将源极线、位线和源极选择栅极线接地。另外，将V_SG施加到漏极选择栅极线。可恰好在施加软编程脉冲之前将漏极选择栅极线电压降低到约2.5V，以在需要时允许升压以进行软编程抑制(步骤617)。在其它情况下不是这样。软编程抑制通过将升高到VDD的沟道仍可在某一程度上发生(步骤617)。 在步骤606，将第一软编程脉冲施加到所述正软编程的组的所有字线。在步骤608，使用擦除验证电压电平针对擦除状态验证所有字线的存储器单元。在一个实施例中，步骤608可包含仅验证内部字线的存储器单元，同时确保末端存储器单元的传导。然而，末端字线的存储器单元在多数情况下在施加擦除验证电压下无论如何都将传导，因为其比内部字线的存储器单元更慢地软编程。  Figure 21 depicts a method for soft programming in one embodiment. For example, the method of FIG. 21 can be used to soft program multiple NAND strings of a block of memory cells. In one embodiment, the soft programming according to FIG. 21 may be performed for the soft programming step 342 of FIG. 7 . In step 602, the soft programming voltage signal V _S P _G M is set to its initial value and the soft programming counter SPC is set to zero. In step 604 the source line, the bit line and the source select gate line are grounded. Additionally, _VSG is applied to the drain select gate line. The drain select gate line voltage may be lowered to about 2.5V just prior to applying the soft programming pulse to allow boosting for soft programming inhibition if needed (step 617). Not so in other cases. Soft programming inhibition can still occur to some extent by raising the channel to VDD (step 617). At step 606, a first soft programming pulse is applied to all word lines of the group being soft programmed. At step 608, the memory cells of all word lines are verified for the erased state using the erase verify voltage level. In one embodiment, step 608 may include verifying only the memory cells of the inner word line while ensuring conduction of the end memory cells. However, the memory cells of the end word lines will in most cases conduct anyway under the application of the erase verify voltage because they are soft programmed more slowly than the memory cells of the inner word lines.

在步骤610，将正软编程的区块中非传导NAND串的数目与预定数目进行比较。如果非传导串的数目不大于预定数目，那么在步骤612将软编程计数器SPC与预定限制值(例如20)进行比较。如果软编程计数器不小于20，那么针对软编程操作在步骤614报告失败状态。如果软编程计数器小于20，那么方法进行到步骤616，其中软编程计数器SPC递增1且软编程电压信号步进增加预定值。在步骤617，在步骤608的验证期间非传导(成功软编程)的NAND串被抑制进一步软编程。可通过向相应位线施加例如V_DD 的较高电压来抑制特定NAND串中的软编程。通过升高位线电压，经抑制NAND串的沟道区域在下一软编程循环期间将升压到高电压。存储器单元的浮动栅极与经抑制NAND串的沟道区域之间的电压差将过低而不能促使单元的进一步软编程。方法接着进行到步骤604以向所述组存储器单元施加额外的软编程脉冲。  At step 610, the number of non-conductive NAND strings in the block being soft programmed is compared to a predetermined number. If the number of non-conductive strings is not greater than the predetermined number, then at step 612 the soft program counter SPC is compared to a predetermined limit value (eg, 20). If the soft program counter is not less than 20, then a failure status is reported at step 614 for the soft program operation. If the soft program counter is less than 20, the method proceeds to step 616, where the soft program counter SPC is incremented by 1 and the soft program voltage signal is stepped up by a predetermined value. At step 617, NAND strings that were non-conductive (successfully soft programmed) during the verification of step 608 are inhibited from further soft programming. Soft programming in a particular NAND string can be inhibited by applying a higher voltage, such as V _DD , to the corresponding bit line. By raising the bit line voltage, the channel region of the suppressed NAND string will be boosted to a high voltage during the next soft programming cycle. The voltage difference between the floating gate of the memory cell and the channel region of the suppressed NAND string will be too low to induce further soft programming of the cell. The method then proceeds to step 604 to apply additional soft programming pulses to the group of memory cells.

如果非传导串的数目大于预定数目，指示存储器单元已成功经历软编程，那么在步骤618重设软编程计数器SPC。在一个实施例中，步骤618可进一步包含增加软编程电压信号。在一个实施例中，步骤618处的增加可与步骤616中的相同或为另一值。例如在一个实施例中，在步骤616，软编程电压信号递增步长大小ΔV_spgm1。在步骤618，其可递增步长大小ΔV_spgm2，其可大于ΔV_spgmi。在一个实施例中可使用类似于图18A的擦除电压信号的软编程电压信号。  If the number of non-conductive strings is greater than the predetermined number, indicating that the memory cell has successfully undergone soft programming, then at step 618 the soft programming counter SPC is reset. In one embodiment, step 618 may further include increasing the soft programming voltage signal. In one embodiment, the increment at step 618 may be the same as in step 616 or another value. For example, in one embodiment, at step 616 , the soft programming voltage signal is incremented by a step size ΔV _spgm1 . At step 618, it may increment the step size ΔV _spgm2 , which may be greater than ΔV _spgmi . A soft programming voltage signal similar to the erase voltage signal of Figure 18A may be used in one embodiment.

在步骤620，将源极线、位线和源极选择栅极线接地并将V_SG施加到漏极侧选择栅极线。在步骤622，抑制内部字线的软编程。可通过向内部字线施加约0V到3V的数量级的较小正电压来抑制内部字线的软编程。在一个实施例中，施加到内部字线的电压较大且为约5V到10V的数量级。举例来说，所述电压可为通常经施加以提升串的沟道区的电压以抑制编程或软编程的通过电压(V_paSs)。对于在步骤618-634的进一步重复中被抑制进一步软编程的NAND串(已验证为经软编程)，较高电压将足以确保经抑制NAND串的沟道区域被充分升压以避免进一步软编程。在步骤624，将软编程脉冲仅施加到正擦除的组的末端字线，以便进一步对末端存储器单元进行软编程。在步骤626，针对擦 除状态验证末端存储器单元字线，同时确保内部字线传导而不考虑其状态(从验证中排除内部字线)。可将擦除验证电压电平施加到末端字线，而将电压V_use1(足以确保内部字线的传导)施加到内部字线。以此方式，仅针对末端字线执行验证，同时从验证中排除内部字线。  In step 620, the source line, bit line and source select gate line are grounded and _VSG is applied to the drain side select gate line. In step 622, soft programming of internal word lines is inhibited. Soft programming of the internal word lines can be inhibited by applying a small positive voltage on the order of about 0V to 3V to the internal word lines. In one embodiment, the voltage applied to the inner word lines is large and on the order of about 5V to 10V. For example, the voltage may be a pass voltage (V _paSs ) that is typically applied to boost the voltage of the channel region of a string to inhibit programming or soft programming. For NAND strings that are inhibited from further soft programming in further iterations of steps 618-634 (verified to be soft programmed), the higher voltage will be sufficient to ensure that the channel region of the inhibited NAND string is sufficiently boosted to avoid further soft programming . In step 624, a soft programming pulse is applied only to the end word line of the group being erased to further soft program the end memory cells. In step 626, the end memory cell word lines are verified for the erased state, while ensuring that internal word lines conduct regardless of their state (exclude internal word lines from verification). An erase verify voltage level may be applied to the end word lines, while a voltage _Vuse1 (sufficient to ensure conduction of the inner word lines) is applied to the inner word lines. In this way, verification is performed only for the end word lines, while excluding inner word lines from verification.

在步骤628，将步骤626中确定的非传导串的数目与预定数目进行比较。如果非传导串的数目大于预定数目，指示末端字线的单元现已向上移位而接近于擦除验证电平，那么方法进行到步骤630，其中报告通过状态。如果非传导串的数目不大于预定数目，那么将软编程计数器与预定限制值进行比较。如果软编程计数器大于预定限制值，那么针对操作在步骤614报告失败状态。然而如果软编程计数器小于预定限制值，那么在步骤634将软编程计数器递增1且使软编程电压信号向上步进。在步骤635，在步骤626的验证期间非传导(成功软编程)的NAND串被抑制进一步软编程。方法接着进行到步骤620以进行末端存储器单元的进一步软编程。  In step 628, the number of non-conductive strings determined in step 626 is compared to a predetermined number. If the number of non-conducting strings is greater than the predetermined number, indicating that the cells of the end word line have now shifted up close to the erase verify level, then the method proceeds to step 630 where a pass status is reported. If the number of non-conducting strings is not greater than the predetermined number, then the soft program counter is compared to a predetermined limit value. If the soft program counter is greater than the predetermined limit value, then a failure status is reported at step 614 for the operation. However, if the soft program counter is less than the predetermined limit value, then at step 634 the soft program counter is incremented by 1 and the soft program voltage signal is stepped up. At step 635 , NAND strings that were non-conductive (successfully soft programmed) during the verify of step 626 are inhibited from further soft programming. The method then proceeds to step 620 for further soft programming of the end memory cells. the

在一个实施例中，步骤634使软编程电压信号递增与步骤616相同的大小，而在其它实施例中，使用其它值。举例来说，如果使用类似于图18B的擦除电压信号的软编程电压信号，那么步骤634可包含增加大小ΔV_spgm3(类似于ΔVE_RA3)，步骤618可包含增加大小ΔV_spgm2(类似于ΔVE_RA₂)，且步骤616可包含增加大小ΔV_spgmi(类似于ΔVERAI)。在此实施例中，步骤616可进一步包含在第一重复期间减小大小ΔV_spgm4(类似于ΔVE_RA4)和针对后续重复增加大小ΔVs_Pgm1。  In one embodiment, step 634 increments the soft programming voltage signal by the same magnitude as step 616, while in other embodiments other values are used. For example, if a soft programming voltage signal similar to the erase voltage signal of FIG. 18B is used, then step 634 may include increasing the magnitude ΔV _spgm3 (similar to ΔVE _RA 3 ), and step 618 may include increasing the magnitude ΔV _spgm2 (similar to ΔVE _R A ₂ ), and step 616 may include increasing the magnitude ΔV _spgm i (similar to ΔVERAI). In this embodiment, step 616 may further include decreasing the magnitude ΔV _spgm4 (similar to ΔVE _R A4 ) during the first iteration and increasing the magnitude ΔVs _Pgm1 for subsequent iterations.

在不同实施例中可以不同方式进行用于软编程的NAND串内字线的划分。举例来说，NAND串的两个最末端字线(例如，WL0、WL1、WL_n-1和WL_n)可组合在一起作为末端字线，且其余字线(WL2-WL_n-2)组合在一起作为内部字线。在此实施例中，图21的步骤622将包含抑制字线WL2-WLn-2，且将执行步骤624和626以进一步对字线WL0、WL1、WL_n-I和WL_n进行软编程和验证。在又一实施例中，六个或六个以上字线可组合在一起作为末端字线。也可实施其它组合。  The division of word lines within a NAND string for soft programming can be done differently in different embodiments. For example, the two endmost wordlines of a NAND string (e.g., WL0, WL1, WLn _-1 , and _WLn ) can be combined together as the end wordlines, and the remaining wordlines (WL2-WLn _-2 ) combined together as internal word lines. In this embodiment, step 622 of FIG. 21 would involve inhibiting word lines WL2-WLn-2, and steps 624 and 626 would be performed to further soft program and verify word lines WL0, WL1, _WLnI , and _WLn . In yet another embodiment, six or more word lines can be grouped together as an end word line. Other combinations can also be implemented.

图22陈述用于图21描绘的流程图的各种操作的偏置条件。列640陈述正擦除组的所有存储器单元的软编程操作的偏置条件。列640对应于图21的步骤604到606。位线、源极线和p阱处于0V以进行软编程。V_DD展示为针对位线电压带括号，以指示V_DD施加到被抑制软编程的那些NAND串。源极侧选择栅极线处于0V，而漏极侧选择栅极线 处于V_SG。将软编程脉冲V_spg_m施加到所述组的每一字线，以便升高与其连接的每一存储器单元的阈值电压。  FIG. 22 sets forth bias conditions for the various operations of the flowchart depicted in FIG. 21 . Column 640 states the bias conditions for the soft programming operation of all memory cells of the group being erased. Column 640 corresponds to steps 604 to 606 of FIG. 21 . The bit line, source line and p-well are at 0V for soft programming. V _DD is shown in parentheses for the bit line voltage to indicate that V _DD is applied to those NAND strings that are inhibited from soft programming. The source side select gate line is at 0V and the drain side select gate line is at V _SG . A soft programming pulse _Vspgm is applied to each word line of the group in order to raise the threshold voltage of each memory cell connected _thereto .

列642陈述用于验证所述组的所有存储器单元的软编程的偏置条件。列642对应于图21的步骤608。这些偏置条件与用于验证一组存储器单元中所有存储器单元的擦除的那些偏置条件相同。位线浮动且p阱处于0V，而将VD_D提供到源极线。两个选择栅极均由V_SG接通。将擦除验证电压施加到每一字线以确定所述串是否非传导且因此具有至少一个已达到擦除验证电平的存储器单元。  Column 642 states the bias conditions used to verify soft programming of all memory cells of the group. Column 642 corresponds to step 608 of FIG. 21 . These bias conditions are the same as those used to verify the erasure of all memory cells in a group of memory cells. The bit line is floating and the p-well is at 0V, while _VDD is supplied to the source line. Both select gates are turned on by _VSG . An erase verify voltage is applied to each word line to determine whether the string is non-conductive and thus has at least one memory cell that has reached the erase verify level.

列644陈述用于仅对末端字线进行软编程的偏置条件。列644对应于图21的步骤620到624。通过将VS_G供应到漏极侧选择栅极线来接通漏极侧选择栅极，并通过将0V供应到源极侧选择栅极线来断开源极侧选择栅极。向内部字线提供较低正电压V_use1(例如，0V到5V)。通过向内部字线供应较小正电压，与其连接的存储器单元可被抑制在施加软编程脉冲下进一步编程。末端字线接收软编程脉冲V_SP_GM以便经历进一步软编程。当已验证为经软编程的NAND串被抑制进一步软编程时，施加到内部字线的值V_usei可为相对高的电压(例如， V pa ss = 5 V - 10 V )而不是较小正电压。因为V_DD也施加到经抑制的串的位线，所以相对高的电压将导致经抑制NAND串的沟道区域在下一软编程循环期间升压到高电压。这保持存储器单元的浮动栅极与经抑制NAND串的沟道区域之间的电压差充分的低，使得单元的进一步软编程不会发生。  Column 644 states the bias conditions for soft programming only the end word lines. Column 644 corresponds to steps 620 to 624 of FIG. 21 . The drain side selection gate is turned on by supplying VS _G to the drain side selection gate line, and the source side selection gate is turned off by supplying 0V to the source side selection gate line. A lower positive voltage _Vuse1 (eg, 0V to 5V) is provided to the inner word line. By supplying a small positive voltage to the inner word line, memory cells connected to it can be inhibited from further programming under application of soft programming pulses. The end word lines receive soft programming pulses V _S P _G M to undergo further soft programming. When a NAND string that has been verified as soft programmed is inhibited from further soft programming, the value V _us ei applied to the inner word line may be a relatively high voltage (e.g., V pa ss = 5 V - 10 V ) instead of a smaller positive voltage. Because V _DD is also applied to the bit line of the suppressed string, the relatively high voltage will cause the channel region of the suppressed NAND string to be boosted to a high voltage during the next soft programming cycle. This keeps the voltage difference between the floating gate of the memory cell and the channel region of the suppressed NAND string sufficiently low that further soft programming of the cell does not occur.

列646陈述用于仅末端字线的软编程验证偏置条件。列646可对应于图21的步骤626。位线浮动，而源极线处于VDD。p阱处于零伏。通过将V_SO供应到漏极选择栅极线和源极选择栅极线来接通选择栅极两者。将V_USei施加到内部字线。如上所论述，在软编程期间使用的V_use1的值(列644)在一些情况下可大于0V到3V。用于验证的V_usei的值为0V到3V的数量级。其仅需要高于擦除验证电压以确保内部字线中软编程已经完成的单元处于传导状态。以此方式，可独立确定并验证末端字线上存储器单元的状态。因此，在软编程期间使用的Vuse1的值(例如，5V到10V)可不同于在软编程验证期间使用的值(例如，0V到3V)。将擦除验证电压或0V施加到末端字线。以此方式，从软编程验证中排除内部字线，同时末端字线经历验证。  Column 646 states the soft programming verify bias conditions for the end word lines only. Column 646 may correspond to step 626 of FIG. 21 . The bit line is floating while the source line is at VDD. The p-well is at zero volts. Both the select gates are turned on by supplying _VSO to the drain and source select gate lines. Apply V _US ei to the internal word lines. As discussed above, the value of _Vuse1 used during soft programming (column 644) may be greater than 0V to 3V in some cases. The value of V _use i used for verification is on the order of 0V to 3V. It only needs to be higher than the erase verify voltage to ensure that soft programmed cells in the internal word lines are in a conducting state. In this way, the state of the memory cells on the end word lines can be independently determined and verified. Therefore, the value of Vuse1 used during soft programming (eg, 5V to 10V) may be different from the value used during soft programming verification (eg, 0V to 3V). An erase verify voltage or 0V is applied to the end word lines. In this way, the inner word lines are excluded from soft programming verification, while the end word lines undergo verification.

图23描绘在经历根据图21和22的实施例的软编程之后一组存储器单元的阈值电压 分布。如图23所示，内部和末端字线的擦除阈值分布均已向上移动接近擦除验证电平。内部字线阈值电压分布430向上偏移接近擦除验证电平，如同通常将发生。末端字线分布432已由于额外软编程(步骤618-635)而向上移动接近擦除验证电平。  Figure 23 depicts threshold voltage distributions for a group of memory cells after undergoing soft programming according to the embodiment of Figures 21 and 22. As shown in Figure 23, the erase threshold distributions for both the inner and end word lines have shifted upwards close to the erase verify level. The internal word line threshold voltage distribution 430 is shifted upwards close to the erase verify level, as would normally occur. The end word line distribution 432 has been moved up close to the erase verify level due to the additional soft programming (steps 618-635). the

上述实例是针对NAND型快闪存储器而提供。然而，本发明的原理适用于利用串联结构的其它类型的非易失性存储器，包含当前现有的那些存储器和预期使用正开发的新技术的那些存储器。  The above examples are provided for NAND type flash memory. However, the principles of the present invention are applicable to other types of non-volatile memories that utilize cascaded structures, including those that currently exist and those that are expected to use new technologies that are being developed. the

出于说明和描述目的已呈现本发明的上述详细描述。不希望其为详尽的或将本发明限于所揭示的精确形式。鉴于以上教示，许多修改和变化是可能的。所描述的实施例经选择以便最好地解释本发明的原理及其实践应用，藉此使所属领域的其他技术人员能够以适合于所预期的特定应用的各种实施例形式及使用各种修改来最佳地利用本发明。希望本发明的范围由所附的权利要求书界定。  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to adopt the various embodiments and use them with various modifications as are suited to the particular use contemplated. to make best use of the present invention. It is intended that the scope of the invention be defined by the appended claims. the