CN101312384B - Method and apparatus for computing even-odd check information in communication network - Google Patents

Embodiment

For the ease of understanding, make an explanation in the face of the term that occurs in the context down.

SONET and SDH:1985, Bellcore proposes SONET (SynchronousOptical Network synchronous optical network) standard, and American National Standards Institute is through a series of relevant sonet standards.1989, the CCITT of CCITT accepted the SONET notion and has formulated SDH (Synchronous Digital Hierarchy, synchronous digital hierarchy) standard; Make it to become and not only be suitable for the current techique system that optical fiber also is suitable for microwave and satellite transmits, with SONET nuance is arranged, SDH/SONET has defined one group of speed and form in the optical fiber transmit optical signals; Usually be referred to as the Optical synchronization digital transmission network; Be one of basis of Broadband Integrated Service Digital Network B-ISDN, SDH/SONET adopts TDM (time division multiplexing) technology, is synchro system; By master clock control, the both is used for the backbone network transmission.

STS-N:Synchronous Transport Signal level N, synchronous driving signal in N rank among the SONET constitutes by transmitting expense and pure load, and N is a positive integer.

STS-Nc: together form the STS-Nc signal by N the pure load region cascade of STS-1.

STM-M:Synchronous Transport Module level M, SDH synchronous digital hierarchy N rank Synchronous Transport Module level-N.

AUG:Administrator Unit Group administrative unit groups forms by administrative unit is multiplexing, and for example, an AUG perhaps is made up of an AU-4 3 multiplexing forming of AU-3, and AUG itself can be multiplexed into the high-order Synchronous Transport Module level-N again.

AU-n:Administrator Unit administrative unit is made up of the virtual container VC-n at the same level that has the AU pointer, n=3 wherein, and 4, after administrative unit groups is multiplexing, become STM-1 frame structure part.Add the AU pointer by virtual container VC-3 and form AU-3; VC-4 adds the AU pointer and forms AU-4.

VC:Virtual Container virtual container; Be to set up the signal structure unit that road (path) layer connects among the SDH; Constitute by container or tributary unit and road expense two parts, comprise basic virtual container (VC-1 and VC-2) and high order virtual container (VC-3 and VC-4).

Container: container, container are the definition units of a pure year capacity, its size be written into G.702 suggestion in the serial rate signals at different levels of existing asynchronous digital of regulation corresponding.

Be example with the optical transport network below, describe a specific embodiment of the present invention.In order more clearly to set forth this specific embodiment; Earlier (detailed principle of multiplexing can be with reference to " SDH/SONET synchronizable optical communication infrastructure " at brief account of principle of multiplexing (or multiple connection principle) work of high-order with SDH to SONET; Wang Tingyao etc. write; Tianjin science tech publishing house, publish in April, 1996).In this manual, with the data rate of 2.5Gb/s (SONET:STS-48, SDH:STM-16) the present invention will be described for example is come, to other data rate, the present invention is suitable equally.

Fig. 1 a shows the Multiplexing Unit of the STS-48 of SONET.We come the principle of multiplexing of STS-48 is described with reference to Fig. 1 a.Because the STS-48 that is multiplexed into different approach has identical structure, therefore below with STS-48 by 16 multiplexing forming of STS-3, each STS-3 is multiplexing and become the principle of multiplexing that example is explained STS-48 by 3 STS-1.

Concrete, it will be understood by those skilled in the art that STS-48 can comprise a plurality of Multiplexing Units, wherein, each Multiplexing Unit comprises 48 bytes.In Fig. 1 a, each blockage is represented 1 byte of a STS-1, and is as shown in the figure; Each blockage is used set of number " x; y " Represent, wherein the 1st numeral " x " numbering of expression STS-3, the 2nd numeral " y " the expression numbering of STS-1 in STS-3.As can be seen from Figure 1, each Multiplexing Unit of STS-48 is 48 bytes, respectively from 16 STS-3.The Multiplexing Unit of each STS-3 comprises 3 bytes, respectively from 3 STS-1.For example, the Multiplexing Unit of the 1st STS-3 comprises by " 1,1 ", and 3 bytes of " 1,2 " and " 1,3 " three groups of numerals are respectively from three STS-1.Can the Multiplexing Unit of STS-48 be arranged in the block structure of 3 row, 16 row, shown in Fig. 1 a.

Certainly; The STS-48 signal also can be formed by one or more STS-Nc signal multiplexings; The STS-Nc signal is formed (N is a positive integer) by N STS-1 cascade; Like STS-3c (forming) by 3 STS-1 signal cascades, STS-12c (can form), STS-6c (can form) etc. by 6 STS-1 signal cascades by 12 STS-1 signal cascades.The Multiplexing Unit of STS-48 when Fig. 1 b shows STS-48 and formed by a STS-3c, a STS-12c, a STS-6c and 9 STS-3 signal multiplexings.It will be understood by those skilled in the art that then the multiplexing situation of the multiplexing situation of STS-48 and the STS-48 shown in Fig. 1 is similar at this moment, repeats no more at this if cascade signal STS-Nc is equivalent for what be made up of N STS-1.

In like manner, can STS-Nc be arranged in the block structure of a plurality of 3 row N/3 row, Nc representes the N rank STS signal of cascade here, and for example STS-3c representes the signal that the pure load region cascade by three STS-1 forms together.

Fig. 2 shows the Multiplexing Unit of STM-16 among the SDH.Concrete, it will be understood by those skilled in the art that STM-16 can comprise a plurality of Multiplexing Units, wherein, each Multiplexing Unit comprises 48 bytes.In Fig. 2, STM-16 is by 4 multiplexing forming of AUG-4, and each AUG-4 is by 4 multiplexing forming of AUG-1, and each AUG-1 forms or formed by 3 AU-3 cascades by 3 AU-3 are multiplexing.Each blockage is represented 1 byte of an AU-3 among Fig. 2; Each blockage representes that with set of number " l; m, n " wherein the 1st numeral " l " represented the numbering of AUG-4; The numbering of the 2nd numeral " m " expression AUG-1 in AUG-4, the numbering of the 3rd numeral " n " expression AU-3 in AUG-1.For example, the Multiplexing Unit of the 1st AUG-1 comprises by " 1,1,1 ", and 3 bytes of " 1,1,2 " and " 1,1,3 " three groups of numerals are respectively from three AU-3.Can STM-16 Multiplexing Unit shown in Figure 2 be arranged in the block structure of 3 row, 16 row.

Certainly, the STM-16 signal also can be regarded as by one or more cascade signal AU-3-Yc are multiplexing and forms, and AU-3-Yc representes the signal that formed by Y AU-3 Adjacent Concatenation here, and Y is positive integer.If with the AU-3-Yc equivalence is Y multiplexing the forming of AU-3; Then can AU-3-Yc be arranged in the block structure (attention: of a plurality of 3 row Y/3 row though present SDH standard is not supported the AU-3 Adjacent Concatenation; But in order to make AU-3 Adjacent Concatenation and SONET, AU-4 compatibility, suppose that AU-3 has top cascade system).

Fig. 3 a shows another Multiplexing Unit of STM-16 among the SDH.In Fig. 3 a, STM-16 is by 4 multiplexing forming of AUG-4, and each AUG-4 is by 4 multiplexing forming of AUG-1, and each AUG-1 is made up of an AU-4.Each blockage among Fig. 3 a is represented 1 byte of an AU-4, and each blockage is represented with set of number " r, s, t ".Wherein the 1st numeral " r " represented the numbering of AUG-4; The numbering of the 2nd numeral " s " expression AUG-1 in AUG-4; Because AUG-1 is made up of an AU-4, therefore, establish the 3rd numeral " t " is 0 always.For example, the Multiplexing Unit of the 1st AUG-4 comprise by " 1,1,0 ", 3 bytes of " 1,2,0 " and " 1,3,0 " three groups of numerals are respectively from three AU-4 or AUG-1.STM-16 is during by multiplexing the forming of mode shown in Fig. 3 a, and the Multiplexing Unit of STM-16 is 16 bytes.This byte number with the Multiplexing Unit of Fig. 1 a, STS-48 shown in Figure 2, STM-16 is different; If but we treat as 1 Multiplexing Unit with the Multiplexing Unit of 3 STM-16 shown in Fig. 3 a; Then the byte number with the Multiplexing Unit of Fig. 1 a, STS-48 shown in Figure 2, STM-16 is identical; All can be arranged in the block structure of 3 row, 16 row, shown in Fig. 3 b.

Certainly, STM-16 also can be by multiplexing the forming of one or more cascade signal AU-4-Xc, and AU-4-Xc representes the signal that formed by X AU-4 Adjacent Concatenation here, and X is a positive integer.If with the AU-4-Xc equivalence is that then AU-4-Xc also can regard the block structure of a plurality of 3 row X row as by X multiplexing the forming of AU-4.

Fig. 4 a shows the frame structure sketch map that the SONET basic synchronization is transmitted the pure load (STS-1SPE) of signal; STS-1SPE is made up of 9 row * 87 a row byte; The 1st classifies Higher Order Path Overhead as, and the 30th row and the 59th are classified the fixing row of filling as, and net load is 756 bytes.B3 byte in the Higher Order Path Overhead realizes BIP-8 Bit Interleave checksum coding, is used for the error monitoring of higher order path.The implication of other each field can be with reference to sonet protocol standard (T1.105 (ANSI), GR253 etc.) and SDH consensus standard (G.707 (ITU) etc.) in the Higher Order Path Overhead, because itself and the object of the invention are not directly got in touch, do not give unnecessary details here.

The basic synchronization that Fig. 4 b shows cascade is transmitted the frame structure sketch map of the pure load (STS-NcSPE) of signal; STS-Nc SPE is made up of 9 row * N * 87 row bytes; Wherein the 1st classify Higher Order Path Overhead as, the 2nd row are classified the fixing row of filling as to N/3, and net load is N * 780 byte.

Fig. 5 a shows the frame structure sketch map of high order virtual container VC-3 among the SDH, and VC-3 is made up of 9 row * 87 row bytes.The frame structure of VC-3 is the same with STS-1SPE, and the 1st classifies Higher Order Path Overhead as, and the 30th row and the 59th are classified the fixing row of filling as, and net load is 756 bytes.

The frame structure sketch map of the high order virtual container VC-4-Xc that Fig. 5 b shows in the SDH cascade when X is 1, is the frame structure sketch map of VC-4.VC-4-Xc is made up of 9 row * X * 261 row bytes, and its frame structure is similar to the frame structure of the STS-Nc SPE shown in Fig. 4 b.Wherein, the 1st classifies Higher Order Path Overhead as, then is the fixedly filling row (if X is 1, then not having the fixing row of filling) of (X-1) row.Net load is X * 2340 byte.

For the various frame structures shown in Fig. 4 a, Fig. 4 b, Fig. 5 a and Fig. 5 b,, then fairly simple if every kind of frame structure is carried out the calculating of B3 respectively separately.Transmit leg carries out BIP-8 to all the elements of former frame and calculates, and deposits result of calculation the B3 position of present frame in; The recipient carries out BIP-8 to all the elements of former frame and calculates, and the B3 byte of result of calculation and present frame is compared, if identical, then thinking does not have error code, and like difference, then expression has error code.

If optical transmission device can be supported SDH, also can support SONET, its computational methods to the B3 of different frame structures are normally done different processing to the B3 of every kind of frame structure, select different processing modes through configuration.Because it is multiple that the form of frame structure has, total processing mode can be a lot, and cost is risen, and complicated circuit is used also inconvenient.

In SDH, the pointer of AU-3 and AU-4 has three kinds of bytes, i.e. H1, H2 and H3.H1 and H2 are mainly used in the indication pointer value, and the H3 byte is used for justification.Under the situation of cascade, H1 and H2 are expressed as CI, and its value is " 1001ss1111111111 ", and wherein the s bit is stipulated.For the STS-Nc signal of SONET, during cascade, the pointer value is like this equally.

With 1 AU-4 (VC-4) equivalence is the cascade of 3 AU-3 (VC-3); This equivalent process has theoretical foundation; In the SDH consensus standard, the pointer of AU-4 has only been used the 1st group of H1H2, and the 2nd, 3 group of H1H2 then is fixed as " 1001ss11_11111111 "; This is exactly the cascade indication in fact, i.e. VC-4 equivalence is the cascade of 3 VC-3.Because AU-4 adds the AU pointer by VC-4 and forms, AU-3 adds the AU pointer by VC-3 and forms, and therefore, the VC-4 equivalence is the cascade of 3 VC-3, and AU-4 equivalence just is the cascade of 3 AU-3.

Can find out that from Fig. 4 a and Fig. 5 a the frame structure of STS-1SPE frame structure and VC3 is identical, except last 3 Higher Order Path Overhead definition difference, then identical for the processing of B3.For the frame structure of VC-4-Xc, according to the principle of multiplexing of SDH/SONET, if the cascade that we are 3 VC-3 with 1 VC-4 equivalence, the VC-4-Xc equivalence is the cascade (VC-3-3Xc) of 3X VC-3 so.Because the processing of the B3 of STS-1 and VC-3 is identical, therefore, the B3 of whole SDH/SONET higher order signal is handled the B3 processing that just is reduced to VC-3/STS-1SPE and VC-3-Xc/STS-Nc SPE.

Listed cascade combination example just among Fig. 6, in fact, the cascade combination in the cascade dial gauge can be legal arbitrarily cascade combination, and the multiplexing order of cascade signal also is variable, is not limited to multiplexing order shown in Figure 6.

Optical transmission device is to the higher order virtual container/pure load in the higher order signal of the STM-M/STS-N of input; All as 3M/N independent incoherent " virtual " VC-3/STS-1SPE signal (these VC-3/STS-1SPE signals; It possibly be real VC-3/STS-1SPE signal; Also possibly be virtual VC-3/STS-1SPE signal, also possibly be both mixing, so claim that they are " virtual " VC-3/STS-1SPE signal).These " virtual " VC-3/STS-1SPE signals are made B3 independently calculate, the gained result is referred to as " virtual " B3.Pointer information/frame structure information according to the higher order signal of STM-M/STS-N; Obtain the cascade dial gauge; Then according to the cascade dial gauge; The B3 result of calculation of " virtual " VC-3/STS-1SPE signal of the VC-4/STS-Nc signal that belongs to VC-4 or cascade is respectively merged, to obtain the true B3 of VC-4 or VC-4-Xc/STS-Nc signal.Here the B3 computational methods of " virtual " VC-3/STS-1SPE signal are with the B3 computational methods of VC-3/STS-1SPE signal real in the prior art.

Fig. 7 shows an embodiment according to the present invention is used for the parity information of each data block of calculated data stream in the network equipment of communication network method flow sketch map.

At first, in step S12, respectively said each data block is divided into a plurality of primitives; Then, in step S13, calculate the parity information of said each primitive respectively; At last, in step S16, the parity information that will belong to a plurality of primitives of same data block merges processing, to obtain the parity information of said each data block.The mode that merges includes but not limited to: the said parity information that belongs to a plurality of primitives of same data block is carried out XOR by turn each other, or carry out no-carry binary addition by turn each other, or calculate 1 or 0 number.For example; Data block A is divided into three master data piece A1, A2 and A3, calculates the parity information of three master data pieces respectively, suppose to take the BIP-8 checksum coding; Then obtain parity code C1, C2 and the C3 of three data blocks respectively, be all 8 bits.C1 and C2 are carried out XOR by turn, and the XOR that obtains 8 bits is C12 as a result, then C12 and C3 is carried out XOR by turn, and the C123 as a result that obtains still is 8 bits, and C123 is exactly the BIP-8 parity code of data block A.

Three steps shown in Figure 7 are for realizing the required essential step of the object of the invention.For example; When only comprising a data block in the data flow; When calculating the parity information of this data block, can this data block be divided into a plurality of primitives, calculate the parity information of each primitive then respectively; Parity information with a plurality of primitives merges at last, to obtain the parity information of said data block.

Concrete, according to the difference of application scenarios, can also on step basis shown in Figure 7, increase some different additional steps.When said data flow is made up of a plurality of data blocks, preferably, also can may further comprise the steps before the step S12: from said data flow, obtain said each data block (for for simplicity, not shown this step among Fig. 7).

Fig. 8 shows another embodiment according to the present invention is used for the parity information of each data block of calculated data stream in the network equipment of communication network method flow sketch map.

At first, in step S10, obtain the location indication information in the said data flow, this location indication information is used to locate said each data block.For example; For STS-N signal/STM-M signal; The location indication information is frame structure indication information and explains and next high-order indication information that by Administrative Unit Pointer the high-order indication information promptly is the position indication information of VC-4 signal in frame structure of VC-3 or VC-4 or cascade.

Secondly, in step S11,, from said data flow, obtain said each data block according to said location indication information.For example STS-N signal/STM-M signal according to frame structure indication information/high-order indication information, obtains each STS-1SPE or STS-Nc SPE signal/VC-3, the VC-4-Xc signal of VC-4 or cascade.

Then, in step S12, respectively said each data block is divided into a plurality of primitives.For example, can VC-4 be divided into three " virtual " VC-3, STS-3c SPE is divided into three " virtual " STS-1SPE.Certainly, if certain data block only comprises a primitive, then need not this data block is cut apart.

In step S13, calculate the parity information of said each primitive respectively.

In step S14, generate the map information between said each data block and its a plurality of primitives that comprise according to said location indication information, for for example STS-N signal/STM-M signal, can generate a cascade dial gauge for example shown in Figure 6.

In step S15, confirm to belong to a plurality of primitives of same data block according to said map information.

At last, in step S16, the parity information that will belong to a plurality of primitives of same data block merges processing, to obtain the parity information of said each data block.

Here need to prove that the execution of step S14 also can be before step S12, S13 carry out; Perhaps after step S12 carries out, before step S13 carries out; Perhaps with the execution of step S12 or step S13 simultaneously.

Preferably, said each primitive is big or small identical.The size that those skilled in the art will appreciate that each primitive also can be inequality.

For the SDH Optical Transmission Network OTN, said data flow comprises the SDH synchronous transfer module; Said data block comprises the SDH high order virtual container VC-4-xC of SDH high order virtual container VC-4 and/or Adjacent Concatenation; Said primitive comprises SDH high order virtual container VC-3.For the SONET Optical Transmission Network OTN, said data flow comprises that SONET transmits signal synchronously; Said data block comprises the pure load of SONET basic synchronization of Adjacent Concatenation; Said primitive comprises the pure load of SONET basic synchronization.The said network equipment comprises optical transmission device.Those having ordinary skill in the art will appreciate that; Method of the present invention is not limited to for example SONET or the optical transport network of SDH and the parity information of Bit Interleave; Need calculate the data format of odd-even check information for other communication network, method of the present invention is suitable equally.

For for simplicity; This checkout gear 10 has comprised the sub-device that is comprised in a lot of preferred embodiments; Those skilled in the art are according to the application's instruction; Will be understood that wherein only segmenting device 12, sub-calculation element 13 is the necessary devices of embodiment of the present invention with merging device 15, and other sub-devices are option means.For example; When only comprising a data block in the data flow; When calculating the parity information of this data block, can this data block be divided into a plurality of primitives, calculate the parity information of each primitive then by sub-calculation element 13 respectively by segmenting device 12; Merge by merging the parity information of device 15 more at last, to obtain the parity information of said data block a plurality of primitives.For example; Segmenting device 12 is divided into three master data piece A1, A2 and A3 with data block A; Sub-calculation element 13 calculates the parity information of three master data pieces respectively; Suppose to take the BIP-8 checksum coding, then obtain parity code C1, C2 and the C3 of three data blocks respectively, be all 8 bits.Merge device 15 C1 and C2 are carried out XOR by turn, the XOR that obtains 8 bits is C12 as a result, then C12 and C3 is carried out XOR by turn, and the C123 as a result that obtains still is 8 bits, and C123 is exactly the BIP-8 parity code of data block A.

At first, first deriving means 11 obtains said each data block from said data flow.This can be come to accomplish respectively particularly by two sub-means: second deriving means 111 obtains the location indication information in the said data flow, and this location indication information is used to locate said each data block; The 3rd deriving means 112 obtains said each data block according to said location indication information from said data flow.For example; For STS-N signal/STM-M signal, the location indication information is frame structure indication information/high-order indication information, according to frame structure indication information/high-order indication information; Obtain each STS-1 or STS-Nc signal/VC-3, the VC-4-Xc signal of VC-4 or cascade.

Preferably, said each primitive is big or small identical.The size that those skilled in the art will appreciate that each primitive also can be inequality.

Figure 10 shows the structured flowchart according to an embodiment of the present invention B3 calculation element in SDH or SONET optical transmission device.

This B3 calculation element comprises n " virtual " B3 calculation element, and n is the STM-M that receives of optical transmission device or the passage number of STS-N signal.It should " virtual " B3 calculation element be a concrete implement device of sub-calculation element 13 shown in Figure 9.Also comprise n " virtual " B3 and cascade indication information memory among Figure 10, be used to store the cascade dial gauge that one the 3 capable M (or N/3) that obtains behind " virtual " B3 byte and STM-M (or STS-N) the signal pointer interpreter of each " virtual " VC-3/ " virtual " STS-1SPE is listed as.B3 calculation element shown in Figure 10 comprises that also n " virtual " B3 arrives tag memory, and " virtual " B3 that is used for storing n road signal " virtual " VC3/STS-1SPE signal arrives sign.Here for brevity, segmenting device 12, second deriving means 111 and the 3rd deriving means 112 shown in not shown Fig. 9.Because the STM-M of a plurality of passages or STS-N signal demand are arranged in optical transmission device to be handled; Therefore also comprise a channel scheduling controller in this B3 calculation element, be used for selecting corresponding passage to handle according to the channel instruction that B3 cascade core processor sends.This B3 calculation element also comprises a B3 cascade core processor and n real B3 memory, and wherein B3 cascade core processor is a concrete implement device of merging device 15 shown in Figure 9.

STM-M/STS-N signal to input according to high-order indication information/frame structure indication information, obtains VC-3, the VC-4-Xc signal of VC-4 or cascade/each STS-1 or STS-Nc signal.Then with it all as 3M/N independent incoherent " virtual " VC3/STS-1SPE signal." virtual " B3 calculation element is made B3 independently to these " virtual " VC3/STS-1SPE signals and is calculated (result of calculation claims that for the time being they are " virtual " B3); " virtual " B3, cascade index signal are written in parallel to the simple double port memory that bit wide is 9 bits by the storage organization of 3 row M/ (N/3) row shown in Figure 6 (to be write flatly; Another mouthful read); Simultaneously; With identical storage organization to another bit wide be 1 true double port memory (two mouthfuls all can write, readable, promptly " virtual " B3 shown in Figure 10 arrives tag memory) write " virtual " B3 and arrive sign (supposition " 1 " expression arrives), see Figure 10.When core processor is accomplished the processing to certain " virtual " B3, under the coordination of channel scheduling controller, to the arrival sign zero clearing of this " virtual " B3.Because the processing to all passages is in 1 row (1/9 frame), to accomplish, therefore can not exist " virtual " B3 is arrived the same address set simultaneously of tag memory and the situation of zero clearing.

For the calculating of " virtual " B3,, can it be divided into identical Y (Y is a positive integer) sub-block and calculate if the byte-rate of a SDH/SONET passage is too high.The structure of every sub-block is 3 row M/Y (N/ (3Y)) row, and the Y sub-block is stitched together, and then is 3 row M (N/3) row.Accordingly, real B3 memory also should be divided into the Y sub-block and stores.

B3 cascade core processor periodically scans " virtual " B3 and arrives tag memory, " virtual " B3 and cascade instruction memory, with the cascade indicating status " virtual " B3 is done different processing according to arriving sign, thereby calculates real B3.The scanning sequency of B3 cascade core processor is seen Figure 11.It always begins from last member of 3M/N " virtual " B3, the scanning direction that in these row, reduces to row, and when this was listed as the 1st line scanning completion, the 3rd row that processor will jump to preceding 1 row continued scanning, so repeatedly, scans completion up to the 1st member.If the higher order signal of the STM-M/STS-N of a plurality of passages is arranged, then processor will jump to next passage, and the scanning process above repeating is accomplished up to all passage scannings, and last member who comes back to the 1st passage begins new round scanning.If have only the higher order signal of the STM-M/STS-N of 1 passage, then the 1st member scanned and got back to last member after the completion and begin new round scanning.Each member's scanning takies a core processor clock cycle, and pipeline system is adopted in each member's processing.Here the implication of " member " is meant " virtual " VC3/STS-1SPE signal.

During concrete the realization, be provided with the status register of two bits and the B3 register of one eight bit in the B3 cascade core processor.A bit in the status register is used for storing previous member's cascade state, is expressed as the cascade member like " 1 ", and " 0 " is expressed as non-cascade member; Another bit is used for storing " virtual " B3 arrival state of previous member, arrives (promptly this member's data have all received and finished, and current member arrives), " 0 " expression no show like " 1 " expression.When optical transmission device just starts, can establish last member's cascade state and be " 0 ", " virtual " B3 arrival state of last member is " 1 ".Here previous member's implication is meant when B3 cascade core processor scans current member, and is previous just by scanned member.The B3 register is used for the value of B3 of temporary current calculating.

In scanning during each member, successively carry out B3 calculation process shown in figure 12, B3 output flow process and " virtual " B3 shown in figure 14 shown in figure 13 arrives sign zero clearing flow process.After executing above-mentioned three flow processs, continue the next member of scanning.To carry out detailed description to above-mentioned three flow processs below.

Figure 12 shows real B3 calculation process sketch map in the B3 cascade core processor of an embodiment according to the present invention in optical transmission device.

In step S21, judge whether last member is the cascade member, i.e. if the value of register of indication cascade in the read status register is for " 1 " then think that last member is the cascade member, if for " 0 " then think that last member is not the cascade member.

If last member is not the cascade member; Then in step S22; " virtual " B3 that from memory, reads current member arrives the value of state and cascade state and " virtual " B3; Before the next member of scanning, " virtual " B3 of current member is arrived state and the cascade state is deposited in the status register, " virtual " B3 value of current member is deposited in the B3 register.

If last member is the cascade member; Judge in step S23 then whether current member is the cascade member; Promptly read current member's in the memory cascade indicated value, if be " 1 " then think that current member is the cascade member, if for " 0 " then think that current member is not the cascade member.

If current member is the cascade member; Then the value of two of the hold mode register bits is constant in step S24; From memory, read " virtual " B3 value of current member, and the value in itself and the B3 register carried out the value of gained deposits in the B3 register after the step-by-step xor operation.

If current member is not the cascade member; " virtual " B3 that then in step S25, from memory, reads current member arrives state; " virtual " B3 arrival state and cascade state with current member before the next member of scanning are deposited in the status register; From " virtual " B3 memory, read " virtual " B3 value of current member, and the value in itself and the B3 register carried out the value of gained deposits in the B3 register after the step-by-step xor operation.

Figure 13 shows real B3 output flow process in the B3 cascade core processor of an embodiment according to the present invention in optical transmission device.

At first in step S31, judge according to the value in the status register whether last member is the cascade member.

When last member is not the cascade member; Judge in step S32 then whether current member arrives; Arriving value of statistical indicant through " virtual " B3 that reads the current member in " virtual " B3 arrival tag memory judges; If it is " 1 " that " virtual " B3 of current member arrives value of statistical indicant, think that then current member arrives, the data that promptly belong to current member all receive and finish; If it is " 0 " that " virtual " B3 of current member arrives value of statistical indicant, think that then current member does not also arrive.If current member arrives, judge in step S33 then whether current member is the cascade member.If current member is not the cascade member, then in step S34, export the value of B3 register.If current member does not arrive or current member is the cascade member, then do not export B3, scan next member.

When last member is the cascade member, judge in step S35 then whether last member arrives, its determination methods if last member arrives, judges then whether current member is the cascade member with step S32 in step S33.If current member is not the cascade member, then in step S34, export the value of B3 register.If last member does not arrive or current member is the cascade member, then do not export B3, scan next member.

" virtual " B3 that Figure 14 shows in the B3 cascade core processor of an embodiment according to the present invention in optical transmission device arrives sign zero clearing flow process.

Judge in step S41 at first whether last member is the cascade member.

If last member is the cascade member, judge in step S42 then whether last member arrives, if last member arrives, then in step S43, with " virtual " B3 arrival sign zero clearing of current member.If last member does not arrive, then do not deal with.Scan next member.

If last member is not the cascade member, judge in step S44 then whether current member arrives, if current member arrives, then in step S43, with " virtual " B3 arrival sign zero clearing of current member.If current member does not arrive, then do not deal with, scan next member.

In fact, last member's arrival state is only just useful when last member is cascade.What its was really indicated is last virtual member's (from the data flow of SDH/SONET is last, and it is first from scanning sequency) of a cascade piece arrival state.That is to say that when last virtual member of cascade piece arrived, we just thought that all cascade members arrive, and no matter other cascade member's arrival state how in this cascade piece.When optical transmission device had just been started working, first B3 that calculates possibly be wrong, but the correctness of this B3 that calculates after not influencing.

Can find out according to the handling process among Figure 12 to Figure 14; Because Figure 13 and true B3 output flow process and " virtual " B3 arrival sign shown in Figure 14 are removed the cascade status indication information and arrival status indication information that need use the last member in the status register in the flow process; Therefore; In scanning during each member, the renewal of status register need execution after Figure 13 and flow performing shown in Figure 14 are intact among Figure 12.Those skilled in the art will appreciate that when concrete sequence circuit is realized carry out under triggering because the value of register changes at clock, above-mentioned three flow processs can be moved simultaneously.

B3 cascade core processor will calculate good real B3 and deposit simple double port memory in, so that the verification of B3 or insert module (not shown among Figure 10) read when needed.The storage organization of the storage organization of this memory and " virtual " B3 memory is identical; Difference is to have only the value that cascade is designated as those members of 0 memory cell to be only real B3; The value that cascade is designated as those members of 1 memory cell is invalid, and the subsequent treatment module should be ignored these members' value.

The memory that " virtual " B3 of storage shown in Figure 10 arrives sign is true double port memory, the structured flowchart of the B3 calculation element that Figure 15 shows memory that Fig. 7 storage " virtual " B3 arrives sign when being simple double port memory.Because " virtual " B3 arrives sign and also can be stored in the simple double port memory, it is multiplexing with the channel scheduling controller that write mouth this moment, possibly carry out write operation simultaneously.Therefore; Need to increase a simple double port memory and come the stores processor complement mark; Write mouthful idle and the tag memory of finishing dealing with is write when mouthful idle when " virtual " B3 arrives tag memory; Can arrive sign according to state zero clearing " virtual " B3 of stores processor complement mark memory by the channel scheduling controller, the sign of finishing dealing with of zero clearing simultaneously.

The treatable largest passages number of B3 calculation element is relevant with the core processor clock in the optical transmission device.If the core processor clock frequency is the byte-rate of SDH/SONET; Then in theory the treatable port number of the present invention be 90 (because the B3 that former frame is calculated will arrive the 2nd row ability of next frame with verification or insertion; The time interval that 1 row is arranged during this); Add pipelining delay and pointer negative justification, the multipotency of the present invention is handled 88 passages.If the core processor clock frequency is Z/one of the byte-rate of SDH/SONET, then Figure 10 or the treatable largest passages number of B3 calculation element shown in Figure 15 are (90/Z)-2.If Z is not a positive integer, then treatable largest passages number deducts 2 again after rounding under (90/Z).

More than specific embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, those skilled in the art can make various distortion or modification within the scope of the appended claims.