CN101546602B - Nonvolatile memory device using variable resistance element - Google Patents

The invention relates to a nonvolatile memory device which comprises a plurality of memory groups and a plurality of global unit lines, wherein each of the memory groups comprises a plurality of nonvolatile memory units, each of the nonvolatile memory units comprises a variable resistance element, each of the variable resistance elements is provided with resistance which varies according to stored data, each of the global unit lines is shared by a plurality of memory groups. A plurality of major lines are arranged corresponding to one of the plurality of memory groups.

Use the non-volatile memory devices of variable resistor element

Technical field

Example embodiment of the present invention relates to the non-volatile memory devices that uses variable resistor element.

Background technology

Use the Nonvolatile semiconductor memory device of resistance material to be divided into NOR flash memory device, nand flash memory equipment, phase change random access memory devices (PRAM) equipment etc.But, dynamic RAM (DRAM) equipment or flash memory device use electric charge to write data, phase change random access memory devices (PRAM) uses the phase change material stores data of for example sulphur alloy, due to cooling the caused temperature change after heating, described phase-change material enters crystalline state or amorphous state (amorphous state).

In other words, because the resistance of the phase-change material of majority in crystalline state is low, but not the resistance of crystalline phase-change material is high, and therefore, crystalline state is called as sets state or " 0 " state, and amorphous state is called reset state or one state.PRAM equipment is applied to the Joule heat that phase-change material produces and writes data setting pulse or reset pulse by using.At length, by using reset pulse that the phase-change material of PRAM unit is heated to above to its fusing point, also quick cooling phase change materials so that the state of phase-change material becomes amorphous state, or by phase-change material being heated to lower than its crystallization point, maintain the temperature schedule time amount that obtains cooling phase change materials so that the state of phase-change material becomes crystalline state, write data to PRAM unit.

Fig. 1 and Fig. 2 are the circuit diagrams of the arrangement for traditional non-volatile memory devices is described.For convenience of description, Fig. 1 and Fig. 2 illustrate that traditional non-volatile memory devices comprises 8 memory set, but it also can comprise the memory set of varying number.

With reference to figure 1, traditional non-volatile memory devices comprise multiple memory set 10_1 to 10_8, overall column select circuit 30_1 to 30_8, overall sensor amplifier (amp) circuit 40_1 is to 40_8 and/or global write drive circuit 50_1 to 50_8.Have more high power capacity and more the non-volatile memory devices of high density of integration can realize with hierarchical bit line structure and classification word line structure, in described hierarchical bit line structure, multiple local bitline are connected to each global bit line, in described classification word line structure, multiple sub-word line couplings are to each main word line.As shown in Figure 1, global bit line GBL corresponding to multiple memory set 10_1 to each arrangement the in 10_8.Main word line direction is arranged to 10_8 corresponding to multiple memory set 10_1.

When global bit line GBL is corresponding to multiple memory set 10_1 during to each arrangement in 10_8, traditional non-volatile memory devices has core architecture as shown in Figure 2.With reference to figure 2, multiple main word line demoder 20_1 arrange to 10_8 corresponding to multiple memory set 10_1 to 12_8 to 20_8 and multiple redundant memory cell array 12_1.

During synchronizing pulse read operation, according to the quantity of just prefetched word, traditional non-volatile memory devices with the core architecture shown in Fig. 2 needs the phenomenal growth of the quantity of the sensor amplifier in overall sense amplifier circuit 401 to 408.For example, if for example, be 4 from the quantity of the word that reads in a memory set (10_1) and look ahead, for example, in an overall sense amplifier circuit (40_1), the quantity of required sensor amplifier is 64 (1 word (16) × 4) so.Like this, in 40_8, need 512 (64 × 8) individual sensor amplifier at 8 overall sense amplifier circuit 40_1.If look ahead 8 words from a memory set, need 1024 sensor amplifiers.If look ahead 16 words from a memory set, need 2048 sensor amplifiers.That is to say, along with the quantity of the word that will look ahead increases, the corresponding increase of area of core architecture.

During test operation, be also difficult to for example, write a large amount of data bit in a memory set (101).The resetting current that suppose in the time that reseting data is write to a Nonvolatile memery unit, flows through a Nonvolatile memery unit is about 1mA, 16 bit data write store groups 101 may be needed to the resetting current of about 16mA at every turn.That is to say, flow into memory set 10_1 (narrow space) owing to crossing high level resetting current, therefore, be difficult to write mass data position at every turn.Like this, because should write low volume data position during test operation at every turn, so need a large amount of test durations.

Further, because arrange multiple main word line demoder 20_1 to 20_8, so increased the area of core architecture corresponding to multiple memory set 10_1 to 10_8.Because memory set 10_1 shares same word line WL to Nonvolatile memery unit and redundant memory cell array 12_1 in 10_8 to the redundant memory unit in 12_8, so arrange multiple redundant memory cell array 12_1 to 12_8 corresponding to multiple memory set 10_1 to 10_8, so, further increased the area of core architecture.

Summary of the invention

The present invention relates to a kind of non-volatile memory devices and constructive method thereof.

This non-volatile memory devices comprises multiple memory set, and each memory set comprises multiple Nonvolatile memery units.Each unit comprises the variable resistor element with the resistance changing according to the data of storage.Comprise multiple global bit line, and each global bit line is shared by multiple memory set.Arrange multiple main word lines corresponding to one in multiple memory set.

Accompanying drawing explanation

Describe example embodiment in detail by reference to accompanying drawing, above-mentioned and other feature and advantage of the present invention will be more obvious, in accompanying drawing:

Fig. 1 and Fig. 2 are the circuit diagrams of the arrangement for traditional non-volatile memory devices is described;

Fig. 3 is for illustrating according to the block scheme of the non-volatile memory devices of the embodiment of the present invention;

Fig. 4 is according to the block scheme of the non-volatile memory devices of the embodiment of the present invention;

Fig. 5 is the concept circuit diagram of the non-volatile memory devices for being described in more detail Fig. 4;

Fig. 6 is for the concept circuit diagram according to the read-write operation of the non-volatile memory devices of the embodiment of the present invention is described;

Fig. 7 A-7D is the exemplary plot of local column select circuit; And

Fig. 8 A and Fig. 8 B are according to the exemplary cross-sectional of the non-volatile memory devices of the embodiment of the present invention.

Embodiment

By reference to illustrating of following example embodiment and accompanying drawing, can be easier to understand advantages and features of the invention and its implementation.But the present invention can multi-formly realize, and should only not be interpreted as being limited to embodiment described herein.But, these embodiment are provided, it will be complete and thoroughly making the disclosure, and will pass on idea of the present invention completely to those skilled in the art, the present invention simultaneously will only be limited by claim.Spread all over instructions, identical label represents identical element.

To understand, when certain element or layer are while being called as " being connected to " or " being coupled to " another element, it can directly connect or be coupled to another element or layer, or can have intermediary element.On the contrary, in the time that certain element is called as " being directly connected to " or " being directly coupled to " another element, there is not intermediary element.Spread all over identical label in full and represent identical element.As used herein, term "and/or" comprises any and all combinations of one or more projects of listing of being associated.

Although in different piece below or based on an embodiment meet embodiment illustrated example embodiment respectively, unless indicate, each describe not uncorrelated mutually.They are variant each other whole or in part, and description be sometimes another description in detail or supplementary form.In following example embodiment, even when for element indication optional network specific digit symbol (amount, numerical value, quantity, scope etc.), be not also restricted to indicated optional network specific digit symbol, limit unless otherwise or in theory this optional network specific digit symbol; Be to be understood that it can be greater than or less than specific numeric character.In the following embodiments, element (comprising element step) is not always necessary, thinks except as otherwise noted or clearly necessary.Similarly, in the time of the shape of indicator elment in the following embodiments or position, think and also comprise basic equating or similarly shape or position with it, think really not so except as otherwise noted or clearly.This keeps setting up to above-mentioned numeric character and scope.In institute's drawings attached of examples shown embodiment, there is the designated identical reference number of element of identical function; And the explanation of these elements no longer repeats.

To understand, although term first, second and other can be used for describing different elements at this, these elements should not limited by these terms.These terms are only for distinguishing an element and another element.Like this, in the situation that instructing without prejudice to the present invention, following the first element can be described as the second element.

As " ... under ", " ... below ", " lower than ", " in the above ", the term of space correlation " above " etc. can be used to convenient description at this, to describe as shown in drawings the other element of an element or feature and (multiple) or the relation of (multiple) feature.To understand, the term of space correlation be intended to comprise the direction in figure use or operation in the different directions of equipment.For example, the element that if the equipment in figure is inverted, is described as " below other elements or feature " or " under other elements or feature " by towards other elements or feature " above ".Like this, exemplary term " ... can be included in above and both direction below below ".Equipment can separately have towards (90-degree rotation or in other directions), and the term of space correlation as used herein is correspondingly explained.

After this, will exemplary embodiment of the present invention be described about PRAM.But those skilled in the art will be apparent, the present invention also can be applicable to use the non-volatile semiconductor memory device of resistance material, as phase transformation RAM (PRAM), and magnetic RAM (MRAM) etc.

Fig. 3 is for illustrating according to the block scheme of the non-volatile memory devices of the embodiment of the present invention.For convenience of description, Fig. 3 illustrates the non-volatile memory devices with 8 memory set, but it also can comprise the memory set of varying number.

Although do not show in Fig. 3, but memory set 110_1 comprises multiple Nonvolatile memery units to 110_8 each, each unit comprises variable resistor element and access devices, variable resistor element has according to the resistance of the data variation of storage, and the electric current of variable resistor element is flow through in access devices control.Variable resistor element can be made up of the material of various kinds, as binary (2 elements), compound (for example, GaSb, InSb or InSe), ternary (3 elements) compound (for example, GeSbTe, GaSeTe, InSbTe, SnSb ₂te ₄or InSbGe), or quaternary (4 elements) compound (for example, AgInSbTe, (GeSn) SbTe, GeSb (SeTe) or Te ₈₁ge ₁₅sb ₂s ₂).The most frequently used material is GeSbTe.Access devices can comprise diode, field effect (FET) transistor, npn bipolar transistor, PNP bipolar transistor or other semiconductor equipments.

More high power capacity and more the non-volatile memory devices of high density of integration can use hierarchical bit line structure and classification word line structure to realize, in described hierarchical bit line structure, multiple local bitline are connected to each global bit line, in described classification word line structure, multiple sub-word line couplings are to each main word line.With reference to figure 3, multiple global bit line GBL0 arrange to 110_8 corresponding to multiple memory set 110_1 to each in GBLn+1.Each in multiple main word lines provides to one of 110_8 corresponding to multiple memory set 110_1.

Fig. 4 is according to the block scheme of the non-volatile memory devices of the embodiment of the present invention.

With reference to figure 4, each global bit line comprises to be write global bit line (WGBL) and reads global bit line (RGBL), write global bit line (WGBL) for to multiple memory set 110_1 to 110_8 data writing, read global bit line (RGBL) for from multiple memory set 110_1 to 110_8 reading out data.The non-volatile memory devices with this configuration can easily be carried out read operation (for example,, when writing fashionable reading) during write operation.

In non-volatile memory devices according to the present invention, multiple memory set 110_1 are divided into multiple sub-block S0 to S7 to the each of 110_8.Overall situation sense amplifier circuit (for example 140 in Fig. 3) comprises and corresponds respectively to multiple sub-block S0 to the first to the 8th sense amplifier circuit 140_1 of S7 to 140_8.Global write drive circuit (for example 150 in Fig. 3) comprise correspond respectively to multiple sub-block S0 to S7 first to the write driver circuit 150_1 of eight convergent points office to 150_8.Overall situation column select circuit (for example 130 in Fig. 3) comprise correspond respectively to multiple sub-block S0 to S7 first to the column select circuit 130_1 of eight convergent points office to 130_8.

Fig. 5 is the concept circuit diagram of the non-volatile memory devices for being described in more detail Fig. 4.

With reference to figure 5, non-volatile memory devices is included in use during write operation multiple and independently writes multiple global bit line RGBL0 that independently read that global bit line WGBL0 uses to WGBLn and during read operation to RGBLn.

In response to writing local array selecting signal WLY0 to WLYn, local column select circuit 155 is optionally coupled multiple local bitline LBL0 to LBLn and writes global bit line WGBL0 to WGBLn accordingly.In response to reading local array selecting signal RLY0 to RLYn, local column select circuit 155 is optionally coupled to multiple local bitline LBL0 to LBLn and reads global bit line RGBL0 to RGBLn accordingly.The exemplary configuration of local column select circuit 155 will describe in detail to 7D with reference to figure 7A below.

Fig. 6 is for the concept circuit diagram according to the read-write operation of the non-volatile memory devices of the embodiment of the present invention is described.

Further, in order to write n × m group data (n and m are greater than 1 integer), can during test operation, in n sub-block, write m group data according to the non-volatile memory devices of the present embodiment simultaneously.

For example, as shown in Figure 6, for example, (for example 8 × 2) group data can write two groups of data during test operation in 8 sub-blocks simultaneously in order writing 16 in a memory set (110_1).In the normal operation period, two groups of data for example can be repeated to write for 8 times, in a sub-block (S0).That is to say, because apply reset current by tester, so can write 16 groups of data during test operation simultaneously.Because to the restriction of current driving ability, so non-volatile memory devices repeats data writing in a sub-block in the normal operation period, but not while data writing in to multiple sub-block S0 to S7.But in the normal operation period, the non-volatile memory devices with enough current driving abilities can be to while data writing in multiple sub-blocks.Because setting/resetting current can flow into multiple sub-block S0 to S7 (, in wide region), so can write 16 groups of data at test period at every turn.That is to say, because test period can write mass data simultaneously, so the test duration can significantly reduce.

Fig. 7 A-7D is the exemplary circuit diagram of local column select circuit 155.

With reference to figure 7A-7D, the local column select circuit 155 of Fig. 5 comprises that (multiple) write local column select circuit (170 in the 170_1 in Fig. 7 A or Fig. 7 B and 170_2 or Fig. 7 C or Fig. 7 D) and (multiple) read local column select circuit (160 in the 160_1 in Fig. 7 A or Fig. 7 B and 160_2 or Fig. 7 C or Fig. 7 D).During write operation, in response to writing local array selecting signal WLY0 to WLY7, (multiple) write local column select circuit coupling local bitline LBL0 to LBL7 and write global bit line WGBL.During read operation, in response to reading the local signal RLY0 that selects to RLY7, (multiple) read local column select circuit coupling local bitline LBL0 to LBL7 and read global bit line RGBL.Memory cell array comprises and is arranged in sub-block (S0 of Fig. 4 is to S7) and is coupled to the multiple Nonvolatile memery units of local bitline LBL0 to LBL7.

As shown in the embodiment of Fig. 7 A, write local column select circuit 170_1 and 170_2 and be arranged in the either side of cell array.Each multiple selection transistors that are included in quantitatively corresponding to the local bitline of cell array of writing local column select circuit 170_1 and 170_2.Each selection transistor is connected writes global bit line WGBL and local bitline LBL0 between separately one in LBL7; And receive and write local array selecting signal WLY0 to separately one in WLY7.Read the either side that local column select circuit 160_1 and 160_2 are also arranged in cell array.But, reads local column select circuit 1601 and only comprise the selection transistor corresponding to the local bitline of even-numbered, and read bit column select circuit 1602 comprises the selection transistor corresponding to the local bitline of odd-numbered.Especially, the selection transistor of reading local column select circuit 1601 is connected between one that reads in global bit line RGBL and local bitline LBL0, LBL2, LBL4 and LBL6 separately; And receive respectively and read local signal RLY0, RLY2, RLY4 and the RLY6 of selecting at its grid.Read local column select circuit 1602 and comprise selection transistor, this selection transistor is connected to be read between global bit line RGBL and local bitline LBL1, LBL3, LBL5 and LBL7, and receives and read local signal RLY1, RLY3, RLY5 and the RLY7 of selecting at its grid.

In the embodiment of Fig. 7 B, write local column select circuit 170_1 and 170_2 and be arranged in the either side of cell array.This writes the each selection transistor comprising for the half local bitline in cell array in local column select circuit.Especially, write local column select circuit 170_1 and comprise selection transistor, this selection transistor is connected to be write between global bit line WGBL and local bitline LBL0, LBL2, LBL4 and LBL6; And these select transistor to receive respectively and write local signal WLY0, WLY2, WLY4 and the WLY6 of selecting at its grid.Write local column select circuit 170_2 and comprise selection transistor, this selection transistor is connected to be write between global bit line WGBL and local bitline LBL1, LBL3, LBL5 and LBL7; And these select transistor to receive respectively and write local signal WLY1, WLY3, WLY5 and the WLY7 of selecting at its grid.In this embodiment, read local column select circuit 160_1 and 160_2 and be arranged in the either side of cell array.Read local column select circuit 160_1 and 160_2 and all comprise the selection transistor being associated with each local bitline.Especially, these are read local column select circuit and comprise selection transistor, and this selection transistor is connected reads global bit line RGBL and local bitline LBL0 between separately one in LBL7.Selecting transistor also to receive respectively each part of reading at its grid selects signal RLY0 to RLY7.

Write local column select circuit and read local column select circuit and can there are various other configurations that are different from illustrated configuration in Fig. 7 A-7D.

Fig. 8 A and Fig. 8 B are according to the exemplary cross-sectional of the non-volatile memory devices of the embodiment of the present invention.

Further, write global bit line WGBL and read global bit line RGBL and be optionally coupled with multiple local bitline LBL (8 LBL in Fig. 8 A).Especially, Fig. 8 A illustrates and writes global bit line WGBL and read global bit line RGBL the example that is positioned at same layer (level).In addition,, although do not show in Fig. 8 A, main word line MWL and sub-word line SWL are optionally coupled.

Fig. 8 B represents the example of non-volatile memory devices, in this non-volatile memory devices, writes global bit line WGBL0 and WGBL1 and reads global bit line RGBL0 and RGBL1 and be positioned at different layers.With reference to figure 8B, main word line MWL and sub-word line SWL form on insulation course 160.Insulation course 170 ' forms on main word line MWL and sub-word line SWL.First reading global bit line and second and read global bit line RGBL0 and RGBL1 and form insulation course 170 ' is upper separately, and another insulation course 180 ' is read global bit line and second first and is read to form on global bit line RBGL1 and RGBL2.Writing global bit line WGBL0 and WGBL1 can reading on insulation course 180 ' form on global bit line RGBL0 and RGBL1.Although do not show in Fig. 8 B, but read global bit line RGBL0 and write global bit line WGBL0 to be optionally coupled with multiple local bitline LBL (4, left side LBL in Fig. 8 B), and read global bit line RGBL1 and write global bit line WGBL1 to be optionally coupled with remaining multiple local bitline LBL (4, the right LBL in Fig. 8 B).Read global bit line RGBL0 and RGBL1 and write global bit line WGBL0 and WGBL1 can various other modes and multiple local bitline LBL coupling.In addition,, although Fig. 8 B shows main word line MWL and sub-word line SWL forms on same layer, they can otherwise be arranged.For example, main word line MWL can form writing on global bit line WGBL0 and WGBL1.

As mentioned above, the invention provides a kind of big or small non-volatile memory devices of the core architecture with reduction.

Although specifically illustrate and described the present invention with reference to exemplary embodiment of the present invention, it will be appreciated by the skilled addressee that the various variations that can carry out in form and details, and do not depart from the spirit and scope of the present invention as defined in claim.