CN101632156B - Printable semiconductor structures and related methods of making and assembling - Google Patents

本发明提供了一种高产率的用于加工、转移以及组装具有所选择的物理尺寸、形状、成分以及空间取向的高品质可印刷半导体元件的途径。本发明的成分以及方法提供了将微小尺寸和/或纳米尺寸的半导体结构阵列高精度配准转移和集成到基片上，所述基片包括大面积基片和/或柔性基片。此外，本发明提供了从诸如体硅晶片的低成本体材料以及智能材料处理策略来制备可印刷半导体元件的方法，该智能材料处理策略实现了一种用于制备宽范围功能半导体设备的多用途的、以及具有商业吸引力的基于印刷的制造平台。

The present invention provides a high yield approach for processing, transferring and assembling high quality printable semiconductor elements of selected physical size, shape, composition and spatial orientation. The compositions and methods of the present invention provide for high-precision registration transfer and integration of arrays of micro-sized and/or nano-sized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. Furthermore, the present invention provides methods for fabricating printable semiconductor elements from low-cost bulk materials such as bulk silicon wafers and smart material processing strategies that enable a versatile approach for fabricating semiconductor devices with a wide range of functions. , and a commercially attractive print-based manufacturing platform.

Printable semiconductor structures and relevant the manufacturing and assemble method

The intersection of related application is quoted

The application requires in the U.S. Patent application No.11/145 of submission on June 2nd, 2005; 542, the U.S. Patent application No.11/145 that submitted on June 2nd, 2005; The priority of the international pct application No.PCT/US05/19354 that on June 2nd, 574 and 2005 submitted to; By reference mode here is not to exceed with disclosed content is inconsistent here, with fitting into this paper in all these applications.

Background technology

Since the all-polymer transistor of demonstration printing first in 1994, those potential newtype electronic systems that on plastic substrate, comprise the electronic equipment that flexibility is integrated have caused people's extensive concern.[Gamier, F., Hajlaoui, R., Yassar, A.and Srivastava, P., Science, the 265th volume, 1684-1686 page or leaf].Recently, basic research has been conceived to develop the new solution-processible material that is used for semiconductor, insulator and semiconductor element and has been used for the flexiplast electronic equipment.Yet; The progress in flexible electronic devices field is not only to be promoted by the exploitation of new solution-processible material, but also the high-resolution that receives shape, high-efficiency appliance, the apparatus assembly processing method of new apparatus assembly and can be applicable to plastic substrate becomes the promotion of diagram technology.Can expect that this type material, equipment structure and manufacturing approach will be played the part of a substantial role in the flexible integrated electronics of the newtype that emerges rapidly, system and circuit.

The interest of flexible electronic devices is mainly resulted from several significant advantage that this technology provides.At first, the mechanical robustness of this plastic substrate material damage and/or the Electronic Performance that make electronic equipment be not easy to receive to cause because of mechanical pressure reduces.The second, it is integrated that the inherent toughness of these substrate materials makes them to come with multiple shape, with this a large amount of useful device structures is provided, and utilized the conventional silicon base electronic equipment of fragility not accomplish.For example, can reckon with that flexible flexible electronic devices makes the new equipment that can make such as electronic paper, wearable computer and large tracts of land high resolution display, these equipment are to be difficult for realizing under existing silicon-based technologies.At last, the combination of solution-processible assembly material and plastic substrate make through these can with low cost on big chip area, produce electronic equipment continuously, at a high speed, printing technology makes.

Yet, show that there are a lot of arduous challenge in the design and the manufacturing of the flexible electronic devices of good Electronic Performance.Developed to such an extent that well manufacturing approach and most of plastic material of conventional silicon-based electronics is incompatible at first.For example, traditional high-quality inorganic semiconductor assembly such as monocrystalline silicon or Ge semiconductor, generally is to handle through growing film under fusing that significantly surpasses most of plastic substrates or decomposition temperature (＞1000 degrees centigrade).In addition, most inorganic semiconductors are insoluble in essence in conventional soln, and this allows processing and transmission based on solution.Second; Although a lot of amorphous silicons, organic and inorganic semiconductor organic or that mix can be brought in the plastic substrate compatiblely; And can under low relatively temperature, handle, but these materials do not have the characteristic electron that the integrated electronics with good Electronic Performance can be provided.For example, the field-effect mobility that the thin-film transistor of being processed by these materials with semiconductor element is showed is than low about three magnitudes of equipment of remaining based single crystal silicon.Because these restrictions, flexible electronic devices is only limited to those at present not to be needed in the high performance application-specific, such as the switch element of the active matrix flat-panel screens that is used for having non-emission pixel and be used for light-emitting diode.

Recently, be formed at superset and obtained progress aspect the Electronic Performance of the electronic equipment on the plastic substrate, so that its application extension is to the electronic application scope of a broad.For example; Occurred several kinds with new thin-film transistor (TFT) design compatible, and these new thin-film transistor (TFT) design expression obvious high equipment performance characteristic of thin-film transistor of going out than have amorphous silicon, the organic or organic and inorganic semiconductor element that mixes to the processing on the plastic substrate material.A kind of more high performance flexible electronic devices is based on through amorphous silicon membrane being carried out the polysilicon membrane semiconductor element that pulsed laser anneal is made.Though this flexible electronic devices provides the equipment Electronic Performance characteristic that strengthens, and utilizes the annealing of pulse laser to limit the ease and the flexibility of this device fabrication, thereby has significantly increased cost.Another kind of good newtype more high-performance flexible electronic equipment is those nanometer materials with solution-processible, such as nano wire, nano belt, nano particle and CNT as the active functional unit in many grand electronics and the microelectronic device.

Assessment thinks that but monocrystal nanowire or the nano belt of using dispersion can be used as a kind of feasible pattern that the print electronic devices of showing the equipment performance characteristic that strengthens is provided on plastic substrate.People such as Duan have described the monocrystalline silicon nano line of a plurality of selections orientation or CdS nano belt thin-film transistor design [Duan, X., Niu, the C as channel semiconductor; Sahl, V., Chen, J.; Parce, J., Empedocles, S.and Goldman; J., Nature, the 425th volume, 274-278 page or leaf].The author has reported a kind of according to the compatible manufacturing process of the solution-treated on its said and plastic substrate; Wherein, Thickness is less than or the monocrystalline silicon nano line or the CdS nano belt that equal 150 nanometers is distributed in the solution; And use conductance it to be assembled on the substrate surface, to be created in the semiconductor element on the thin-film transistor to alignment method.The light micrograph that is provided by the author is illustrated in the nano wire or the nano belt of arranging individual layer to 1000 nanometers with about 500 nanometers of substantially parallel direction and interval in the disclosed manufacturing process.Although this author's report has higher relatively intrinsic field-effect mobility (≈ 119cm for independent nano wire or nano belt ²V ^-1s ^-1), but confirm intrinsic field-effect mobility value " approximately little two magnitudes " [Mitzi, D.B, Kosbar, the L.L. of entire equipment field-effect mobility recently than people such as Duan report; Murray, C.E., Copel, M.Afzali; A., Nature, the 428th volume, 299-303 page or leaf].This equipment field-effect mobility is than the low several magnitudes of conventional monocrystalline inorganic thin-film transistors, is likely because practice challenge that collimation, intensive encapsulation and dispersing nanowires when utilizing people's disclosed method such as Duan and equipment structure or nanometer band contact causes.

Use nanocrystal solution as the precursor (precursor) of polycrystalline inorganic semiconductor film but explored be a kind of feasible method that the print electronic devices of the higher equipment performance characteristic of displaying can be provided on plastic substrate.People such as Ridley disclose a kind of solution-treated manufacturing approach, wherein under the compatible temperature of plastics, handle the cadmium selenide nano-crystal solution with about 2 nano-scales, think that field-effect transistor provides semiconductor element.[Ridley, B.A., Nivi, B.andJacobson, J.M., Science, the 286th volume, 746-749 page or leaf (1999)].The author has reported a kind of method, and wherein the low temperature grain growth in the cadmium selenide nano-crystal solution provides and included the brilliant monocrystalline area of hundreds of nanometers.Although people such as Ridley reported improved electrology characteristic can with the apparatus in comparison with organic semiconductor device, equipment mobility (the ≈ 1cm that obtains by these technology ²V ^-1s ^-1) hang down several magnitudes than the equipment field-effect mobility of conventional monocrystalline inorganic thin-film transistors.Be likely by the restriction of people's such as Ridley equipment structure and the field efficient mobility that manufacturing approach obtained and cause by electrically contacting of between each nano particle, setting up.Particularly, organic end end group is used for the brilliant solution of stabilized nanoscale and stops cohesion, possibly hinder that between adjacent nano particle, to set up for high equipment field-effect mobility is provided be necessary excellent electric contact.

Although people such as people such as Duan and Ridley provide the method that is used on plastic substrate, making thin-film transistor, described equipment is constructed the transistor that has adopted the apparatus assembly that comprises the mechanical rigid such as electrode, semiconductor and/or insulator.The plastic substrate that selection has a good mechanical properties can provide the electronic equipment that can operate in direction variable or distortion.Yet, can reckon with that this athletic meeting produces mechanical stress on each rigid crystals tube apparatus assembly.This mechanical stress possibly cause the damage to each assembly, for example breaks, and electrically contacting between the apparatus assembly failed or destruction.

The United States Patent (USP) of all submitting to 11/145 on June 2nd, 2005; 574 and 11/145,542 discloses a kind of high yield manufacturing platform of printable semiconductor elements that uses to prepare electronic equipment, optoelectronic device and other function electronic installations through multipurpose, low cost and large-area printing technology.Disclosed method and composition provide use the heat switching of well laying accuracy, registration and pattern reproductions degree that is provided on the big area of base to touch to print and/or the solution printing technology come to micro-dimension and/or nano-scale semiconductor structure shift, assembling and/or integrated.Disclosed method provides important processing advantage, makes to use conventional high-temperature processing method making the integrated of high-quality semi-conducting material on the substrate through following printing technology: this printing technology can with the certain limit that comprises flexible plastic substrate in the low relatively temperature of useful substrate material compatibility under (＜about 400 degrees centigrade) independently carry out.The flexible thin-film transistor that utilizes the printable semiconductor material manufacture is when in crooked and the good electrical performance characteristics of non-curved shape displaying of following time, such as greater than 300cm ²V ^-1s ^-1The equipment field-effect mobility and greater than 10 ³The ON/OFF ratio.

Be appreciated that the commercial appeal that with low-cost, as to arise from the high-quality printable semiconductor elements of body material manufacture method raising is used to produce the printing technology of large area flexible electronics and optoelectronic device and equipment array from above.And, make the printable semiconductor composition that can carry out highly control and also will improve the applicability that these methods are used to make the function device of wide region based on the assemble method of printing to physical size, spatial orientation and the registration that is printed onto on-chip semiconductor element.

Summary of the invention

The invention provides a kind of high yield approach that is used to process, shift and assemble high-quality printable semiconductor elements with selected physical size, shape, composition and spatial orientation.Composition of the present invention and method provide the accurate registration of the array height of microsize and/or nano-scale semiconductor structure are shifted and is integrated on the substrate that is included in large area substrates and/or flexible substrate.In addition; The invention provides the method for preparing printable semiconductor elements with low-cost body (bulk) material and intellectual material processing policy such as body silicon wafer (bulksiliconwafer), this intellectual material processing policy has been realized a kind of multipurpose that is used to prepare wide region function semiconductor equipment, has been had the manufacturing platform based on printing of commercial appeal.The manufacturing of this semiconductor, transfer and integrated platform provide a plurality of advantages, and these advantages comprise the height control of geometry, space orientation and tissue, doped level and material purity to printable semiconductor structures.

The inventive method and composition make it possible to carry out the complicated integrated electronics or the manufacturing of optoelectronic device or equipment array scope; Comprise large tracts of land, flexibility, the grand electronic equipment of high-performance, these electronic equipments are showed the performance characteristic that can intend with the semi-conductive apparatus in comparison of those based single crystals that utilize conventional high-temperature processing method to make.Printable semiconductor elements is integrated, location, tissue, transfer, one-tenth figure and/or be integrated on the substrate or interior the present invention makes composition and associated method and in fact can be used to make any structure that comprises one or more semiconductor element.Yet these methods are for making complicated integrated electronics or optoelectronic device or equipment array; Particularly useful such as diode array, light-emitting diode, solar cell and transistor (for example, thin-film transistor (TFT), metal-semiconductor field effect transistor (MESFET) TET and bipolar transistor).Composition of the present invention and associated method is for being used for the integrated circuit of manufacturing system level; Such as NOA and NAND gate and complementary logic circuit also is useful; Wherein the printable semiconductor elements edge one abundant spatial orientation that limits is printed on the substrate and is interconnected, to form required circuit design.

On the one hand, the invention provides the processing method of using body silicon wafer parent material, these materials are repeated to handle the printable semiconductor elements with physical size, shape and the spatial orientation that provides having of high yield accurately to choose.In the embodiment of the present invention aspect this, provide one and had the silicon wafer that (111) are orientated and have an outer surface.In having the embodiment of commercial appeal, this wafer is low-cost, body (111) silicon wafer.The silicon wafer outer surface produces a plurality of notch feature in (111), and wherein each notch feature comprises a bottom surface and a side of the silicon wafer that is exposed to the open air.At least a portion of the side of notch feature is covered.In the context of this specification, " covering " refers to provides cover material, such as preventing or stop etching perhaps can reduce the anti-etching cover material of the etching speed on covered surface.Zone between the notch feature is etched, and makes this etching take place along < 110>direction of (111) silicon wafer, produces the printable semiconductor elements that one or more comprises the silicon structure of being carved (undercut) or complete undercutting at the bottom of the part with this.In the embodiment of a practicality, between the notch feature of adjacent position, carry out the end along < 110>direction of silicon wafer and carve, produce printable semiconductor element with this.Alternatively, select position, shape and the spatial orientation of notch feature to keep element (alignment maintenance element), such as the bridge element that printable semiconductor elements is connected to wafer to form to aim at.

In one embodiment, the part of notch feature side, but be not all, covered, produce the covered zone of side and do not have covered zone with this.The covered zone that do not have of side is etched, and for example, through the anisotropic etching method, causes the end to carve (111) silicon wafer zone between notch feature with this.In this embodiment of the present invention, etching takes place between notch feature along silicon wafer < 110>direction, produces the printable semiconductor elements that comprises by the silicon structure at quarter at the bottom of the part or the complete quarter end with this.

In another embodiment; The side of notch feature hidden fully and notch feature between the zone be etched; Its etching takes place along < 110>direction of silicon wafer; For example, the material below the covered zone is carried out etching, this causes the end to carve the zone of (111) silicon wafer between notch feature.This processing manufacturing comprises by the printable semiconductor elements of the silicon structure at quarter at the bottom of the part or the whole quarters end.In some embodiments, the following material of base plate (floor) that is positioned at notch feature is removed, for example, and through the anisotropic etching method.Alternatively, the base plate of this notch feature is hidden by part, thereby reserves inlet for etchant, and wherein this inlet is positioned on the base plate of notch feature.Wherein but the side of notch feature can more accurately be limited and select the thickness of printed element than the certain methods that adopts part to hide the side by the manufacturing approach that hides fully.

Alternatively, this method can also be included in to be made before the printable semiconductor elements, the step that geometry, physical size and the form of notch feature are made with extra care.In context, refining referring to such as the material on the surface of notch feature such as the side of groove and base plate removed processing.Refining comprise the processing that causes more smooth notch feature surface and/or cause having the processing of the notch feature of physical size and configuration of surface more uniformly, thereby cause printable semiconductor elements to have more smooth surface and characteristic and/or have more uniform physical size and form.In one embodiment, utilize the anisotropic etching technology, for example utilize the etching of hot KOH solution, geometry, physical size and/or form are made with extra care.The inventive method comprises that on geometry, physical size and/or the form treatment step manufacturing approach for preparation microelectromechanical systems (MEMS) and nanoelectronic mechanical system (NEMS) that relates to refining notch feature be useful.

The outer surface of (111) wafers of a plurality of notch feature with selected physical size, position and space orientation is patterned at this method is used for making simultaneously in a large number (for example, about 1 * 10 ³To about 1.0 * 10 ¹⁰) printable semiconductor elements array aspect is useful, said printable semiconductor elements is placed on the position and spatial orientation of accurate selection, so that they are finally assembled and are integrated in the device systems.Method of the present invention can be produced and the corresponding printable semiconductor elements array of the major part (for example about 75%-about 95%) of silicon wafer outer surface.

The present invention includes wherein between the adjacent grooves characteristic method that proceeds to complete etching along < 110>direction of (111) silicon wafer, thereby the zone of (111) silicon wafer between the end fluting characteristic fully, thereby the preparation printable semiconductor elements.Alternatively, the present invention includes wherein between the adjacent grooves characteristic incomplete etching, thereby the zone of (111) silicon wafer between the end fluting characteristic partly, and thereby produce the printable semiconductor elements of carving at the bottom of the part along silicon wafer < 110>direction.Wherein passing through the complete end of this etching processing step at some carves in the method for printable semiconductor elements; Select the spatial orientation and the physical size of the notch feature on the silicon chip outer surface, make manufacturing printable semiconductor elements remain connected on one or more end of this printable semiconductor elements, on the silicon wafer that is integrated and connected alternatively.In some embodiments, this printable semiconductor elements is directly connected on the silicon wafer, and in other embodiments, this printable semiconductor elements is connected on the silicon wafer through keeping element such as one or more aligning of bridge element.

Silicon wafer with (111) orientation is used in combination with etching system of the present invention, provides a kind of to printable semiconductor elements and aim at alternatively and such as the bridge element, keep the useful intrinsic etching stopping of element at least part or all of quarter end.For example, in some embodiments, select one to provide along the anisotropic etching system of the preferred etching of silicon wafer < 110>direction.In these embodiments; Along carrying out etching than silicon wafer < 110>direction along silicon wafer < 111>direction faster speed; And in some applications, preferably, along with than carrying out etching along silicon wafer < 110>direction of the fast 100 times speed of silicon wafer < 111>direction; And in some embodiments, along than carrying out etching along silicon wafer < 110>direction of the fast 600 times speed of silicon wafer < 111>direction.In some processing conditions, use an anisotropic etching system, etching is not carried out along < 111>direction of silicon wafer basically.In the context of this specification, the expression of " etching is not carried out along < 111>direction of silicon wafer basically " refers to and is lower than several percentage points the etching degree approximately that general printing is handled with the semiconductor element manufacturing.The effective etching system that is used for this carving treatment step produces the printable semiconductor elements with bottom surface smooth, that carve at the end end, and for example carve the bottom surface and has the surface roughness of being less than or equal to 0.5 nanometer at the end.Useful in the method anisotropic etching agent system includes but not limited in room temperature or uses the wet chemistry etching of alkaline solution under greater than the 298K temperature; Said alkaline solution such as KOH, alkali hydroxide solution; EDP (ethylene diamine pyrochatechol); TMAH (TMAH), gallium amine (amine gallate) (gallic acid, monoethanolamine, pyrazine (pyrazine), surfactant solution) and hydrazine.

The process useful that is used to hide the notch feature side comprises carry out the solution deposition of angled electron beam deposition, chemical vapour deposition (CVD), thermal oxidation and cover material such as the cover material of the mixing of metal or metal.Exemplary method comprises the angled electron beam deposition of two metal Ti/Au, is used to provide the part of notch feature side to cover." hidden " that these are cast in angled evaporation process in this embodiment, defines the thickness of printable semiconductor elements at least in part.This method comprise the treatment step that hides the notch feature side fully and, alternatively, just partly hide the treatment step of notch feature side, for example hide the treatment step of selected part, zone, area or the degree of depth in the side.

In the embodiment of the present invention aspect this, the pattern that will have the notch feature of selected size, orientation and position is provided to outer surface.In this embodiment, the notch feature on the outer surface has physical size (being length, width and the degree of depth), shape, position and the space orientation that the part of being selected as at least limits physical size, shape, position and the spatial orientation of printable semiconductor elements and selectively limits the bridge element.Choose relative position (for example spacing), shape and the spatial orientation of adjacent grooves characteristic, to limit shape, width or the length of printable semiconductor elements.For example, the spacing between this adjacent grooves characteristic defines the width or the length of printable semiconductor elements, can select the degree of depth of notch feature, to confirm the thickness of printable semiconductor elements at least in part.In some embodiments; Have one or more basically evenly the notch feature of the physical size of (promptly in about 5%) be preferred; Has one or more uniform physical size so that produce, such as the printable semiconductor elements of homogeneous thickness, width or length.Can make notch feature through any method well known in the prior art; Include but not limited to, such as the photoetching treatment of near field phase-shift photolithography, soft etching processing, stripping means, dry chemical etching, plasma etching, wet chemistry etching, micromachined, electron beam writes and passive ion etching.In an effective embodiment that the notch feature pattern with selected physical size and space orientation can be provided; The step that produces one or more notch feature at the outer surface of silicon wafer may further comprise the steps: (i) come one or more zone of cover outer surface through using a mask, thereby produce the covered zone of outer surface and do not have covered zone; And (ii) etched wafer outer surface at least a portion does not have covered zone, for example utilizes anisotropy dry type etching or isotropism dry type lithographic technique.

In the embodiment of the present invention aspect this, notch feature comprises a plurality of passages with selected physical size, position and space orientation in the wafer outer surface.For example, comprise that the notch feature of first and second passages can be patterned onto on the silicon wafer, physics is separately each other to make them.In this embodiment; The step of etching proceeds to second channel along < 110>direction of silicon wafer from first passage between notch feature; Thereby the end carve at least a portion of the silicon wafer between adjacency channel; So that be manufactured on the printable semiconductor elements between first and second passages, and optional bridge element from (111) silicon wafer.This processing produces the silicon structure at the quarter partially or completely end that comprises between first and second passages.In the effective embodiment that is used for preparing the printable semiconductor elements array; Produce a pattern that comprises the passage of the position that has abundant qualification in a large number and size at the silicon wafer outer surface, thereby make it possible under single processing mode, produce simultaneously a large amount of printable semiconductor elements.

In one embodiment, the orientation of first and second passages on the wafer outer surface on vertically is in the substantially parallel structure.In this embodiment, etch step between the notch feature produce between first and second passages, the printable semiconductor band carved of the end either partially or fully.For some embodiments preferably; The position of first and second passages and physical size are chosen for and make the printable semiconductor band keep being integrated and connected on the silicon wafer; Up to further processing; Such as relating to the treatment step that contacts with transfer equipment, this transfer equipment includes but not limited to boxing impression.For example; In one embodiment; First passage ends at first end; And second channel ends at second end, and the printable semiconductor band keeps directly or keeps the silicon wafer that element is connected to zone between second end of first terminal and this passage of said first passage through the aligning such as the bridge element.In addition.This first passage and second channel can end at third and fourth end respectively, and alternatively, the printable semiconductor band can also directly or through the aligning such as the bridge element be kept the silicon wafer that element connects zone between third and fourth end.

The method of this aspect of the present invention also comprises many selectable process steps, includes but not limited to material deposition and/or is used for the conductive structure such as electrically contacting, insulation system and/or additional semiconductor structure are formed the composition on printable semiconductor elements; Annealing steps; Wafer cleans; Surface treatment is for example scraped to reduce the roughness of outer surface to the surface; Material doped processing; Transfer equipment or use solution printing technology transfer, composition, assembling and/or the integrated printable semiconductor elements of use such as boxing impression; The wafer surface finishing; Make the printable semiconductor elements functionalization, for example, prepare hydrophilic or hydrophobic group; For example utilize etching to remove material; Growth and/or remove on the printable semiconductor elements thermal oxide layer and to the combination in any of these optional treatment steps.

The method that the present invention prepares printable semiconductor elements can also comprise the step that printable semiconductor elements is discharged from silicon wafer.In the context of this specification, " release " refers to the processing that printable semiconductor elements is separated from silicon wafer.Releasing and processing in the present invention can comprise that the aligning that one or more end with printable semiconductor elements of dismantling such as the bridge element is connected to female substrate (mother substrate) keeps element.Printable semiconductor elements can carry out through the transfer equipment that makes printable semiconductor elements contact such as the boxing impression that can be used for the contact print transfer processing from the release on the silicon wafer, such as the dry type trans-printing.In some embodiments, the contact surface of the outer surface of semiconductor element and transfer equipment such as the boxing impression of unanimity contacts, and is consistent the contact alternatively, makes semiconductor element be adhered to contact surface.Alternatively, the method for this aspect of the present invention also comprises the step of the semiconductor element registration being transferred to transfer equipment.Alternatively, the method for this aspect of the present invention comprises that also utilization receives the separating rate of dynamics Controlling to promote the printable semiconductor elements registration is transferred on the boxing impression.

An advantage that is used to make this method of printable semiconductor elements is to use given (111) the silicon wafer initiation material such as body (111) silicon wafer, more than this method can be carried out once.The reprocessing ability of this method is useful; Because it make this method the single initial silicon chip of use repeatedly repeat to become possibility, thereby make it possible to produce tens or even the printable semiconductor elements of hundreds of square feet from one square feet body silicon wafer initiation material.In one embodiment, the step of the outer surface of finishing silicon wafer after this method also is included in release and shifts printable semiconductor elements.In the context of this specification, express " finishing silicon wafer " refer to produce one smooth and be the treatment step of smooth silicon wafer outer surface alternatively, for example after discharging and/or shifting one or more printable semiconductor elements.Finishing can be carried out through any known technology of prior art, includes but not limited to polishing, etching, grinding, micromachined, chemical-mechanical polishing; Anisotropy wet type etching.In an effective embodiment; Treatment step (i) produces a plurality of notch feature at the silicon wafer outer surface; (ii) hide at least a portion side of notch feature, and the whole side that hides the groove pattern alternatively, and (iii) between the side, carry out etching; Thereby produce additional printable semiconductor elements, behind the finishing outer surface, be repeated above-mentioned steps.Use single silicon wafer initiation material, can repeat to comprise discharge and the inventive method of refinement treatment step many times.

Aspect another, the invention provides can high registration accuracy shift, registration assembling and/or registration be integrated into and receive suprabasil printable semiconductor composition and structure.In the context of this specification; Express the Coordination Treatment that " registration transfers ", " registration assembling ", " registration is integrated " refer to the space orientation that keeps being transferred element, be preferably about 5 microns and more preferably be in about 0.1 micrometer range for some application.Registration process of the present invention can also refer to the inventive method and be 5 microns and some embodiments are preferably under 500 nanometers printable semiconductor elements is shifted, assembles and/or be integrated into the ability on the specific region that receives substrate in preliminary election.The printable semiconductor composition of this aspect of the present invention and structure have strengthened accuracy, accuracy and the fidelity of trans-printing assembling and integrated technology, thereby a kind of be used to the prepare stalwartness of high-performance electronic and optoelectronic device and the manufacturing platform with commercialization feasibility are provided.Registration process among the present invention can use various transfer equipments to carry out, and these transfer equipments include, but not limited to can be used for the die transfer equipment such as elasticity and non-resilient die such as the contact print transfer processing of dry type contact print.

In an embodiment aspect this, the invention provides a kind of printable semiconductor structures that comprises printable semiconductor elements; And one or more bridge element that is connected to, is integrated and connected alternatively printable semiconductor structures and be connected to the parent crystal sheet.Select physical size, composition, shape and the geometry of this printable semiconductor elements; And bridge element; Make printable semiconductor is contacted the bridge element that can fracture with transfer equipment such as boxing impression, thereby printable semiconductor structures is discharged from the parent crystal sheet with controllable mode.

In one embodiment, bridge element, printable semiconductor elements and parent crystal sheet are connected with being integrated, so that comprise an integral body (unitary) structure.In the context of this specification, " overall structure " refers to the composition that wherein parent crystal sheet, bridge element and printable semiconductor elements comprise en-block construction.For example, in one embodiment, an overall structure comprises single, a continuous semiconductor structure, and one of them or more a plurality of bridge element are integrated to be connected to the parent crystal sheet and to be connected to printable semiconductor elements.Yet; The present invention also comprises printable semiconductor structures; Wherein this bridge element, printable semiconductor elements and female silicon chip do not comprise an overall structure; But through such as covalent bonds, adhere to and/or the adhesion of intermolecular force (for example, model moral gas force, hydrogen bond combine, active force, dispersion force between dipole) and so on is connected to each other together.

The printable semiconductor structures of this aspect of the present invention can comprise single or a plurality of bridge elements that are connected to, are preferably be integrated and connected printable semiconductor elements and parent crystal sheet.Bridge element of the present invention comprises the structure that the surface of printable semiconductor elements is connected to the parent crystal sheet.In one embodiment, one or more bridge element is connected to the parent crystal sheet with the end and/or the bottom of printable semiconductor elements.In one embodiment, the bridge element is connected to the parent crystal sheet with the end that one or two stops the length of printable semiconductor band.In some embodiments, printable semiconductor elements and bridge element are at least partly carved at the bottom of the parent crystal sheet.In an embodiment that can high registration accuracy shifts, printable semiconductor elements and bridge element be quarter at the bottom of the parent crystal sheet fully.Yet the present invention also comprises the bridge element that printable semiconductor elements is connected to the structure parent crystal sheet, that do not carved the end of by.The example of carving structure of this non-end is that the bottom with printable semiconductor elements connects and/or the bridge element of anchor to the parent crystal sheet.

The present invention includes its jackshaft element with at least two of the printable semiconductor elements different terminal or surperficial embodiments that are connected to the parent crystal sheet.Printable semiconductor structures with a plurality of bridge elements is useful for the application that those need improved, high-precision registration to shift, because they provide the bigger stability of aligning, spatial orientation and the position of semiconductor element during the contact surface that contacts and transfer to transfer equipment and/or reception substrate.

The bridge element of this aspect of the present invention is to aim to keep element, this aligning keep that element connects printable semiconductor elements and/or anchor to female substrate, such as semiconductor wafer.The bridge element for shift, in the assembling process and/or keep printable semiconductor elements in the integrated treatment step selected to and/or the position be useful.The bridge element also is useful for the relative position of in transfer, assembly process and/or integrated treatment step, keeping semiconductor element pattern or array and orientation.In the method for the invention; The bridge element keeps the position and the spatial orientation of printable semiconductor elements relating to during such as the contact of the contact surface of transfer equipments such as unitary elasticity die, bonding, transfer and integrated processing, thereby makes and can transfer to transfer equipment from parent crystal sheet registration.

The bridge element of this aspect of the present invention can separate from printable semiconductor elements, and can obviously not change the position and the spatial orientation of printable semiconductor elements in the contact of transfer equipment and/or when mobile.Through during the contact of transfer equipment and/or moving, for example shift in the contact print process in dry type, the bridge element is fractureed and/or breaks off connection and can realize separating.The separation that causes by fractureing can promote the separating rate that receives dynamics Controlling of transferring to the transfer equipment contact surface to be improved through using such as boxing impression and/or using.

In the embodiment of the present invention aspect this, select spatial configuration, geometry, composition and the physical size of bridge element, so that being provided, shifts high-precision registration.In the context of this specification, express the transfer that space orientation and relative position variation that " high registration accuracy transfers " refer to printable semiconductor elements wherein are lower than about 10% printable semiconductor elements.High-precision registration shifts and also refers to printable semiconductor elements and transfer to transfer equipment and/or receive substrate and have the good accuracy of laying.High-precision registration shifts the pattern transfer that also refers to printable semiconductor elements and has good fidelity to transfer equipment and/or reception substrate.

Bridge element of the present invention can comprise the partially or completely structure at the quarter end.Effectively the bridge element can have the width that consistent width or symmetry change in the present invention, and such as the width that is tapered into narrow neck, this width helps to discharge through fractureing the bridge element.In some embodiments; This bridge element has the mean breadth that is selected from about 100 nanometers to about 1000 micrometer ranges; Have and be selected from about 1 nanometer, and have and be selected from the average length of about 100 nanometers to about 1000 micrometer ranges to the average thickness of about 1000 micrometer ranges.In some embodiments, the physical size of this bridge element and shape are to limit with respect to the physical size that is connected to the printable semiconductor elements of parent crystal sheet this bridge element.For example, use mean breadth at least than the mean breadth of printable semiconductor elements to when young 2 times, be preferably little 10 times for some application; And/or the average thickness bridge element littler 1.5 times than the average thickness of printable semiconductor elements, can obtain registration and shift.Can also sharp characteristic be provided to the bridge element, but with help they fracture and the galley conductor element is transferred to transfer equipment and/or is received substrate from parent crystal sheet registration.

In an embodiment aspect this, this printable semiconductor elements comprises that its length is along printable semiconductor band main longitudinal axis extension, that end at one first end and second end.The first bridge element is connected to the parent crystal sheet with first end of printable semiconductor band, and the second bridge element is connected to the parent crystal sheet with second end of semiconductor tape.Alternatively, this printable semiconductor band, the first bridge element and the second bridge element are by the structure at the complete quarter end.In one embodiment, the first bridge element, the second bridge element, printable semiconductor band and parent crystal sheet comprise an overall semiconductor structure.In one embodiment, the mean breadth of the first and second bridge elements arrives about 20 times than the mean breadth little about 1 of printable semiconductor band approximately.In one embodiment, each in the first and second bridge elements is connected respectively to less than 1% to about 100% of the cross-sectional area of first terminal and second end of printable semiconductor band.The present invention includes the first and second bridge elements wherein have located adjacent one another or away from the embodiment of spatial configuration.

In the present invention, the outer surface of printable semiconductor elements and/or bridge element can be by functionalization, to bring up to the registration transfer such as the transfer equipment of boxing impression.Can be used for function scheme that registration shifts and comprise and add hydrophilic and/or hydrophobic group to the printable semiconductor elements surface, to improve bonding with the transfer equipment contact surface.An alternative chemistry is that these metals include but not limited to gold to one or more contact surface (but the surface on the printed element and/or receiving surface) metallizing.These metals can be processed into has self-assembled monolayer, but these individual layers can be bridged to printed element with receiving surface with chemical mode.In addition, two so-called naked gold surface can be when a contact (for example, through cold welding) just can form the combination of a metal solder.

Printable semiconductor elements of the present invention can be used the material manufacture in the wide region.The effective precursor material that is used to make printable semiconductor elements comprises semiconductor die film source (wafersource), and this semiconductor die film source comprises the body semiconductor wafer such as silicon single crystal wafer, polycrystalline silicon wafer, germanium wafer; Ultra-thin semiconductor wafer such as ultra thin silicon wafers; (be positioned at the semiconductor on the insulation wafer, such as the doped semiconductor silicon chip of P type or N type wafers doped and wafer with selected alloy spatial distribution such as the (Si-SiO for example of the silicon on the insulator ₂, SiGe)); And be positioned at the semiconductor on the substrate wafer, such as the silicon and the silicon on the insulator that are positioned on the substrate wafer.And, that printable semiconductor elements of the present invention can be kept somewhere scraping of from the semiconductor equipment that utilizes conventional method to handle or be not used high-quality or the semi-conducting material manufacturing handled again and get.In addition, printable semiconductor elements of the present invention can be from being positioned at sacrifice layer or substrate (for example SiN or SiO such as amorphous, polycrystalline and single-crystal semiconductor material (for example, polysilicon, amorphous silicon, polycrystalline GaAs and amorphous GaAs) film ₂) on, and various nanocrystalline film source of being annealed subsequently and the brilliant manufacturing of other bodies, said body crystalline substance includes but not limited to graphite, MoSe ₂And transient metal sulfide and yttrium bromide cupric oxide.

The dry type that shifts die such as elasticity that comprises example transfer equipment of the present invention shifts die, combined type shifts die, the consistent formula transfer equipment such as consistent formula boxing impression, and such as the multilayer transfer equipment of multilayer elastic die.It is useful handling for contact print such as the transfer equipment of boxing impression, shifts contact print such as dry type.Transfer equipment of the present invention is consistent formula alternatively.Can be used for transfer equipment of the present invention comprise contain just like submit to United States Patent (USP) and trademark office on April 27th, 2005, name be called " Composite PatterningDevices for Soft Lithography ", U.S. Patent Application Serial Number 11/115; The transfer equipment of a plurality of polymeric layers described in 954 is included it in here by reference.Available example patterning devices comprises a polymeric layer with low young's modulus in the inventive method, such as gathering (dimethyl siloxane) (PDMS) layer, uses preferably for some, and thickness is selected from about 1 micron and arrives about 100 microns scope.It is useful using low modulus polymeric layer; Because it provide can with one or more a plurality of printable semiconductor elements; Particularly have crooked, printable semiconductor elements coarse, plane of exposure smooth, smooth and/or waveform and set up good consistent the contact; And can with the substrate surface of the configuration of surface of relief intensity with wide region, such as substrate surface that is bending, coarse, smooth, smooth and/or waveform, set up the transfer equipment of good contact.

The present invention also comprises printable semiconductor elements is shifted; Comprise that high registration accuracy shifts; To such as the method on the transfer equipment of boxing impression, and/or, comprise the high registration accuracy assembling and/or be integrated into the on-chip method that receives printable semiconductor elements assembling and/or integrated.An advantage of printing process of the present invention and composition is; Can with a kind of mode of the selected spatial orientation that keeps semiconductor element with the pattern transfer of printable semiconductor elements be assembled on the substrate surface, wherein the selected spatial orientation of semiconductor element limits pattern.This aspect of the present invention be fabricated in the position of abundant qualification for a plurality of printable semiconductor elements and the space orientation on application be useful especially, wherein these positions that fully limit and space orientation is directly corresponding to selected equipment structure and equipment structure array.But transfer printing machine of the present invention can shift, location and assembling printable semiconductor elements and/or printing functionality equipment; Include but not limited to transistor, optical waveguides, microelectromechanical systems, nanoelectronic mechanical system, laser diode or the circuit that is completed into.

This processing method and composition can also be applied to the body semi-metallic except can be applicable to semi-conducting material.For example, this method, composition and structure can be utilized carbonaceous material, such as graphite individual layer and graphite linings, and other stratified materials such as mica.

In one embodiment, the invention provides a kind of method that is used for printable semiconductor elements is transferred to transfer equipment, the method comprising the steps of: the printable semiconductor structures that comprises printable semiconductor elements (i) is provided; And at least one bridge element that is connected to printable semiconductor structures and is connected to the parent crystal sheet, wherein this printable semiconductor elements and this bridge element are at least partly carved at the bottom of the parent crystal sheet; (ii) printable semiconductor elements is contacted with the transfer equipment with contact surface, wherein the contact between contact surface and printable semiconductor elements is attached to contact surface with printable semiconductor elements; And (iii) move transfer equipment, thereby printable semiconductor structures is transferred on the transfer equipment from the parent crystal sheet with a kind of mode that causes the bridge element to fracture.

An embodiment, the present invention provides a kind of being used for that printable semiconductor elements is assembled into the method on the receiving surface of substrate, and the method comprising the steps of: printable semiconductor elements (i) is provided; And at least one bridge element that is connected to said printable semiconductor structures and is connected to the parent crystal sheet, wherein said printable semiconductor elements and said bridge element part are at least carved at the bottom of said female silicon chip; (ii) said printable semiconductor elements is contacted with the transfer equipment with contact surface, wherein the contact between said contact surface and said printable semiconductor elements is attached to said contact surface with said printable semiconductor elements; (iii) move said conversion equipment with a kind of mode that causes said bridge element to fracture; Thereby said printable semiconductor structures transferred on the said transfer equipment from said parent crystal sheet, thereby form the said contact surface that is distributed with said printable semiconductor elements on it; The said printable semiconductor elements that (iv) will be positioned on the said contact surface contacts with the said receiving surface of said substrate; And (v) the said contact surface with said consistent formula transfer equipment separates with said printable semiconductor elements; Wherein said printable semiconductor elements is transferred to said receiving surface, thereby said printable semiconductor elements is assembled on the said receiving surface of said substrate.

In one embodiment, the invention provides a kind of method that is used to make printable semiconductor elements, comprise step: (1) provides has the silicon wafer that (111) are orientated and have outer surface; (2) the said outer surface at said silicon wafer produces a plurality of concave character, and wherein each said concave character comprises the bottom surface and the side of the silicon wafer of exposure; (3) at least a portion of the said side of the said notch feature of covering; And (4) carry out etching between said notch feature, and wherein etching takes place along < 110>direction of said silicon wafer, thereby makes described printable semiconductor elements.

Description of drawings

Figure 1A provides diagram the schematic cross-sectional view that is used to make the exemplary method of printable semiconductor elements of the present invention, and said printable semiconductor elements comprises the monocrystalline silicon zone from the body silicon wafer with (111) orientation.Figure 1B provides and has set forth the flow chart that is used for producing from the body silicon wafer treatment step of printable semiconductor elements in this method.

Fig. 1 C provides cross-sectional view to handle sketch map, this figure diagram wherein partly covering but be not the manufacturing approach that hides the side of notch feature fully.Fig. 1 D provides cross-sectional view signal processing figure, this figure diagram wherein hide the manufacturing approach of the side of notch feature fully.

Fig. 1 E provides the image that raceway groove is constructed but make with extra care the notch feature of side that has in the silicon (111).Notch feature shown in Fig. 1 E is limited phase-shift photolithography, metal-stripping and passive ion etching and removing of subsequent metal etching mask.Fig. 1 F provides having the raceway groove structure and making with extra care the image of the notch feature of side in the silicon (111).

Fig. 2 A and 2B provide the diagrammatic top view of printable semiconductor structures of the present invention, and this printable semiconductor structures comprises a printable semiconductor elements and two bridge elements.In the structure shown in Fig. 2 A, these bridge elements are placed away from each other, and in the structure of Fig. 2 B, these bridge elements are placed located adjacent one anotherly.

Fig. 2 C and 2D provide the image that printable semiconductor elements is connected to the bridge element of parent crystal sheet.

Fig. 3 (a) schematically diagram a kind of use be integrated with the GaAs line of the trans-printing of resistive band, the processing of on plastics, making transistor, diode and logical circuit, these GaAs lines prepare by monocrystalline GaAs parent crystal sheet.(b) the SEM image of row GaAs line (having a resistive band) array, the end of these GaAs lines is connected on the parent crystal sheet.This part line of representing by arrow be positioned at array lines below, separate on expression GaAs line and the body silicon.This insertion figure has provided not have and has supported each root line that ground exists, and clearly show that its triangular-section.(c) utilizing that trans-printing forms to the on-chip GaAs linear array shown in (b) of PET, passage length is that 50 microns and gate length are the SEM image of each MESFET of 5 microns.(d) Ti/n-GaAs Schottky diode optical microphotograph is imaged onto on the PET plate.These insertions figure shows that an electronic pads connection is positioned on the resistive band of these line one ends, and another electrode (150nm Ti/150nm Au) pad is directly connected on the GaAs line that is used to form the Schottky contact.(e, f) to have a various logic gates and be installed in the optical imagery that the PET substrate of each MESFET on the crooked white marking axle (f) was gone up and be positioned to flat surfaces (e).

Fig. 5: the circuit diagram of inverter (a), optical imagery (b) and output-input characteristics (c).All MESFET gate lengths are 5 microns.This V _Dd(GND) is biased to 5V with respect to ground.

Fig. 6: the circuit diagram of Different Logic door, optical imagery and output-input characteristics: (a, b, c) NOR gate; (d, e, f) NAND gate.The gate length of all MESFET is 5 microns.This ratio scale is represented 100 microns.Be applied to the V on these gates _DdWith respect to ground (GND) is 5V.The logical zero of this NOR gate and NAND gate and " 1 " input signal are driven by-5V and 2V respectively.The logical zero of this NOR gate is respectively 1.58-1.67V and 4.1V with " 1 " output.The logical zero of this NAND gate is respectively 2.90V and 4.83-4.98V with " 1 " output.

Fig. 7: (a) be positioned at that PU/PET is on-chip, passage length is that 50 microns and gate length are the SEM image of each GaAs line MESFET of 2 microns, shows that each transistor is formed by the GaAs line of ten collimations.(b) the transistorized current-voltage shown in the figure (a) (is I _DSTo V _DS) curve.See this V from top to bottom _GSBe reduced to-3.0V from 0.5V, step-length is 0.5V.This illustration shows that this transistor is at V _DSTransfer curve in the zone of saturation of=4V.

Fig. 8: (a, b) experiment (blueness) of the RF of the different GaAs-line MESFET of gate length response and simulation (redness) result: 2 microns (a) and 5 microns (b).This measured value is to utilize the detection structure shown in (a) middle illustration to carry out.(c) f _TDependence to gate length.Measurement result on this different symbolic representation distinct device; This dotted line is corresponding to simulation.

Fig. 9: the mechanical flexibility characteristic that is positioned at the on-chip high speed GaAs-line of PU/PET MESFET (gate length is 2 microns).(a) optical imagery of measurement mechanism being installed.V _DS=4V and V _GSUnder=the 0V, surface stress effect (on the occasion of corresponding respectively to the stress that stretches and compress with negative value) is to flowing through the influence of source electrode to the saturation current (b) of drain electrode; And (c) at V _DSON/OFF current ratio in the zone of saturation of=4V.

Figure 10: the signal handling process of making monocrystalline silicon zone.(a) SF ₆Raceway groove in plasma etching (111) silicon face.(b) thermal oxidation and angled evaporation Ti/Au layer passivation side.(c) last, by hot KOH/IPA/H ₂Carve this silicon ribbon at the bottom of the O solution.The cross section SEM image of the band of (d) carving at the bottom of the part.(e) discharge flexible band.

Figure 11: by the AFM figure that carves the micro-structural silicon that produces at the bottom of the anisotropy wet type etching.(a) the AFM height image of the band on the PDMS die, downside is made public.When the edge of these bands was measured, these bands were 115 to 130 nanometer thickness, the arc decline in the centre.(b) afm image of the downside of the band of 500 nanometer thickness has disclosed by KOH/IPA/H ₂Carve the nanoscale roughness of introducing at the bottom of the O solution.

Figure 12: be used for the signal handling process of micro-structural silicon on from " donor " wafer transfer to plastic substrate.(a) the PDMS die rolls against chip, and this chip has the band of carving at the end of anchor on wafer.(b) band is combined on the die and can removes from this wafer through peeling off die.(c) then will be with and be printed onto on the plastic substrate from die.(d) the SEM image of the band carved of the almost completely end of anchor on donor wafer.(e) that remove from donor and paste the optical microscopy map of the band on the die.(f) lay flexiplast " chip " photograph for preparing the TFT that gets by the silicon ribbon that shifts.

Figure 13: be positioned at the on-chip monocrystalline silicon bottom gate of PET/ITO transistor characteristic electron; The L=100 micron, W=100 micron, linear mobility 360cm ²V ^-1s ^-1Saturated mobility 100cm ²V ^-1s ^-1(a) transmission characteristic (VD=0.1) shows that ON/OFF ratio is about 4000, and illustration is the vertical view of equipment.(b) current/voltage (I-V) characteristic.

Figure 14: (a) be used to make the heterojunction GaN wafer sketch map of HEMT (HEMT, the two-dimensional electron gas (2DEG) that forms at ALGaN and GaN interface); (b) the HEMT geometry on the plastic substrate; (c) the Ws-GaN design of supporting with two " narrow bridge " at the Ws-GaN end of tape.Utilizing flexibly, anisotropic etching is orientated the Ws-GaN element of making nothing support ground existence.

Figure 15: the schematic illustration that Ws-GaN HEMT is fabricated onto the step on the plastic substrate.

Figure 16: (a) the GaN wafer before the Si below the TMAH wet etching.(b) nothing after the TMAH etching supports the GaN band that ground exists.Note to sacrifice the etching of Si layer and the color distinction between the etch areas not.(c-d) the SEM image of the intermediate steps of the Si below the TMAH anisotropic etching.(e) be soaked with the SEM image of the PDMS plate of the μ s-GaN object that combines by model moral gas force.(f) transfer to the SEM image of the μ s-GaN of the PET that scribbles PU.This metal and polymer areas by artificially go up color, just to check.

The platform (stage) of Figure 18 (a) actual flexion and the optical imagery of plastic apparatus.(b) differently curved radius (with and corresponding stress) under the transfer curve that obtains.I-V curve (orange) that (c) when plastic plate bends to the maximum deflection radius, is obtained and plastic plate is obtained when flattening after bend cycles I-V curve (blue).

Figure 19 provides diagram the handling process sketch map that is used to make the method for multilayer printable semiconductor elements array of the present invention.

Four layers of Si (111) that Figure 21 provides (a) that big specification is provided are with the picture of collimation array.(b and c) overlook observe and the figure (a) during (d and e) angled observation shown in the SEM image of four layers of Si (111).

Figure 22 provides the picture (a) and the OM image (b and c) of flexible Si (111) band that discharges.(d is to f) is the SEM image of the band shown in (a).

Figure 23 provides the optical imagery (a) of Si (111) band of transferring to the on-chip collimation of PDMS.(b) come from the afm image of four bands in the array shown in the figure (a).(c) lay the picture of flexible polyester film of Si (111) the array pattern of four shifting science and technology in four directions circulations that come from single Si sheet.

Embodiment

Referring to accompanying drawing, identical numeral components identical and the same numbers that appears in the more than one accompanying drawing are indicated components identical.And, these definition below hereinafter using:

" can print " and relate to and the substrate exposure at high temperature (promptly not to be less than or equal under about 400 degrees centigrade temperature) realization transfer, assembling, composition, to organize and/or be integrated on the substrate or inner material, structure, apparatus assembly and/or integrated function device; In one embodiment of the invention, but printing material, element, apparatus assembly and equipment can shift contact print transfer, assembling, composition through solution printing or dry type, organize and/or be integrated on the substrate or inner.

" printable semiconductor elements " of the present invention for example comprises through using dry type to shift contact print and/or solution printing process assembled and/or be integrated into the semiconductor structure on the substrate surface.In one embodiment, printable semiconductor elements of the present invention is whole monocrystalline, polycrystalline or microcrystal inorganic semiconductor structure.In one embodiment, printable semiconductor elements is connected on the substrate such as the parent crystal sheet through one or more bridge element.In the context of this specification, overall structure is the en-block construction with characteristic of mechanical connection.Semiconductor element of the present invention can be unadulterated or mix to have selected alloy spatial distribution, and the multiple different dopant material of can mixing, and comprises P and N type alloy.The present invention includes at least one cross sectional dimensions and be less than or equal to about 1 micron nanostructure printable semiconductor elements more than or equal to about 1 micron micro-structural printable semiconductor elements and at least one cross sectional dimensions.Useful printable semiconductor elements comprises the element that those obtain from " top-down " processing of high-purity body material in plurality of applications, and said high-purity body material is such as those high-purity crystals semiconductor wafers that utilizes conventional high-temperature process technology to produce.In one embodiment; Printable semiconductor elements of the present invention comprises composite construction; This composite construction has a semiconductor that is operably connected at least one supplementary equipment therefore assembly or structure; This supplementary equipment therefore assembly or structure such as conductor layer, dielectric layer, electrode, additional semiconductor structure or their combination in any.In one embodiment, printable semiconductor elements of the present invention comprises tensile semiconductor element and/or heterojunction semiconductor element.

" cross sectional dimensions " refers to the size of the cross section of equipment, apparatus assembly or material.Cross sectional dimensions comprises width, thickness, radius and diameter.For example, having banded printable semiconductor elements characterizes with length and two cross sectional dimensions; Thickness and width.For example, the printable semiconductor elements that has a column characterizes with length and cross sectional dimensions diameter (alternatively using radius).

In this manual; Use as the same meaning term " flexibility " and " flexible "; And refer to and be unlikely to experience the deformation ability that produces remarkable stress when material, structure, equipment or apparatus assembly are deformed to curved shape, this remarkable stress is such as being the stress the failpoint of exosyndrome material, structure, equipment or apparatus assembly.In an example embodiment; Flexible material, structure, equipment or apparatus assembly can be deformed into curved shape; And do not produce stress more than or equal to about 5%; For some are used,, and for some are used, more preferably be more than or equal to about 0.5% preferably more than or equal to about 1%.

" semiconductor " refers to any material that under very low temperature, has tangible electrical conductance for insulator at the temperature place of about 300K.In this manual, the semi-conductive use of term be intended to microelectronics and electronic equipment in the use of this term consistent.The semiconductor that is used for the present invention can comprise such as silicon, germanium and adamantine elemental semiconductor; IV compound semiconductor such as SiC and SiGe; Such as the III-V family semiconductor of AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN and InP, such as Al _xGa _1-xThe triple semiconducting alloies of II1-V family of As, the II-VI family semiconductor such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS and ZnTe, the semiconductor CuCl of I-VII family is such as the IV-VI family semiconductor of PbS, PbTe and SnS, such as PbI ₂, MoS ₂And the layer semiconductor of GaSe, such as CuO and Cu ₂The oxide semiconductor of O.The extrinsic semiconductor (extrinsic semiconductor) that the term semiconductor comprises intrinsic semiconductor (intrinsic semiconductor) and is doped with a kind of or more kinds of selected materials; Comprise the semiconductor with p type dopant material and the semiconductor of n type dopant material, to provide to given application or the useful useful characteristic electron of equipment.The term semiconductor comprises composite material, and this composite material comprises the mixture of a plurality of semiconductors and/or alloy.The useful particular semiconductor material of application more of the present invention is comprised; But be not limited to Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP and GaInAsP.The porous silicon semi-conducting material is useful for the present invention in the application of transducer and field of light emitting materials, such as light-emitting diode (LED) and solid-state laser.The impurity of semi-conducting material is atom, element, ion and/or the molecule except that this semi-conducting material itself, or any alloy that is provided to semi-conducting material.Impurity is the undesired material that appears in the semi-conducting material, and they possibly cause negatively influencing to the electrology characteristic of semi-conducting material, and these impurity include but not limited to, oxygen, carbon and the metal that comprises heavy metal.Beavy metal impurity includes, but not limited to the family of elements between copper and lead on the periodic table, calcium, sodium and all ions, compound and/or its complex.

In this manual; Term " good electron performance " and " high-performance " are used as the same meaning; And refer to and have such as the characteristic electron of field-effect mobility, threshold voltage and on-off ratio, equipment and apparatus assembly such as required functions such as electronic signal switch and/or amplifications can be provided.The example printable semiconductor elements of displaying good electron performance of the present invention can have more than or equal to 100cm ²V ^-1s ^-1The intrinsic field-effect mobility, preferably, the intrinsic field-effect mobility is more than or equal to about 300cm for some are used ²V ^-1s ^-1The example transistor of displaying good electron performance of the present invention can have more than or equal to about 100cm ²V ^-1s ^-1The intrinsic field-effect mobility, preferably, the intrinsic field-effect mobility is more than or equal to about 300cm for some are used ²V ^-1s ^-1, and for some are used more preferably, the selffield effect mobility is more than or equal to about 800cm ²V ^-1s ^-1The example transistor of displaying good electron performance of the present invention can have and is lower than about 5 volts threshold voltage and/or greater than about 1 * 10 ⁴The on-off ratio.

" plastics " refer to generally and when being heated, can be molded or be shaped, and any synthetic or naturally occurring material that hardens into required form, or the combination of any of these material.The example plastics that can be used in equipment of the present invention and the method comprise, but are not limited to polymer, resin and fiber derivative.In this manual; The term plastics mean and comprise synthetic plastics material; This synthetic plastics material comprises that one or more has the plastics of one or more additives, such as structure reinforcing agent, filtering agent, fiber, plasticizer, stabilizer the required chemistry or the additive of physical property can be provided maybe.

" elastomer " refers to and can be stretched or be out of shape, and can be returned to its original-shape and do not have the polymeric material of permanent basically deformation.Elastomer experience usually is flexible deformation basically.Can be used for the mixture that example elastomer of the present invention can comprise polymer, copolymer, synthetic material or polymer and copolymer.Elastic layer refers to and comprises at least one elastomeric layer.Elastic layer can also comprise alloy and other non-elastic materials.Can be used for elastomer of the present invention can include but not limited to, thermoplastic elastomer (TPE), styrene materials, olefin material, polyolefin, TPUE, polyamide, rubber polymer, PDMS, polybutadiene, polyisobutene and gather (ethylene-butadiene-styrene), polyurethane, polychloroprene and silicones.Elastomer provides the boxing impression useful to this method.

" transfer equipment " refers to and can receive and/or reappose such as the element of printable semiconductor elements or the equipment or the apparatus assembly of element arrays.Can be used for transfer equipment of the present invention and comprise having the consistent transfer equipment that one or more can set up the consistent contact surface that contacts with those elements that will shift.This method and composition are particularly suitable for being used in combination with transfer equipment, and this transfer equipment comprises the boxing impression that can be used for the contact print processing.

" large tracts of land " refers to more than or equal to about 36 square inches area, such as the receiving surface of the substrate that is used for device fabrication.

" equipment field-effect mobility " refers to the field-effect mobility such as transistorized electronic equipment, calculates as utilizing the output current data corresponding with this electronic equipment.

" the consistent contact " refers to surface, coating surface and/or deposits the contact of setting up between the surface of material on it, and the material that is deposited possibly be useful for transfer on the substrate surface, assembling, tissue and integrated morphology (such as printable semiconductor elements).In one aspect, consistent one or more contact surface macroscopic view that relates to consistent transfer equipment that contacts adapts to substrate surface or adapts to the global shape such as the object surfaces of printable semiconductor elements.Aspect another, consistent one or more contact surface microcosmic that relates to consistent transfer equipment that contacts adapts to substrate surface, makes to form the tight contact that does not have the space.The consistent use that contacts of term is consistent with the use of this term in soft print field.Can between one or more the naked contact surface of consistent transfer equipment and substrate surface, set up consistent the contact.Alternatively, can apply contact surface,, and set up consistent the contact between the substrate surface like a kind of contact surface of transfer equipment with material for transfer, printable semiconductor elements, apparatus assembly and/or deposition equipment above that at one or more.Alternatively, can and be coated with between the substrate surface such as the material of material for transfer, solid photoresist layer, pre-polymer layer, liquid, film or fluid at one or more of consistent transfer equipment contact surface naked or that apply and set up consistent the contact.

" lay accuracy " and refer to transfer method or equipment and will transfer to the ability of select location such as the element of printable semiconductor elements; This select location or with respect to position such as other apparatus assemblies of electrode, or with respect to the position of the selection area of receiving surface." well lay " but accuracy refers to equipment and method can printed element be transferred to respect to another equipment or apparatus assembly or with respect to the selected location of receiving surface institute favored area; Simultaneously be less than or equal to 50 microns with respect to the spatial offset of the position that is absolutely correct;, some, and for some application, more preferably are less than or equal to 5 microns for using more preferably for being less than or equal to 20 microns.Comprise at least one equipment but the invention provides with the printed element well laying accuracy and shift.

" reproduction degree " refer to such as the selected element pattern of printable semiconductor elements pattern transfer to well the substrate receiving surface the measuring of degree.The well reproduced degree refers to the selected element pattern transfer that wherein in transfer process, keeps each relative positions and orientation; For example each element is less than with respect to the spatial offset of their positions in selected pattern or equals 500 nanometers, more preferably for being less than or equaling 100 nanometers.

" the quarter end " refer to wherein such as the bottom surface of printable semiconductor elements, bridge element or both elements at least part with separate or unfixed structure construction such as another structure of parent crystal sheet or body material.Carve to refer to wherein and construct from another structure separated structures such as parent crystal sheet or body material fully such as the bottom surface of printable semiconductor elements, bridge element or both elements at the end fully.It can be partially or completely not have to support the structure that ground exists that structure is carved at the end.Another support structure such as parent crystal sheet or body material that structure can partially or completely be separated with it by them is carved at the end.Structure is carved at the end can be attached in the surface except that the bottom surface, another structure of stickup and/or connection such as wafer or other body materials.For example, the present invention includes method and composition that printable semiconductor elements wherein and/or bridge element locate to be connected to wafer endways, this end is positioned on the surface except that the bottom surface (for example, sees Fig. 2 A and 2B).

In following specification,, a large amount of details of equipment of the present invention, apparatus assembly and method have been set forth for the present invention is provided the accurately thorough explanation of essence.Yet to those skilled in the art, will become it is apparent that, can put into practice the present invention without these details.

The invention provides and be used to make printable semiconductor elements and the pattern of printable semiconductor elements and printable semiconductor elements is assembled into the method and apparatus on the substrate surface.The method of making the high-quality printable semiconductor elements with low-cost semiconductor material body is provided.The present invention also provides semiconductor structure and the method for printable semiconductor elements being transferred to transfer equipment and/or reception substrate from parent crystal sheet high registration accuracy.These methods of the present invention, equipment and apparatus assembly can be produced high-performance electronic and optoelectronic device and equipment array on flexible plastic substrate.

Figure 1A provides diagram the schematic section that is used to prepare the exemplary method of printable semiconductor elements of the present invention, and this printable semiconductor elements comprises the printable semiconductor band from the monocrystalline silicon of the body silicon wafer with (111) orientation.Figure 1B provides a flow process, and this flow process has been set forth and has been used for comprising repeatably treatment step from the treatment step of this method of body silicon wafer production printable semiconductor elements.

Fig. 1 C provides cross section signal processing figure, the lateral parts ground rather than the covered fully manufacturing approach of notch feature that this has schemed diagram.Fig. 1 D provides cross section signal processing figure, this figure diagram wherein the side of notch feature by the manufacturing approach that hides fully.Shown in Fig. 1 D, also hide the part of notch feature base plate, rather than all.In this embodiment, this method comprises the step of the following material of the covered side that is etched in notch feature.The board structure that this part hides is that etchant provides an inlet, thereby etching can be occurred between the notch feature, between the adjacent grooves characteristic.The inventive method that adopts the side hide notch feature fully is to the qualification of printable semiconductor elements thickness with to select to provide on improved accuracy and the precision be useful.In one embodiment, the side is hidden fully, thereby the passivation border is only appeared on the base plate of notch feature.In these methods, the thickness of band is not limited on the passivation border, but by the height of base plate, the height of raceway groove and the end face of silicon chip limit.

The method that the present invention makes printable semiconductor elements can also comprise the step that geometry, physical size and form to notch feature are made with extra care.To notch feature refining can be after producing notch feature and form and/or discharge printable semiconductor elements before any a moment of manufacturing processing carry out.In an effective embodiment, before relating to the treatment step that hides the notch feature side partially or completely, notch feature is made with extra care.The raceway groove that Fig. 1 E provides having in the silicon (111) to be produced is constructed not by refining notch feature image.Notch feature shown in Fig. 1 E is phase-shift photolithography, metal-stripping and passive ion etching and remove etch masks subsequently and limit.Fig. 1 F provides the notch feature image that channel arrangements side quilt is made with extra care that has in the silicon (111).Notch feature shown in Fig. 1 F is by phase-shift photolithography, metal-stripping and passive ion etching, by means of the refining of anisotropic etching in hot KOH solution with remove etch masks subsequently and limit.This sample is also handled with angled evaporation of metal.Shown in these image comparison, the base plate of raceway groove and side limit more smoothly than the base plate and the side of raceway groove among Fig. 1 E among Fig. 1 F.

In this context, refining referring to such as the side of notch feature and the surperficial material of notch feature of base plate removed processing.Make with extra care the processing that comprises the processing that causes more smooth notch feature surface and/or cause having the notch feature of more uniform physical size and configuration of surface.In one embodiment, utilize the anisotropic etching technology, for example utilize the etching of hot KOH solution, geometry, physical size and/or form are made with extra care.But the anisotropy wet type etching to raceway groove is particularly useful for the generation of (111) silicon ribbon of registration transfer.The advantage of this refinement treatment step comprises that (1) provides the qualification of the improved raceway groove base plate of confirming according to the crystallographic axis of parent crystal sheet, and (2) crystallographic axis through the parent crystal sheet provides improved raceway groove side to limit.

Among the present invention, select spatial placement, geometry, composition and the physical size of bridge element or these combination in any, shift so that high-precision registration to be provided.Fig. 2 C and 2D provide the image of bridge element, and these bridge elements are connected to the parent crystal sheet with printable semiconductor elements.Fig. 2 C shows (narrow) bridge element that can print silicon cell and but printed element is connected to mother (SOI) wafer.The geometry of printable semiconductor elements and bridge element is limited the SF6 etching.Shown in Fig. 2 C, printable semiconductor elements and bridge element bearing have rounded corner.The circularity of these corners and the overall geometry of these elements have reduced the ability that when utilizing the PDMS transfer equipment, discharges printable semiconductor elements.Also show (narrow) bridge element that can print silicon cell and but printed element is connected to mother (SOI) wafer among Fig. 2 D.Geometry is limited hot KOH anisotropic etching.Shown in Fig. 2 D, this printable semiconductor elements and bridge element bearing have sharp-pointed corner.The acuteness of those corners focus the stress to abundant qualification split off a little on, therefore and strengthened the ability of utilizing the PDMS transfer equipment to discharge these elements.

The GaAs line collimation array that utilizes photoetching and anisotropy chemistry etching to produce with integrated ohm contact (ohmic contact) from the high quality single crystal wafer provide a kind of be expected can be used for transistor, Xiao Jite diode, gate and even the material of complicated circuitry more on the flexible plastic substrate.These equipment lists reveal outstanding electricity and mechanics characteristic, these two performances for emerging low cost, be commonly referred to the large area flexible person in electronics of grand electronics all very important.

For the function device that can be used for plurality of applications (for example, optics, photoelectricity device, electronics device, senser element etc.), the micron of monocrystalline inorganic semiconductor and nanoscale lines, band, platelet etc. are attractive construction units.For example, can be assembled into the array of collimation and the transmission channel that is used as flexible thin-film transistor (TFT) on the plastic substrate through Langmuir/Bu Luojie trick (or micro-fluidic technologies) by the synthetic Si nano wire of " bottom-up " method.In a diverse ways, be that about 100nm and width are at several microns micrometer/nanometer level Si element (the micro-structural silicon that arrive the form of the band in the hundreds of micrometer range with thickness; μ s-Si) can produce from high-quality, monocrystalline body source (for example, SOI (silicon-on-insulator), SOI wafer, or body wafer) through " top-down " method.Such material can be used for being manufactured on the flexible TFT on the plastic substrate, and the equipment mobility is up to 300cm ²V ^-1s ^-1Should cause having the silicon-based semiconductor material of similar superperformance based on source material of high quality wafer (aspect the low and low surface defect density of the doped level, uniform doping, the surface roughness that fully limit), these superperformances are useful for reliable, high performance operation of equipment.Should " top-down " make handle attractive still because it provides the high-sequential that in " xeroprinting " process, will be limited to wafer level to organize nano/micron structure to remain into final (for example plastics or other) on-chip possibility of equipment.Although utilize silicon possibly obtain high-performance, utilize GaAs can obtain better characteristic (the for example speed of service), for example, because the high about 8500cm of intrinsic electron mobility of GaAs ²V ^-1s ^-1Research has before confirmed, utilizes anisotropy chemistry etch step, produces the technology of the Nano/micron line with triangular cross section from the GaAs wafer through " top-down " manufacturing step.Through the GaAs line all also is on these GaAs lines, to form ohm contact when being connected on the wafer, and then their trans-printings is made up the mechanically flexible metal-semiconductor field effect transistor (MESFET) with excellent in performance to plastic substrate.These transistors show single small signal gain in the gigahertz zone.This example confirmed with trans-printing as assembling/integrated when strategy, on plastic substrate, make up the ability of the various functional circuit elements unit such as inverter and gate as active block with the MESFET of these types and based on the diode of GaAs line.The system of these types is important being used for steerable antenna, monitoring structural health conditions device and requiring on the light plastic substrate, to have the large area electron circuit of other equipment of high speed, high-performance flexible equipment.

In this design; Line is made public with original, the exposed surface of ohm bar; Further lithographic printing (lithographic) is handled and metallization to be used for, and to limit source electrode and drain electrode (250nm Au), source electrode is connected integrated ohm contact on line with drain electrode.For transistor, these electrodes define source electrode and drain electrode; For diode, they represent Ohmic electrode.The contact that formed by photoetching and online and plastic substrate are stripped to when integrating on the naked part of line defines Schottky contact that is used for diode and the gate electrode that is used for MESFET.All processing to plastic substrate all are to take place in the temperature below 110 ℃.We do not observe owing to mismatch in coefficient of thermal expansion or other maybe effect cause the GaAs line and peel off from substrate.In transistor, the width means of gate electrode is used to control the critical dimension of the speed of service.Electrode position between source electrode and the drain electrode is inessential relatively in this work.This degree of holding to bad registration is very important on plastic substrate, obtaining high-speed cruising reliably; Wherein owing to slight uncontrollable distortion can take place plastics in the processing procedure; Accurately registration often is a challenge or impossible, does not have the degree of holding to bad registration in the equipment of non-auto-collimation high speed MOSFET (metal-oxide semiconductor fieldeffect transistor) type.With suitable geometry a plurality of transistors and diode are linked together and to have produced functional logic circuit.Fig. 3 A signal has shown NOR gate.

Scanning electron microscopy (SEM) image (Fig. 3 C) shows ten parallel lines, and these lines form transistorized semiconductor subassembly.The passage length of this equipment and grid length are respectively 50 microns and 5 microns.These geometries are used to make up simple integrated circuit, i.e. gate.Ti/Au bar in the gap between source electrode and drain electrode forms the Schottky contacts with the n-GaAs surface.This electrode plays a grid, is used for the electric current of modulated current between source electrode and drain electrode.Diode (Fig. 3 D) uses at one end has ohm bar has the Schottky contact at the other end line.Fig. 3 E and 3F have shown the image of the on-chip GaAs transistor of PET, diode and ball bearing made using set.Among Fig. 3 F, have the bending shaft of the PET plate of circuit, indicated the pliability of these electronic units around white marking.

DC characteristic (Fig. 3 C) on the plastics based on the MESFET of line demonstrate qualitatively be formed at wafer on MESFET have identical characteristic (Fig. 4 A).Electric current (I between source electrode and the drain electrode _DS) be applied in the bias voltage (V on the grid _GS) modulation well, i.e. I _DSWith V _GSReduction and reduce.Aspect this, negative V _GSEfficient carrier (electronics that promptly is used for n-GaAs) in the decay passage area and reduction channel thickness.In case V _GSNegative arriving to a certain degree, damping layer equals the thickness of n-GaAs layer, and the electric current between source electrode and the drain electrode (is I by pinch off _DSBasic vanishing).Shown in Fig. 4 A, at V _GSLess than-the 2.5V place, I _DSAlmost reduce to zero.At source electrode-drain voltage (V _DS) when being 0.1V (linear areas), this pinch-off voltage (is grid voltage V _GS) be 2.7V.(the V in the zone of saturation _DS=4V), Fig. 4 B shows transistorized transfer curve.According to Fig. 4 B, ON/OFF current ratio and maximum transconductance are confirmed as about 10 respectively ⁶With about 880 μ S.The function of the spacing (being passage length) between the number that this whole source electrode-drain current is a line (being effective channel width) and source electrode and the drain electrode.When channel width was constant, the transistor with jitty can provide high relatively electric current.For example, at V _GS=0.5V and V _DSDuring=4V, the saturated I of transistor _DS3.8mA (Fig. 4 C) when the 1.75mA when its passage length is 50 μ m is increased to its passage length and is 25 μ m.Using for some, although have the transistor of jitty high electric current can be provided, is difficult owing to nip off electric current fully, and the ON/OFF current ratio is tending towards descending.Shown in Fig. 4 C, has the transistorized I of the passage length of 25 μ m _DSEven for V _GSAlso still several microamperes magnitude during for-5V.

Wherein, J representes to apply the forward diode current density of bias voltage (V), and k is a Boltzmann constant, and T is absolute temperature (i.e. 298K in the experiment), φ _BBe schottky barrier height and A ^*The effective Rui Chasheng constant that is GaAs (is 8.64Acm ^-2K ^-2).Through drawing the graph of a relation (vignette) between InJ and the bias voltage (V), confirm saturation current J according to the intercept and the gradient of linear relationship (straight line of vignette) ₀With ideal factor n.φ _BAmount estimate through equality (2).φ _BWith n jointly as the evaluation criteria of schottky interface characteristic.Two interface charge attitudes (charge state) that all depend on to heavens between metal and the GaAs, i.e. the increase of charge state will cause φ _BReduction and the increase of n value.For the diode of making in this work, confirm φ according to the vignette of Fig. 4 D _BBe respectively 512meV and 1.21 with n.These equipment are compared with the diode on being structured in wafer, have to hang down Schottky barrier (512meV is to about 880meV) of some and bigger ideal factor (1.21 pairs about 1.10) slightly.

These GaAs-line equipment (being MESFET and diode) can integratedly be formed into the gate that is used for complicated circuit.For example, connect two passage length MESFET different, that have different saturation currents, form an inverter (logic inverter) (Fig. 5 A and 5B).This load transistor (top) and switching transistor (bottom) have 100 and 50 microns passage length respectively, and the grid length of 150 microns channel width and 5 microns.It is saturation current about 50% of switching transistor that this design causes saturation current from load transistor, and this guarantees the V of load line and switching transistor _GS=0 curve intersects at a little cut-in voltage in the range of linearity.In the zone of saturation, i.e. V _DdBe biased to 5V, measure reverser.As grid (V to switching transistor _In) apply a big negative voltage (logical zero) when this transistor is closed, the voltage (V on the output node _Out) equal V _Dd(logical one, high positive voltage) is because load transistor is opened always.V _InIncrease switching transistor opened and provided big electric current to pass switching transistor and load transistor.When switching transistor is opened fully, i.e. V _InWhen being big positive voltage (logical one), V _OutBe reduced to a low positive voltage (logical zero).Fig. 5 C has shown transfer curve.This inverter shows greater than 1 maximum voltage gain (i.e. (dV _Out/ dV _In) _Max=1.52).Through increasing a level conversion branch road (shown in Fig. 3 D) that comprises Schottky diode, with V _OutLogic state transition become to be suitable for the integrated voltage of further circuit.

The a plurality of equipment parallel connections or the tandem compound of the type are obtained more complicated logic function, such as NOR gate inclusive NAND door.For the NOR gate shown in Fig. 6 A and 6B, two identical MESFET that parallel connection connects play switching transistor.Open any switching transistor (V through applying a high positive voltage (logical one) _AOr V _B), can provide one pass load transistor drain electrode (V _Dd) and the big electric current of arrival point (GND), thereby cause output voltage (V ₀) be in low level (logical zero).Only (logical zero) just can obtain high positive output voltage (logical one) when two inputs all are in high negative voltage.Fig. 6 C has shown the dependence of output to the input of NOR gate.In the structure (Fig. 6 D and 6E) of NAND gate, have only when applying high positive voltage (logical one) two switching transistors are all opened, the electric current that passes all crystals pipe is very big.In this structure, output voltage shows low relatively value (logical zero).Under other input combinations, almost do not have electric current to flow through transistor, cause can with V _DdSuitable high positive output voltage (logical one) (Fig. 6 F).The type gate and/or passive component (for example, resistor, capacitor, conductor etc.) further integrated is expected on plastics, provide at a high speed, the large area electron system.

In a word; Utilize high-quality, body single-crystal wafer, the GaAs line with integrated ohm contact of use " top-down " technology manufacturing provides high-performance " can print " semi-conducting material and a kind of easy relatively approach that on flexible plastic substrate, realizes transistor, diode and integrated gate is provided.High temperature processing step (the for example formation of ohm contact) is come the very orderly GaAs linear array of trans-printing from the separation and the use PDMS die of plastic substrate, is the key feature of method described herein.Concerning the speed of service has the large tracts of land print electronic devices of requirement, is attractive with the GaAs line as semiconductor, because (i) GaAs has high intrinsic electron mobility (about 8500cm for those ²V ^-1s ^-1) and in the high-frequency circuit of routine, set up application; The MESFET that (ii) makes up with GaAs provides than MOSFET and has more simply handled; Because MESFET does not need gate insulator; (iii) GaAs MESFET does not receive in the puzzlement of the parasitic overlapping ability that non-auto-collimation MOSFET takes place, even (iv) under limited other composition registration of level that can obtain easily on the large tracts of land plastic substrate and resolution, can realize the high-speed cruising among the GaAs MESFET yet.The cost that GaAs is high relatively (than Si) and be difficult to utilize GaAs to produce complementary circuit shows some shortcomings.Yet; On plastic substrate, make up the relatively easy property of high-performance transistor and diode; And the ability in the functional circuit of integrating these components to indicated this method to be expected to be used for requirement mechanical suppleness is arranged, light structures and can with the compatible electronic system of processing large-area, similar printing.

Experimental section: ((carrier concentration is 4.0 * 10 to the GaAs wafer PA) to have a n type GaAs layer through the epi dopant Si of the molecular beam epitaxy in the high vacuum chamber (MBE) deposition growing on (100) Semi-insulating GaAs wafer for IQE Inc., Bethlehem ¹⁷Cm ^-3).This lithographic process has adopted AZ photoresist (being respectively applied for AZ5214 and the AZ nLOF 2020 of positive and negative imaging), this be with the temperature of plastic substrate compatibility under (＜110 ℃) carry out, this plastic substrate is and is coated with (cured) polyurethane (PU that handled; NEA 121, Norland Products Inc., Cranbury; NJ) PET (PET of about 175 micron thick, polyester film, Southwall Technologies; Palo Alto, CA) plate.GaAs wafer with photoresist mask pattern is at etchant (4mL H ₃PO ₄(85wt%), 52mL H ₂O ₂By etching anisotropically, said etchant cooled off in ice-water bath (30wt%), and the 48mL deionized water).All these metals are by the speed evaporation of electron-beam evaporator (Temescal) with about 4A/s.When having deposited the thick metal of 50nm, this evaporation apertures (os) quits work, and prevents the plastic substrate fusing with cooling sample (5min).After the sample cooling, repeated evaporation/cool cycles is with the more metals of deposition.

Embodiment 2: the transistorized gigahertz operation of the mechanical flexibility on the flexible plastic substrate

The GaAs line is used in combination with ohm contact that forms from body wafer, soft lithographic plate trans-printing technology; And the device design of optimizing can be formed on the low-cost plastic substrate mechanical flexibility transistor, and its each device rate is in the gigahertz scope and the mechanical flexible ability with height.Method disclosed herein is included in to be manufactured in the simple layout has the material that limited lithographic plate image forms resolution and registration.This embodiment has described transistorized electricity of high-performance and mechanics characteristic.These results are very important in some applications, and these application include, but not limited to high-speed communication and calculating, and the emerging type of large area electron system (" grand electronic equipment ").

The large area flexible electronic system (being grand electronic equipment) that is formed by high mobility semiconductor is attractive, because potential application requirements high-speed communication of some of these circuit and/or computing capability.(TFT shows that the mobility than polycrystalline organic film is (common＜1cm to the flexible thin-film transistor that various inorganic material utilization such as amorphous/polycrystalline oxide and chalkogenide, polysilicon and monocrystalline silicon nano line and the micro-structural band make up ²V ^-1S ^-1) higher mobility (10～300cm ²V ^-1S ^-1).Work before is verified, has very high intrinsic electron mobility (about 8500cm ²V ^-1S ^-1) monocrystalline GaAs linear array, in the arrangement (geometry) of metal-semiconductor field effect transistor (MESFET), can work to be used for the transmission channel of TFT.This embodiment is presented under the optimal design, and similarly equipment can be operated under the frequency in GHz zone, even has limited lithographic printing resolution, and has good flexible ability.Particularly; Experimental result shows on the plastic substrate to be that 2 microns transistor shows cut frequency and is higher than 1.5GHz based on the MESFET of GaAs line for grid length; And when using the thick substrate of about 200mm, radius bend is during to about 1cm, and its characteristic electron has limited change.Simple analog and experimental observation to equipment performance meet very much, and can obtain the running frequency of S-frequency band (5GHz).

Should make policy class basically and be similar to the described strategy in other places, but have the equipment geometry and the processing method of optimization, can realize high-speed cruising.Has integrated ohm bar (through at N ₂Under the atmosphere, 120nm AuGe/20nm Ni/120nm Au annealing was formed in 1 minute at 450 ℃) GaAs line (about 2 microns of width) array come from having the manufacturing of 150nm n-GaAs epitaxial loayer (100) Semi-insulating GaAs (SI-GaAs) wafer through the chemical etching of photoetching and anisotropy.Depositing Ti (2nm)/SiO on the GaAs line at the quarter end ₂(50nm) bilayer is handled to promote trans-printing as adhesion layer, and the pollution of the organic substance (mainly being the organic substance that shifts from stamp surfaces) that relates in not handled with ohm contact of the flat surfaces of protective wire.Through these samples being immersed 1: 10 HF solution removing this layer, in step subsequently, the clean surface exposure of GaAs line is used for device fabrication.In addition, this Ti/SiO ₂Thin thickness (in trans-printing, being used as the thickness of the photo-induced etching agent of adhesion layer in the work before us) causes plastics PET (PET) plate on relatively flat surface; Down auxiliary at the polyurethane (PU) of skim spin coating, printing GaAs linear array on said plate.This improved surface flatness make can deposit narrow gate electrode and vertically do not have the crack, thereby a kind of approach of the speed of service of effective increase equipment is provided.

The on-chip MESFET of PET (seeing that grid length is 2 microns a general transistorized SEM image, shown in Fig. 7 A) that is positioned at that is obtained shows and is structured in DC transmission characteristic like the transistor-like on the parent crystal sheet.Fig. 7 B has shown to grid length to be 2 microns equipment, the electric current (I between source electrode and the drain electrode _DS) as grid voltage (V _GS) (vignette) function with at different V _GSFollowing function as source/drain voltage.V _DSFor the voltage of nipping off of 0.1V place (being the range of linearity) is-2.7V.The ON/OFF current ratio of confirming according to the average measurement value on many equipment is about 10 ⁶These equipment are showed negligible hysteresis (vignette), and this is a particular importance for high-speed response.These equipment demonstrate the consistency of good device-to-device (device-to-device); Form 1 has been listed the statistics (number of devices＞50) of the MESFET of passage length with 50 microns and different grid length.This DC characteristic almost is independent of grid length, except the equipment list with big grid length reveals low slightly ON/OFF ratio.Yet, to describe as following, this grid length plays the part of a pivotal player when confirming running frequency.

The statistics of the parameter that form 1 extracts from the MESFET with different grid lengths

* all crystals pipe is made up of the GaAs line of 10 parallel connections, and its passage length is 50 μ m.

The vignette of Fig. 8 A has shown the layout of the equipment that designed to be used microwave test.Each unit of this test structure comprises two identical MESFET; This MESFET grid length is that 2 microns and passage length are 50 microns; These two MESFET have a public grid, and detection pad (pad) is configured to mate with the layout of RF probe.In measurement, drain electrode (D) end remains on 4V (with respect to source electrode (S)) and grid (G) and is driven by the bias voltage of 0.5V, and to be coupled with the equivalent voltage amplitude be 224mV, have the RF power of the 0dB of 50 Ω.This measurement utilizes HP8510C Network Analyzer to carry out, and utilizes standard SQL T (Short-Open-Load-Through) technology to go up at CascadeMicrotech 101-190BISS substrate (a slice is coated with the ceramic chip of the golden pattern of laser reconditioning) and through WinCal3.2 this HP8510C Network Analyzer is calibrated for error in 1GHz at 50MHz.In other words, short calibration (short calibration) is considered to be desirable short, and open calibration (open calibration) is considered to be desirable opening.Need not further remove to embed (de-embedding) owing to accomplish this calibration, so the reference planes of measuring are arranged between input probe and the output probe.In other words, these parasitic element on the contact mat are included in the measurement.Yet, consider that frequency is that the wavelength of the RF signal of 1GHz is 300mm, and the length of contact mat being 200 microns the fact, these parasitic element can be ignored the influence of contact mat.Because contact mat closely is 1/1500 of a wavelength, so the impedance conversion effect of this contact mat is negligible.

This small signal current gain (h ₂₁) can extract from the S-parameter of this measured equipment.This amount shows that the signal to the RF signal of input has logarithm dependence (Fig. 9 A).This cell current gain frequency (f _T) be restricted to short-circuit current gain and become 1 o'clock residing frequency.This amount can intersect confirm through the x axle of according to least square fitting 20dB/decade line the curve of Fig. 9 A being extrapolated and find out it.The value of confirming by this way is f _T=1.55GHz.As far as we know, this equipment has been represented the fastest transistor with mechanical flexibility and the f on the plastics _TBe in first transistor in gigahertz zone.We are basis and small-signal equivalent circuit model also, utilizes the electric capacity between DC parameter of being surveyed and the electrode that is calculated to estimate that the RF of GaAsMESFETD responds.F according to the figure and the experimental result gained of analog result gained _T=1.68GHZ conforms to very much.This model also is applicable to the transistor with different grid lengths well, and for example, grid length is the experiment f of 5 microns MESFET _T(730MHz) with the simulation gained amount (795MHz) near (Fig. 9 B).In this model, only considered the intrinsic parameters of MESFET, because extrinsic parameter (promptly relevant with surveying pad inductance and impedance) is considered to insignificant.Mutual conductance (g _m), output impedance (R _DS) and charging resistor (R _i, explained that the electric charge on the passage can not respond V instantaneously _DSThe fact of variation) can extract from the DC measurement result.The intrinsic capacity relevant with this MESFET comprises the contribution from damping layer, edge and how much edge capacitances.Wherein each all utilizes and is used for that channel width is equaled the equality that the conventional equipment of the summation width of single GaAs line calculates and calculates.The electric capacity of damping layer is with grid length (L _G), effectively plant width (W) and decay highly characterize:

( H depletion = ( 2 &epsiv; r &epsiv; 0 q N D ) ( kT q ) ( ln N D N i - 1 ) )

In this equality:

C depletion = &epsiv; r &epsiv; 0 L G W H depletion

Suppose that wherein damping layer comes work as a parallel plate capacitor.This edge capacitance (edge fringing capacitance) and geometry edge capacitance (geometricfringing capacitance) respectively by:

C edge = ( &epsiv; r &epsiv; 0 W ) ( 1.41 + 0.86 &epsiv; 0 &epsiv; r &epsiv; 0 )

With

C geometric = [ &epsiv; r W + &epsiv; 0 ( 150 &mu;m - W ) + 200 &mu;m ] ( K ( 1 - k 2 ) 1 / 2 K ( k ) )

Confirm.150 μ m and 200 μ m are respectively the width and the length of source electrode or drain pad.K (k) be first kind ellptic integral and

k DS = [ 2 ( L S + L DS ) L DS ( L S + L DS ) 2 ] 1 / 2

With

k GS = k GD = L GD L GD + L G &CenterDot;

C _GS, the electric capacity between grid and the source electrode comprises all these three kinds of electric capacity; And C _DSAnd C _DGInclude only edge capacitance and geometry edge capacitance.As a rule, C _EdgeAnd C _GeometricContribution can be left in the basket, and analog result is not had appreciable impact because they much smaller than with the proportional C of grid length _DepletioThis specification of a model the performance of the linear array equipment on the plastic plate, comprise f _TVariation with grid length.Fig. 8 C will have (symbol) surveyed and (dotted line) f that is calculated of the GaAs-line MESFET of different grid lengths and 50 microns passage lengths _TCompare.This model indication is through reducing grid length or can obviously increasing f through the layer design in the further optimization GaAs parent crystal sheet _TValue.

We have reported that tension stress is 15 microns the influence based on the MESFET of line to grid length.In this embodiment, our examination is in pressure and the performance that is in the high-speed equipment in the stretching, and this pressure and pulling force are up to snap point.This measurement result comprises whole DC electrology characteristics, is as substrate being bent to the spill with different curvature radius and the function of convex shape (see figure 9).This bending radius is extracted through the side elevation image of crooked sample is carried out geometric fit.Spill and convex bending surface produce tension stress (be assigned with on the occasion of) and compression (being assigned with a negative value) on equipment.Utilize the stress of estimating to cause with the similar equipment of Fig. 8 A apparatus shown to Effect on Performance by bending.Along with tension stress is increased to 0.71% (bending radius corresponding to 200 used in this work micron thick substrates is 14mm), this saturation current (is V _DS=4v, V _GS=0V) increasing about 10% and along with compression is increased to 0.71%, this saturation current reduces about 20% (Fig. 9 B).When after this substrate is bending towards arbitrary direction bending, being released, this electric current recovers, thereby the distortion of expression plastic substrate and these other assemblies of equipment is flexible in this zone.(estimating that PET and PU at stress＞about 2% place plastic deformation take place).To Ga _xIn _1-xGa on As or (100) GaAs wafer _xIn _1-xThe research that receives the stress upper strata of As shows that biaxial stress and the outside uniaxial stress (this situation and present embodiment are similar) that applies can cause the remarkable drift and the valence band division of band-gap energy in the upper strata.Tension stress reduces band-gap energy, thereby increases total carrier concentration (electronics and hole) and improve electric current.On the contrary, compression has increased band-gap energy and has reduced electric current.These phenomenons are consistent with our observed result of equipment.In site measurement imaging utilizing the SEM microscope to BENDING PROCESS has confirmed do not have the GaAs thread breakage at stress＜+/-0.71% place.In tension stress is about 1% when above, because some lines fracture (or crack of gate electrode), decline appears in equipment.Than wideer line used herein (for example, 10 microns wide), because their higher relatively bending rigidities, line separates from plastics for those width, with the crooked pressure of release tension stress, rather than fractures.

Because bending stress is less than 20% to the change of saturation current, so the variation of ON/OFF ratio is mainly confirmed by closing change in current.The dislocation of the variation of valence band holes concentration and the n-GaAs layer that caused by stress and the number of blemish possibly close change in current to transistor has contribution.Tension stress and compression both can increase the number of dislocation and blemish, thereby increase the pass electric current of this equipment.Tension stress produces additional hole and electronics, and this also increases the pass electric current.On the other hand, compression reduces hole concentration.As a result, the pass current ratio that can estimate to be in the MESFET in the pulling force do not have strain equipment want high.Compression has side effect to the pass electric current of equipment.Therefore, corresponding ON/OFF current ratio will reduce under pulling force, and under pressure, remain unchanged basically.Fig. 9 C has provided the dependence of surveying ON/OFF current ratio counter stress in the zone of saturation, shows and qualitative meeting discussed above.

In a word, the result of this embodiment shows that the surface stress (in pulling force and pressure, up to 0.71%) that is caused by bending does not have the significantly performance of decay next MESFET by the technology manufacturing of revising.The more important thing is, under case of bending, discharge sample and make equipment performance return to its reset condition.These observations have been indicated at the suprabasil MESFET based on the GaAs line of PU/PET has the mechanical performance of the requirement of the grand electronic apparatus application that meets a lot of anticipations.In addition, the TFT of these types shows high speed, these speed approach that those are suitable for the RF communication equipment and be suitable for that other requirements have mechanical suppleness, light structures and with large tracts of land, be similar to the speed of the compatible application of the processing of printing.For use be this job spotlight thin, flexible, have equipment proper density and the line or belt large-area circuits type; Some shortcomings of GaAs (are that the wafer cost is high with the Si that is used for custom integrated circuit; Can not make up reliable complementary circuit; Mechanically frangible etc.) compare, just had only lighter importance.

Intensive correlation properties (Confinement-related properties) and widely used form factors (form factors) make that low-dimensional materials are expected to new application is arranged in electronics, photonic propulsion, micro-electromechanical system and other field.For example, high-performance flexible electronic equipment (for example transistor, sampler element etc.) can be constructed through the micro-/ nano line, band or the pipe that use those to be placed in, to be coated in or to be printed on the plastic substrate.Approach, the high aspect ratio material structure make material in single-crystal semiconductor material, have crooking ability and, under some version, have stretch capability, these materials were frangible and fragile originally in body.The result; The semi-conducting material of these types provides the attractive of vacuum and the accessible polymerization of solution/amorphous organic material has been substituted, and the accessible polymerization of these vacuum and solution/non-is showing obviously lower performance usually through organic material aspect the carrier mobility.The top-down approach of describing recently produces semiconductor line, band and plate from the silicon substrate material source.This method provides the height control of geometry, spatial organization, doped level and material purity to resultative construction.Yet the economic attractiveness of this method particularly for those application that needs large tracts of land to cover, receives the restriction of wafer (SOI, the epitaxial loayer on the growth substrate etc.) unit are cost.

In this embodiment, we have reported a kind of diverse ways.Particularly, we have provided a kind of thin-film transistor (TFT), and this TFT uses the silicon ribbon collimation array of the sub-micron thick of obtaining from body silicon (111) wafer cheaply.We begin to describe make these structures and with them through the technology of boxing impression trans-printing to the plastic substrate.We have provided the architectural feature of the shape of these bands, their thickness and configuration of surface.The electrical measurement that the Schottky barrier TFT that is formed by these printer belts is done shows that it is 360cm that the band of these printings has n type field-effect mobility ²V ^-1s ^-1And the ON/OFF ratio is 4000.

Figure 10 diagram a kind of surface from Si (111) wafer (Montco, Inc., n type, 0.8-1.8 Ω .cm) produce the method from top to bottom of the band of thin (＜1 micron).The phase shifting mask photoetching begins this method from the near field ¹³, then be metal-stripping and SF ₆Plasma etching (Plasmatherm RIE system, 40sccm SF ₆, 30mTorr, 200W RF power, 45 seconds), be about 1 micron to produce deeply on the Si surface, wide is the array (Fig. 1 (a)) of 1 micron raceway groove.Spacing between the raceway groove defines the width (being generally 10 microns) of band.Then, under 1100 ℃ on wafer the growth 100nm thermal oxide.Through two metal deposition step that angled electron beam evaporation Ti/Au (3/30nm) carries out, provide part to cover (Figure 10 B) to the raceway groove side.These cast the thickness that " covering " limits band during angled evaporation.The extent control of the condition of channel etching, evaporation angle and metal flow collimation this scope of covering, and the thickness of therefore having controlled band.CF ₄Plasma etching (40sccmCF ₄, 2sccm O ₂, the 50mTorr basic pressure, 150W RF power 5min) is removed the oxide of exposure.At last, (mass ratio is 3: 1: 1 H to carve these bands at the bottom of the hot KOH solution ₂O: KOH: IPA, 100 ℃).Etch front is carried out along < 110>direction, and keeps (111) plane (Figure 10 C) and form the band that those nothings that accounted for former wafer most of (75-90%) exist with supporting.Etching mask is designed to make each to be with in the end of raceway groove anchor (Figure 12 A and Figure 12 B) to wafer.Utilize the KI/I in the water ₂(2.67/0.67wt%) remove this mask, and continue, should make thereby accomplish with HF.The band that produces by this way is that approach, smooth and is (Figure 10 E) of mechanical flexibility, describes the method for having utilized expensive silicon-on-insulator wafer before using with those ^5,7,11Being with of producing is similar.The thickness that AFM (Figure 11 A) shows general band from about 115 to about 130nm.These variations are shown as slight color change in light micrograph (Figure 12 E).Is 0.5nm like AFM to one of them the measured roughness in 5 μ m * 5 μ m zone of downside that is presented in the band among Figure 12 B.This value is greater than top polished surface (0.12nm) or greater than the downside (0.18nm) that adopts same procedure from the band of soi wafer generation.Interesting is to adopt other anisotropic etching agent to reduce this roughness.Varied in thickness and, in small range, the source of roughness partly is the edge roughness in the raceway groove, it so that cause the roughness in the passivation of side in the angled evaporation process.The thickness that raising side quality can reduce band rises and falls.Yet, shown in following, utilize those bands of technology manufacturing described herein can construct transistor arrangement with superperformance like us.

Through the printing treatment of high (＞95%) productive rate, can band be transferred on another (flexibility) substrate, like the sketch map that Figure 12 gave.In order to carry out this printing treatment, the PDMS die rolled on this silicon chip and then shell back fast, to obtain this band again.This processing depends on the dynamics Controlling to the adhesion of this die.This die, quilt " soaking " like this, (Figure 12 B and 12E) can print these bands through contacting with another substrate.Be printed onto a thick on-chip band of PET of 0.2mm that is coated with ITO and can be used on plastics, making high performance flexible bottom gate TFT, wherein ITO is as gate electrode.One deck SU-8 that before printing, deposits on the ITO grid plays gate dielectric and promotes band to shift as a kind of adhesive.In printing process, these bands immerse the SU-8 that did not handle, and make their top imbed the adhesive surface, between basal surface of being with and ITO, stay about 2 microns medium.By offset printing (100 μ m long * 100 μ m wide) and utilize HF/H ₂O ₂Ti source electrode and the Schottky barrier contact of drain contact formation source electrode and drain electrode of wet etching thick (the about 0.2 μ m) that limit.These bottom gate equipment demonstrate distinctive n type enhancement mode MOSFET grid modulation.Transistor obtains about 103 ON/OFF ratio, and the equipment level mobility, and as using normal equation determined to mos field effect transistor, 14 up to about 360cm ²V ^-1s ^-1(linear) and 100cm ²V ^-1s ^-1(saturated, as to estimate) at the Vd=5V place.The mobility of this band itself should be than the high about 20% (440cm of equipment level mobility ²V ^-1s ^-1Linear, and 120cm ²V ^-1s ^-1Saturated) because the spacing between them makes them only fill about 83% passage.For the thick substrate of 0.2mm, when substrate bent to limited radius (15mm), this carrying device can be intact, but in more sharp-pointed bending (5mm), decline seriously.

In a word, this embodiment has confirmed a kind of manufacturing strategy that is used for can printing from the generation of body silicon (111) wafer monocrystalline silicon zone of high yield.After making, the body wafer surface is made with extra care feasible can repeatedly the repetition, thereby can produce tens or even up to a hundred square feet band from one square feet initiation material.The TFT that makes from these bands on the plastics has confirmed that they are as the semi-conductive application of high-performance flexible.These equipment and the strategy of making them not only can be used for the large area flexible electronic equipment, can also be used for needs three-dimensional or isomery integrated or utilize the application of other characteristic that is difficult to obtain under the little preparation method of conventional silicon.

In in the past several years of the flexible large-area electronics equipment that is comprised in the emerging grand electronic device field, technology witness considerable progress; And have several main users and have military application; In the near future, they are expected to by commercialization.Microelectronic circuit with novel form factor is the critical component of these systems, and possibly need new manufacturing approach (particularly printing process) to make them.Owing to this reason, but existing a large amount of attentivenesss put in the semi-conductive printing form, and organic (for example benzene, polythiourea etc.) and inorganic (such as polysilicon, inorganic nanowires) material are all examined or check.This work has demonstrated very good result some equipment on being integrated in plastic substrate.Yet the current range of application but receives the restriction by the congenital bad performance of the equipment of semiconductor fabrication, and its inborn bad performance is such as them low effective equipment mobility and running frequency.We have examined or check a kind of new model that is called as micro-structure semiconductor (μ S-Sc) can print inorganic semiconductor, its can routine with the organic polymer substrate on realize to make unusual high-performance equipment.We also illustrate, and use μ S-Sc as the basis, can on semiconductor wafer, prepare the equipment of exploitation fully, and will transfer on the flexible substrate subsequently, and not reduce their performance.This method is utilized the high-quality of wafer level semiconductor, but makes them can be obedient to the manufacturing approach based on printing.In these materials, monocrystalline μ s-GaN has very big attraction, because he has superior material property, comprises wide band band gap (3.4eV is to the 1.4eV of GaAs), thereby causes high breakdown electric field (3MV cm ^-10.4MV cm to GaAs ^-1), high saturated carrier velocity (2.5*10 ⁷Cm s ^-1To 10 of GaAs ⁷Cm s ^-1), and good thermal conductivity (1.3W cm ^-10.5W cm to GaAs ^-1).In addition, the integrated generation of heterojunction with AIGaN/GaN heterojunction structure form has high conduction band offset and piezoelectric response, and surperficial carrier density is positioned at 1.0 * 10 ¹³Cm ^-2The equipment attenuating material of scope.These attractive characteristics make GaN be suitable for those requirements to be had in the equipment of high-frequency and high power performance, such as the electronic equipment that is used for radio communication, full-color light-emitting equipment and the UV photodetector that is used for electro-optical system.

Since confirming the HEMT (HEMT) of AlGaN/GaN for the first time, existing a lot of basic research activities focus on this field.These effort have impelled equipment to be integrated on the various substrates, and these substrates comprise sapphire, SiC, Si and AlN.In this embodiment; We describe flexible AlGaN/GaN heterojunction structure HEMT (HEMT; Figure 14 summary shows this technology) manufacturing, some transistors wherein are processed and through the scheme (protocol) based on contact print its Si from them (111) growth substrate are transferred on the plastic plate subsequently.This work provides the description that will be integrated into technology on the plastic substrate based on the high-performance HEMT equipment of the III-V semi-conducting material of heterostructure.

Figure 15 schematically diagram be used for the step of HEMT equipment.This process starts from utilizing standard sequence photoetching and strip step on body GaN heterostructure wafer, to form ohm contact (Ti/Al/Mo/Au) (Figure 15 A).Deposit PECVD oxide layer and Cr metal then, with as the mask of dry etching subsequently.Photoetching and etching to Cr and PECVD oxide define GaN with required geometry, and these bands are used as solid ink (Figure 15 B) in printing subsequently.After peelling off the photoresist at top, utilize the ICP dry etching to remove the GaN of exposure (Figure 15 C).Remove this Cr layer through this ICP etch step, but thicker PECVD oxide layer is stayed the top of GaN basically intactly.Utilize the anisotropy wet type etching (Figure 15 D) of tetramethyl ammonium hydroxide (TMAN) to remove the Si below being positioned at and separate the GaN band from female substrate.In this highly basic etching process, the PECVD oxide plays the unabated effect of protection ohm contact., then utilize BOE (buffer oxide etching agent) treatment step to be removed by the residue PECVD oxide of plasma and the serious roughening of wet etching step.Subsequently through electron beam evaporation with the top of new smooth, a sacrificial silicon oxide deposition to the GaN band.Printing to GaN contacts (Figure 15 E) with this wafer with dimethyl silicone polymer (PDMS) plate, and this plate is removed from female substrate fast, obtains the fully transfer of μ s-GaN to PDMS with this.The plate that is somebody's turn to do " by soaking " is then rolled on the PET that scribbles polyurethane (PU) (PET) plate (Figure 15 F), and begins from the top side, utilizes UV light to handle PU (Figure 15 H).Peel off PDMS and realize of the transfer of μ s-GaN element to plastic substrate.This transfer has stayed remaining PU at GaN band top.When utilizing BOE to peel off the SiO of the electron beam deposition that evaporates in the step of Figure 15 E ₂During layer, these remnants are removed.The final step of this processing comprises that forming source/drain connects and conductivity gate metal contact (Ni/Au), comes the layer (Figure 15 F) of composition through the electron-beam evaporation and the lift-off processing of the standard of use.

In order to keep not having the home position of the μ s-GaN that supports the ground existence behind the Si below removing (Fig. 1 d), we have adopted the new geometry of the micro-structure semiconductor (μ s-Sc) shown in the listed processing of Figure 14.This μ s-GaN band has two narrow bridges (promptly two split off a little, shown in the arrow of Figure 14 C) at the end of GaN, to help that PDMS printing equipment (Figure 15 E) is transferred in they adjustment.This structure goes out significant improvement with respect to " peanut " design expression of reporting before.Under this design, find to cause that fractureing of transfer processing is very effective.Than " peanut " design demand early etch period is carried out strictness optimization and requires etching speed height unanimity in large tracts of land, the μ s-Sc that is suitable for printing with generation is with.Current " narrow bridge " design is not very sensitive to etching speed difference.For a situation after the diagram, Figure 16 A and 16B have shown respectively before TMAH anisotropic etching step and the GaN wafer optical imagery of getting afterwards.In these figure, be easy to discern and do not have the different color of supporting and being supported the GaN micro-structural.Figure 16 C and 16D have shown the scanning electron microscope image of being got in the TMAH etch step interstage of the Si below cutting (SEM).The dashed region of the enlarged image of Figure 16 D and Figure 16 B has explained that effectively the Si etching process is basically only along the height anisotropic nature of transmitting perpendicular to the direction of GaN band orientation.In this special system, preferential etching is to take place along (110) direction; Si (111) surface, shown in Figure 14 C, as intrinsic etching isolation mask.Figure 16 E has shown the SEM image of the PDMS plate that was soaked, and the full tension force (full-tension) that wherein is utilized in its wafer registration shifts μ s-GaN.The image of Figure 16 F has shown the SEM micro-image that is printed structure, and wherein, last step is for to transfer to μ s-GaN heterojunction structure equipment on the PU that is coated with the PET substrate.These images have confirmed not damage the heterojunction structure band based on the transfer of the μ s-GaN figure of " narrow bridge ".

Figure 17 A and 17B have provided the representative optical imagery of HEMT after transferring on the PET substrate based on μ s-GaN.Various contrasts are corresponding to the various compositions (lend) of the equipment schematic cross-sectional shown in Figure 14 B.In this geometry, the control that active electronic passage (active electronchannel) is formed between two ohm contacts (Ti/Al/Mo/Au) and electronics flow velocity (or electric current) is contacted by Schottky (Ni/Au) grid.Passage length, channel width and the grid width of Figure 17 B apparatus shown is respectively 20,170 and 5 microns.To handle little fill factor (filling factor) restriction that caused by the side wet etching different with before μ s-GaN; The fill factor that these equipment are corresponding is very high, than the report of early the III-V structure as far as printing (67% couple of μ s-GaAs 13%).Figure 17 C has shown typical drain current-voltage (I-V) characteristic by the GaN HEMT equipment of plastic support; This grid is biased to 1V with step-length 1V from-3V.This equipment is that 1V and drain bias are that the 5V place shows the about 5mA of maximum drain current in grid bias.Figure 17 D has shown at constant drain voltage (V _d=the transmission characteristic that records under 2V).This equipment list reveals-threshold voltage (V of 2.7V _Th), 10 ³ON/OFF than and the mutual conductance of 1.5mS.But before shifting, have same geometry the mutual conductance of GaN HEMT have the mutual conductance of 2.6mS.This transfer process is rendered as and makes this value reduce about 38%.

The crooked stage of use is studied the mechanical suppleness of GaN HEMT, like Figure 18 A, shown in Figure 18 B.Figure 18 B has shown a series of transfer curves of surveying as the function of bending radius (and corresponding stress).When radius bend was arrived 1.1cm (corresponding to the stress of 0.46% magnitude), we observed the highly stable response in mutual conductance, threshold voltage and the ON/OFF ratio of being surveyed.Figure 18 C shown a sequence the maximum stress place with discharge current-voltage (I-V) curve that latter two position of this stress records.As mentioned above, the influence of being found is relatively limited, and seen little difference shows that μ s-GaN HEMT equipment is not damaged by the bend cycles of rigidity between three I-V curves of Figure 17 B and Figure 18 B.

In a word, this embodiment has described a kind of being suitable for and has been printed onto the processing on the plastic substrate with the high-performance GaN HEMT of flexible form.We have further confirmed a kind of effective μ s-Sc geometry that helps the trans-printing scheme, and the intellectual material strategy that is used for removing through anisotropy wet type etching sacrifice layer.Our result shows that μ s-GaN technology provides significant chance for the of future generation grand electronic equipment of exploitation such as high-performance mobile computing and high-speed communication system.

Method: the heterojunction GaN on silicon (100) wafer (Nitronex) goes up and makes the GaN micro-structural, and this GaN micro-structural is made up of three layers of III-V semiconductor: AlGaN layer (18nm does not mix); GaN resilient coating (0.6 micron is not mixed); And AlN transition zone (0.6 micron).Use AZ 5214 photo-induced etching agents, open ohm voltage contact area and utilize O ₂Plasma cleans this exposed region.(Plasmatherm, 50mTorr, 20sccm, 300W, 30 seconds).In order to obtain low contact resistance, before metallization step, utilize the SiCl in the RIE system ₄Plasma carries out preliminary treatment to ohm voltage contact area.Depositing Ti/Al/Mo/Au (end of to top 15/60/35/50nm) metal level then.Utilize electron beam evaporation to come depositing Ti, Al and Mo, and deposit Au with thermal evaporation.Utilize lift-off processing to limit these contacts.These contacts are using N ₂For annealing 30 seconds down at 850 ℃ in the rapid thermal annealing system of surrounding environment.This PECVD oxide (Plasmatherm, 400nm, 900mTorr, 350sccm 2%SiH ₄/ He, 795sccm NO ₂, 250 ℃) and the Cr metal (electron beam evaporation, 150nm) layer is deposited as being used for the mask material of ICP etching subsequently.Photoetching, wet etching (Cyantek Cr etching agent) and RIE handle ((50mTorr, 40sccm CF ₄, 100W 14min) defines the geometry of GaN.After utilizing acetone to remove photo-induced etching agent, utilize ICP dry etching (3.2mTorr, 15sccm Cl ₂, 5sccm Ar ,-100V bias voltage 14min) is removed the GaN of exposure, and (Aldrich, 5min) etches away following silicon by 160 ℃ then to utilize TMAH wet etching solution.This sample is immersed BOE (NH ₄F: HF is 6: 1) continue 90 seconds, to remove the PECVD oxide and to be with napex newly to deposit the SiO of the electron beam evaporation of 50nm at GaN ₂Then with the contact of this GaN wafer and PDMS plate (Sylgard 184, Dow corning), then with this PDMS plate with＞0.01ms ^-1Peeling rate peel off to fetch these μ s-GaN elements.The PDMS plate that is soaked with μ s-GaN is rolled then on the PET plate (PET, 100 microns of thickness, Glafix Plastic) that is coated with polyurethane (PU, Norland optical adhesive, No.73)).Begin the sample exposure at UV light (the active mercury lamp 173 μ W cm of the ozone of family expenses from the top ^-2) under, to cure PU.Shelled back PDMS in 30 seconds and the electron beam oxide is removed through in BOE, soaking, can realize μ s-GaN element is transferred on the plastic substrate.The negative photo-induced etching agent (AZ nLOF2020) of use comes the pattern of composition Schottky voltage contact area and then utilizes electron beam evaporation to deposit Ni/Au (80/100nm) layer.Utilize lift-off processing and combine AZ remover (KWIK continues 5 hours) to remove this PR.

The picture of the collimation array that four layers of Si (111) that Figure 21 provides (a) that big specification is provided are with.(b and c) overlooks the SEM image and the SEM image of the angled observation of the four layers of Si (111) shown in (d and the e) figure (a) for four layers of Si (111) of figure shown in (a).

Figure 22 provides the photograph (a) and the OM image (b and c) of flexible Si (111) band that discharges.(d to f) is the SEM image of the band shown in (a).

The optical imagery that the Si (111) that Figure 23 provides (a) to transfer to the on-chip collimation of PDMS is with.(b) for coming from the afm image of four bands in the array shown in the figure (a).(c) lay the picture of flexible polyester film of Si (111) the array pattern of four shifting science and technology in four directions circulations that come from single Si sheet.

Reference

a)?Y.Xia，P.Yang，Y.Sun，Y.Wu，B.Mayers，B.Gates，Y.Yin，F.Kim，H.Yan，Adv.Mater.2003，15，353.b)?C.M.Lieber，Mater.Res.Soc.?Bull.2003，28，486.c)?M.C.McAlpine，R.S.Friedman，C.M.Lieber，Proc.IEEE2005，93，1357.d)M.Law，J.Goldberger，P.Yang，Ann.Rev.Mater.Res.2004，34，83.e)P.Yang，Mater.Res.Soc.Bull.2005，30，85.f)?Z.R.Dai，Z.W.Pan，Z.L.Wang，Adv.Funct.Mater.2003，13，9.g)special?issue?on?nanostructured?advanced?materials，Pure?Appl.Chem.?2002，74(9).

a)L.A.Bauer，N.S.Birenbaum，G.J.Meyer，J.Mater.Chem.2004，14，517.b)?Y.Cui，Q.Wei，H.Park，C.M.Lieber，Science?2001，293，1289.

Z.Tang，N.A.Kotov，Adv.Mater.2005，17，951.

X.Duan，C.Niu，V.Sahi，J.Chen，J.W.Parce，S.Empedocles，J.L.Goldman，Nature?2003，425，274.

R.S.Friedman，M.C.McAlpine，D.S.Ricketts，D.Ham，C.M.Lieber，Nature?2005，434，1085.

E.Menard，K.J.Lee，D.-Y.?Khang，R.G.Nuzzo，J.A.Rogers，Appl.Phys.Lett.2004，84，5398.

a)S.Mack，M.A.Meitl，A.Baca，in?preparation.?b)?Y.?Sun，S.Mack，J.A.Rogers，Proc.Intl.Electron?Device?Meeting?(IEEE)，2005，in?press.

a)?E.Menard，R.G.Nuzzo，J.A.Rogers，Appl.Phys.Lett.2005，86，093507.b)Z.-T.Zhu，E.Menard，K.Hurley，R.G.Nuzzo，J.A.Rogers，Appl.Phys.Lett.2005，86，133507.

a)Y.Sun，J.A.Rogers，Nano?Lett.?2004，4，1953.b)?Y.Sun，D.-Y.Khang，F.Hua，K.Hurley，R.G.Nuzzo，J.A.?Rogers，Adv.Funct.Mater.2005，15，30.

Y.Sun，S.Kim，I.Adesida，J.A.Rogers，Appl.Phys.Lett.2005，87，083501.

Y.Sun，H.-S.Kim，E.Menard，S.?Kim，G.Chen，I.Adesida，R.Dettmer，R.Cortez，A.?Tewksbury，J.A.Rogers，Appl.Phys.Lett.，submitted.

R.H.Reuss，B.R.Chalamala，A.Moussessian，M.G.Kane，A.Kumar，D.C.Zhang，J.A.Rogers，M.Hatalis，D.Temple，G.Moddel，B.J.Eliasson，M.J.Estes，J.Kunze，E.S.Handy，E.S.Harmon，D.B.Salzman，J.M.Woodall，M.A.Alam，J.Y.Murthy，S.C.Jacobsen，M.Olivier，D.Markus，P.M.Campbell，E.Snow，Proc.IEEE2005，39，1239.

D.C.Duffy，C.McDonald，O.J.A.Schueller，G.M.Whitesides，Anal.Chem.1998，70，4974.

S.M.Sze，Semiconductor?Devices，Physics?and?Technology(Wiley，New?York，1985).

G.Eftekhari，Phys.Status?Solidi?A-Appl.Res.1993，140，189.

H.-I.Chen，C.-K.Hsiung，Y.-I?Chou，Semicond.Sci.Technol.2003，18，620.

S.Forment，M.Biber，R.L.van?Meirhaeghe，W.P.Leroy，A.Türüt，Semicond.?Sci.Technol.2004，19，1391.

L.Stephen，S.E.Butner，Gallium?Arsenide?Digital?Intergrated?Circuit?Design.(McGraw-Hill，New?York，1990).

¹R.H.Reuss，B.R.Chalamala，A.Moussessian，M.G.Kane，A.Kumar，D.C.Zhang，J.A.Rogers，M.Hatalis，D.Temple，G.Moddel，B.J.Eliasson，M.J.Estes，J.Kunze，E.SHandy，E.S.Harmon，D.B.Salzman，J.M.Woodall，M.A.Alam，J.Y.Murthy，S.C.Jacobsen，M.Olivier，D.Markus，P.M.Campbell，and?E.Snow，Proc.IEEE39，1239(2005).

²K.Nomura，H.Ohta，A.Takagi，T.Kamiya，M.Hirano，and?H.Hosono，Nature?432，488(2004).

³D.B.Mitzi，L.L.Kosbar，C.E.Murray，M.Copel，and?A.Afzali，Nature428，299?(2004).

⁴S.Ucjikoga，MRS?Bull.27，881(2002).

⁵X.Duang，C.Niu，V.Sahi，J.Chen，J.W.Parce，S.Empedocles，and?J.L.Goldman，Nature?425，274(2003).

⁶R.S.Friedman，M.C.McAlpine，D.S.Ricketts，D.Ham，and?C.M.Lieber，Nature?434，1085(2005).

⁷E.Menard，K.J.Lee，D.-Y.Khang，R.G.Nuzzo，and?J.A.Rogers，Appl.Phys.Lett.84，5398(2004).

⁸E.Menard，R.G.Nuzzo，and?J.A.Rogers，Appl.Phys.Lett.86，093507(2005).

⁹Z.-T.Zhu，E.Menard，K.Hurley，R.G.Nuzzo，and?J.A.Rogers，Appl.Phys.Lett.86，133507(2005).

¹⁰Y.Sun，S.Kim，I.Adesida，and?J.A.Rogers，Appl.Phys.Lett.87，083501(2005).

¹¹Y.Sun，and?J.A.Rogers，J.A.Nano?Lett.4，1953?(2004).

¹²Y.Sun，D.-Y.Khang，F.Hua，K.Hurley，R.G.Nuzzo，and?J.A.Rogers，Adv.Funct.Mater.15，30(2005).

¹³A.S.Sedra，and?K.C.Smith，Microelectronic?Circuits?(Oxford?University?Press，NewYork，1998).

¹⁴L.Stephen，and?S.E.Butner，Gallium?Arsenide?Digital?Intergrated?Circuit?Design(McGraw-Hill，New?York，1990).

¹⁵M.C，Lau，Small?Signal?Equivalent?Circuit?Extraction?from?a?Gallium?ArsenideMESFET?device(M.S.thesis，Virginia?Polytechnic?Institution?and?State?University，Blacksburg，VA，1997).

¹⁶L.B.Freund，Intl.J.Solids?Struct.37，85(2000).

¹⁷C.P.Kuo，S.K.Vong，R.M.Cohen，and?G.B.Stringfellow，J.Appl.Phys.57，5428(1985).

¹X.Duan，C.Niu，V.Sahi，J.Chen，J.W.Parce，S.Empedocles，J.L.Goldman，Nature425，274(2003).

²Y.Huang，X.Duan，Q.Wei，C.M.Lieber，Science?291，630(2001).

³M.?A.Meitl，Y.Zhou，A.Gaur，S.Jeon，M.L.Usrey，M.S.Strano，J.A.Rogers，NanoLett.4，No.9?1643(2004).

⁴R.S.Friedman，Nature434，1085(2005).

⁵E.Menard，K.J.Lee，D.-Y.Khang，R.G.Nuzzo?and?J.A.Rogers，Appl.Phys.Lett.?84，5398(2004).

⁶E.Menard，R.G.Nuzzo?and?J.A.Rogers，Appl.Phys.Lett.86，(2005).

⁷Z.-T.Zhu，E.Menard，K.Hurley，R.G.Nuzzo，J.A.Rogers，Appl.Phys.Lett.86，133507(2005).

⁸Y.Sun，S.Kim，I.Adesida，J.A.Rogers，Appl.Phys.Lett.87，083501(2005).

⁹K.J.Lee，M.J.Motala，M.A.Meitl，W.R.Childs，E.Menard，A.K.Shim，J.A.Rogers，R.G.Nuzzo，Adv.Mater.17，2332(2005).

¹⁰M.A.Meitl，Z.-T.Zhu，V.Kumar，K.J.Lee，X.Feng，Y.Y.Huang，I.Adesida，R.G.Nuzzo，and?J.A.Rogers，Nat.Mater.5，33(2006).

¹¹D.Y.Khang，H.Jiang，Y.Huang?and?J.A.Rogers，Science?311，208(2006).

¹²S.R.Forrest，Nature?428，911(2004).

¹³J.A.Rogers，K.E.Paul，R.J.Jackman，G.M.Whitesides，Appl.Phys.Lett.70，2658(1997).

¹⁴S.Sze.，Semiconductor?Devices：Physics?and?Technology?2nd?ed.(Wiley，New?York，2002)，pp.190-192.

R.Reuss?et?al.Proc.IEEE.2005，39，1239.

J.A.Rogers，Z.Bao，K.Baldwin，A.Dodabalapur，B.Crone，V.R.Raju，V.Kuck，H.Katz，K.Amundson，J.Ewing，P.Drzaic，Proc.Nat.Acad.Sci.2001，98，4835.

B.S.Ong，Y.Wu，P.Liu，S.Gardner，J.Am.Chem.Soc.2004，126，3378.

S.R.Forrest，Nature，2004，428，911.

C.R.Kagan，D.B.Mitzi，C.D.Dimitrakopoulos，Science?1999，286，945.

X.Duan，C.Niu，V.Sahi，J.Chen，J.W.Parce，S.Empedocles，J.L.Goldman，Nature，2003，425，274.

J.Kwon，D.Kim，H.Cho，K.Park，J.Jung，J.Kim，Y.Park，T.Noguchi，IEEE?Trans.Electron.2005，466，7.

K.Lee，M.J.Motala，M.A.Meitl，W.R.Childs，E.Menard，A.K.Shim，J.A.Rogers，R.G.Nuzzo，Adv.Mater.2005，17，2336.

Z.Zhu，E.Menard，K.Hurley，R.G.Nuzzo，J.A.Rogers，App.Phys.Lett.2005，86，133507.

M.A.Meitl，Z.Zhu，V.Kumar，K.Lee，X.Feng，Y.Huang，R.G.Nuzzo，J.A.Rogers，Nature?Mater.2006，5，33.

D.Khang，H.Jiang，Y.Huang，J.A.Rogers，Science，2006，311，208.

Y.Sun，S.Kim，I.Adesida，J.A.Rogers，App.?Phys.?Lett.?2005，87，083501.

K.Lee，Dr.J.Lee，H.Hwang，J.A.Rogers，R.G.Nuzzo，Small?2005，1，1164.

(a)?GaN?and?related?Materials?(Eds.：S.J.Pearton)，Gordon?and?Breach，New?York，1997.(b)Group?III?Nitride?Semiconductor?Compounds(Eds.：B.Gil)，Clarendon，Oxford，1998.

(a)U.Mishra，P.Parikh，Y.Wu，Proc.IEEE.2002，90，1022.(b)S.J.Pearton，J.C.Zolper，R.J.Shul，F.Ren，J.Appl.Phys.1999，86，1.(c)S.C.Jain，M.Willander，J.Narayan，R.?Van?Overstraeten，J.Appl.Phys.2000，87，965.

M.A.Khan，A.Bhattari，J.N.Kuznia，and?D.T.Olson，App.?Phys.Lett.?1993，63，1214.

Typical?Si?anisotropic?etch?ratios?in?TMAH?and?H20?mixtures?are?reported?from?12to?50?in?the?direction?<110>/<111>.Please?see?to?the?following?references；(a)Fundamentals?of?Microfabrication，(Ed：M.Madou)，CRC?Press，New?York，1997.(b)D.L.Kendall，Ann.Rev.Mater.Sci.1979，9，373.

V.Kumar，L.Zhou，D.Selvanathan，and?i.Adesida，J.?Appl.?Phys.?2002，92，1712.

Silicon?Processing?for?the?VLSI?Era，Vol.1：Process?Technology，(Ed：S.Wolf，R.N.Tauber)?Lattice?Press，1999.

About quoting the explanation of part and change

Relate to self-assembling technique below with reference to document; These technology can be applied in the inventive method; Shift, assemble and the interconnection printable semiconductor elements through contact print and/or solution printing technology; And by reference mode is included it in here: (1) " Guided molecularself-assembly:a review of recent efforts ", Jiyun C Huie SmartMater.Struct. (2003) 12,264-271; (2) " Large-ScaleHierarchical Organization of Nanowire Arrays for IntegratedNanosystems ", Whang, D.; Jin, S.; Wu, Y.; Lieber, C.M.NanoLett. (2003) 3 (9), 1255-1259; (3) " Directed Assembly ofOne-Dimensiona.l Nanostructures into Functional Networks ", YuHuang, Xiangfeng Duan; Qingqiao Wei; And Charles M.Lieber, Science (2001) 291,630-633; And (4) " Electric-fielda ssistedassembly and alignment of metallic nanowires ", Peter A.Smithet al., Appl.Phys.Lett. (2000) 77 (9), 1399-1401.

All relate to the reference of this application, for example, comprise disclosed or the patent of mandate or the patent text of equivalent; The patent application publication; Unpub patent application; And non-patent literature class text, or the material in other sources; All included in the mode of quoting, although included in the mode of quoting respectively, the degree of including in is at least partly exceeded with the application is consistent with each other with each data here.(for example, reference, inconsistent the quoting through the content beyond the inconsistent part of part during this is quoted of part included in the mode of quoting)

Since then, any one appendix or a plurality of appendix are included the part as this specification and/or accompanying drawing in the mode of quoting.

Used term " to comprise " here and " by comprising "; They are by the existence of explanation as the said characteristic of explanation, integral body, step or institute's finger assembly; There are not or one or more additional other characteristics integral body, step, assembly, perhaps these combination but do not get rid of.Also to should be mentioned that in the embodiment that each separates of the present invention; Term " comprises " or " by comprising " can be replaced by term similar on the grammer alternatively; For example by " by ... form " or " basically by ... form ", so as to describing other embodiments that those there is no need to expand.

Through with technology the present invention being described with reference to various concrete and embodiment preferred.It should be understood, however, that and much to change and to revise, but all drop in order of the present invention and the scope.It is apparent that to those skilled in the art; Composition, method, equipment, equipment component, material, technology and technology except that specifically describing at this; Also can be used to put into practice the present invention, as fully openly seeking help from inappropriate experiment here.In all well known in the art and disclosed composition here, method, equipment, equipment component, material, technology and technology things of equal value on function all intend to be encompassed in by the present invention.When open scope, mean and comprise all underranges and each value, the same as being set forth them respectively.The present invention is not subject to disclosed embodiment, comprises any that show in the accompanying drawings or in the specification exampleization, the mode with example or illustration of these exampleizations provides, and does not constitute restriction.Scope of the present invention is only limited claims.