CN101771260B - Mine intrinsic safety electric source interception self-recovery protection device - Google Patents

一种矿用本安电源截流自恢复保护装置，由检测电路、单稳态电路、信号隔离叠加电路、驱动加速调整电路组成，检测电路分为两路，一路与单稳态电路相连接，另一路与信号隔离叠加电路相连接，单稳态电路的输出与信号隔离叠加电路相连接，信号隔离叠加电路的输出与驱动加速调整电路相连接。本发明适用于矿用本安电源输出短路保护，能实现矿用本安电源在输出端短路的情况下，彻底地关断输出电流，并且能够在故障解除时实现输出电压自恢复功能，减少短路故障时电源释放的能量，从而减少短路时产生的火花释放的能量，防止短路火花点燃易燃易爆气体。并且能降低短路时开关器件的损耗，提高了效率，解决了散热问题。

A mine-used intrinsically safe power supply cut-off self-recovery protection device is composed of a detection circuit, a monostable circuit, a signal isolation superposition circuit, and a drive acceleration adjustment circuit. The detection circuit is divided into two circuits, one of which is connected to the monostable circuit, and the other One path is connected with the signal isolation and superposition circuit, the output of the monostable circuit is connected with the signal isolation and superposition circuit, and the output of the signal isolation and superposition circuit is connected with the drive acceleration adjustment circuit. The invention is suitable for the output short circuit protection of the mine intrinsically safe power supply, and can completely cut off the output current when the mine intrinsically safe power supply is short-circuited at the output end, and can realize the self-recovery function of the output voltage when the fault is eliminated, reducing the short circuit The energy released by the power supply during a fault, thereby reducing the energy released by the spark generated during a short circuit, and preventing the short circuit spark from igniting flammable and explosive gases. And it can reduce the loss of the switching device during short circuit, improve the efficiency and solve the problem of heat dissipation.

矿用本安电源截流自恢复保护装置Mining intrinsically safe power supply cut-off self-recovery protection device

技术领域 technical field

本发明涉及矿用本安电源输出短路保护装置，尤其适用于矿用本安电源输出短路保护，也适用于常规的电源输出短路保护。The invention relates to an output short-circuit protection device of an intrinsically safe power supply for mines, and is especially suitable for output short-circuit protection of intrinsically safe power supplies for mines, and is also suitable for output short-circuit protection of conventional power supplies.

背景技术 Background technique

井下的电控系统中，使用大量的本质安全型电源。这些本质型电源的安全可靠性能对井下安全生产有着重要的意义。为了防止井下本质安全型电源输出端短路(过载)时产生的火花点燃易燃易爆气体，必须降低短路火花所释放的能量。对于输出功率较小而又没有稳压要求的本质安全型电源，可以直接采用输出端串电阻或增加电源内阻的方法进行限能保护。而对于具有稳压要求的本质安全型电源不能采用上述方法，该类型本安电源常用的短路限能保护方式有三种：限流型保护，截止电流型保护，减流型保护。其中截止电流型保护电路比较复杂，电路故障排除后电源也不易自动恢复。由本质安全型电源的工作特性可知输出端短路时，要是不加特殊的保护电路，虽然输出电压为零，但是输出电流很大。较大的短路电流对于周围充满了易燃易爆气体的环境存在着潜在的危险。另外，短路电流增加了开关器件的开通损耗，使得散热问题尤为突出。In the underground electric control system, a large number of intrinsically safe power supplies are used. The safe and reliable performance of these essential power sources is of great significance to underground safe production. In order to prevent the flammable and explosive gas from being ignited by the spark generated when the output end of the downhole intrinsically safe power supply is short-circuited (overloaded), the energy released by the short-circuit spark must be reduced. For intrinsically safe power supplies with low output power and no voltage stabilization requirements, energy-limiting protection can be performed directly by using series resistors at the output end or increasing the internal resistance of the power supply. However, the above methods cannot be used for intrinsically safe power supplies with voltage stabilization requirements. There are three commonly used short-circuit energy-limiting protection methods for this type of intrinsically safe power supplies: current-limiting protection, cut-off current protection, and current-reduction protection. Among them, the cut-off current type protection circuit is relatively complicated, and the power supply is not easy to recover automatically after the circuit fault is eliminated. From the working characteristics of the intrinsically safe power supply, it can be known that when the output terminal is short-circuited, if no special protection circuit is added, although the output voltage is zero, the output current is very large. A large short-circuit current is potentially dangerous to the surrounding environment full of flammable and explosive gases. In addition, the short-circuit current increases the turn-on loss of the switching device, which makes the problem of heat dissipation particularly prominent.

发明内容 Contents of the invention

技术问题：本发明的目的是提供一种结构简单，安全可靠，损耗低，散热好的矿用本安电源截流自恢复保护装置。Technical problem: The purpose of this invention is to provide a mine-used intrinsically safe power supply cut-off self-recovery protection device with simple structure, safety and reliability, low loss and good heat dissipation.

技术方案：本发明矿用本安电源截流自恢复保护装置，由检测电路、单稳态电路、信号隔离叠加电路以及驱动加速调整电路组成；其中：检测电路分为两路，一路与单稳态电路相连接，另一路与信号隔离叠加电路相连接，单稳态电路的输出与信号隔离叠加电路相连接，信号隔离叠加电路的输出与驱动加速调整电路相连接。Technical solution: The self-recovery protection device for mine intrinsically safe power supply of the present invention is composed of a detection circuit, a monostable circuit, a signal isolation superposition circuit and a drive acceleration adjustment circuit; wherein: the detection circuit is divided into two circuits, one circuit and the monostable circuit The circuits are connected, and the other circuit is connected with the signal isolation and superposition circuit, the output of the monostable circuit is connected with the signal isolation and superposition circuit, and the output of the signal isolation and superposition circuit is connected with the drive acceleration adjustment circuit.

所述的检测电路由上拉电阻R1、电压比较器CP1、电流比较器CP2、CP3、与非门U1和多个电阻R+、R-、R、R0、检测电阻R10连接组成；其中：电压比较器CP1、电流比较器CP2、CP3均有两个输入端亦即一个反相端脚1、一个同相端脚2和一个输出端脚3，与非门U1有两个输入端脚1、脚2和一个输出端脚3，电压比较器CP1的同相端脚2和反相端脚1分别与参考电压Vref和输出电压检测值KVo连接，电流比较器CP2的同相端脚2和反相端脚1分别与输出电流检测值Io和参考电流Iref连接，电压比较器CP1的输出端脚3与电流比较器CP2的输出端脚3分别连接与非门U1的输入端脚1和脚2，与非门U1的输出端脚3连接与电源Vin相连的上拉电阻R1，电流比较器CP3的同向端脚2经电阻R接地GND，反相端脚1分别连接电阻R+、R-、R0的一端，其中电阻R+、R-的另一端分别连接到检测电阻R10的电压V+、V-端，电阻R0的另一端连接到电流比较器CP3的输出端脚3，电流比较器CP3的输出端脚3连接到保护电阻R8上。The detection circuit is composed of a pull-up resistor R1, a voltage comparator CP1, a current comparator CP2, CP3, a NAND gate U1 and a plurality of resistors R+, R-, R, R0, and a detection resistor R10; wherein: the voltage comparison Comparator CP1, current comparator CP2, and CP3 have two input terminals, that is, an inverting terminal pin 1, a non-inverting terminal pin 2 and an output terminal pin 3, and the NAND gate U1 has two input terminal pins 1 and 2. And an output terminal pin 3, the non-inverting terminal pin 2 and the inverting terminal pin 1 of the voltage comparator CP1 are respectively connected to the reference voltage Vref and the output voltage detection value KVo, the non-inverting terminal pin 2 and the inverting terminal pin 1 of the current comparator CP2 They are respectively connected to the output current detection value Io and the reference current Iref, the output terminal pin 3 of the voltage comparator CP1 and the output terminal pin 3 of the current comparator CP2 are respectively connected to the input terminal pin 1 and pin 2 of the NAND gate U1, and the NAND gate The output terminal pin 3 of U1 is connected to the pull-up resistor R1 connected to the power supply Vin, the same-direction terminal pin 2 of the current comparator CP3 is grounded to GND through the resistor R, and the inverting terminal pin 1 is respectively connected to one end of the resistors R+, R-, and R0. The other ends of the resistors R+ and R- are respectively connected to the voltage V+ and V- terminals of the detection resistor R10, the other end of the resistor R0 is connected to the output pin 3 of the current comparator CP3, and the output pin 3 of the current comparator CP3 is connected to to the protection resistor R8.

所述的单稳态电路由电容C1、C2、电阻R2、R3、与非门U2、U3连接组成；其中：与非门U2、U3分别有两个输入端脚1、脚2和一个输出端脚3；电容C1的一端连接检测电路中与非门U1的输出端脚3，电容C1的另一端连接与非门U2的输入端脚2，与非门U2的输入端脚2通过R2接地GND，与非门U2的输出端脚3连接到电容C2的一端，电容C2的另一端分别连接到与非门U3的输入端脚1和脚2，与非门U3的输入端脚1和脚2通过电阻R3接地GND，与非门U3的输出端脚3连接到与非门U2的输入端脚1。The monostable circuit is composed of capacitors C1, C2, resistors R2, R3, and NAND gates U2, U3; wherein: NAND gates U2, U3 respectively have two input terminals pin 1, pin 2 and an output terminal Pin 3; one end of the capacitor C1 is connected to the output pin 3 of the NAND gate U1 in the detection circuit, the other end of the capacitor C1 is connected to the input pin 2 of the NAND gate U2, and the input pin 2 of the NAND gate U2 is grounded to GND through R2 , the output pin 3 of the NAND gate U2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is respectively connected to the input pin 1 and pin 2 of the NAND gate U3, and the input pin 1 and pin 2 of the NAND gate U3 The resistor R3 is grounded to GND, and the output terminal pin 3 of the NAND gate U3 is connected to the input terminal pin 1 of the NAND gate U2.

所述的信号隔离叠加电路由上拉电阻R4、下拉电阻R11、光耦OP1、OP2、保护电阻R8、R9连接组成；其中：光耦OP1、OP2分别包括两个输入端脚1、脚2和两个输出端脚3、脚4，上拉电阻R4一端连接电源Vin，上拉电阻R4另一端分别连接光耦OP1的输入端脚1和OP2的输入端脚1，单稳态电路中与非门U3的输出端脚3连接到光耦OP1的输入端脚2，检测电路中电流比较器CP3的输出端脚3连接到光耦OP2的输入端脚2，光耦OP1的两个输入端脚1与脚2之间并联有保护电阻R9，光耦OP2的两个输入端脚1与脚2之间并联有保护电阻R8，光耦OP1的输出端脚3与光耦OP2的输出端脚3共同连接到电源Vin，光耦OP1的输出端脚4与光耦OP2的输出端脚4共同经下拉电阻R11接地GND。The signal isolation superimposition circuit is composed of pull-up resistor R4, pull-down resistor R11, optocoupler OP1, OP2, protection resistor R8, R9 connected; wherein: optocoupler OP1, OP2 includes two input terminals pin 1, pin 2 and Two output pins 3 and 4, one end of the pull-up resistor R4 is connected to the power supply Vin, and the other end of the pull-up resistor R4 is respectively connected to the input pin 1 of the optocoupler OP1 and the input pin 1 of OP2. The output terminal pin 3 of the gate U3 is connected to the input terminal pin 2 of the optocoupler OP1, the output terminal pin 3 of the current comparator CP3 in the detection circuit is connected to the input terminal pin 2 of the optocoupler OP2, and the two input terminal pins of the optocoupler OP1 There is a protective resistor R9 in parallel between 1 and pin 2, a protective resistor R8 is connected in parallel between the two input terminals of the optocoupler OP2, pin 1 and pin 2, and the output pin 3 of the optocoupler OP1 is connected with the output pin 3 of the optocoupler OP2. Commonly connected to the power supply Vin, the output pin 4 of the optocoupler OP1 and the output pin 4 of the optocoupler OP2 are both grounded to GND through the pull-down resistor R11.

所述的驱动加速调整电路由电阻R5、R6、R7、去耦电容C3、驱动芯片U4、调整管Q1连接组成；其中：电源Vin经去耦电容C3接地GND，驱动芯片U4的脚1、脚8连接到电源Vin，驱动芯片U4的脚4、脚5接地GND，驱动芯片U4的输入端脚2连接到信号隔离叠加电路中的光耦OP1的输出端脚4，驱动芯片U4的输出端脚6和脚7共同连接到电阻R5的一端，电阻R5的另一端连接电阻R6、R7的一端以及调整管Q1的触发端，电阻R6的另一端接地GND，电阻R7的另一端连接电源Vin，调整管Q1的源极接到电源Vin。The driving acceleration adjustment circuit is composed of resistors R5, R6, R7, decoupling capacitor C3, driver chip U4, and adjustment tube Q1; wherein: the power supply Vin is grounded to GND through the decoupling capacitor C3, and pins 1 and 2 of the driver chip U4 are connected to each other. 8 is connected to the power supply Vin, pin 4 and pin 5 of the driver chip U4 are grounded to GND, the input pin 2 of the driver chip U4 is connected to the output pin 4 of the optocoupler OP1 in the signal isolation superposition circuit, and the output pin of the driver chip U4 6 and pin 7 are connected to one end of the resistor R5, the other end of the resistor R5 is connected to one end of the resistors R6 and R7 and the trigger end of the adjustment tube Q1, the other end of the resistor R6 is grounded to GND, and the other end of the resistor R7 is connected to the power supply Vin to adjust The source of the tube Q1 is connected to the power supply Vin.

所述的电压比较器CP1、电流比较器CP2、CP3的型号为LM324；所述的光耦OP1、OP2的型号为EL817；所述的调整管Q1的型号为J349。The model of the voltage comparator CP1, the current comparator CP2, CP3 is LM324; the model of the optocoupler OP1, OP2 is EL817; the model of the adjusting tube Q1 is J349.

有益效果：可以实现矿用本安电源在输出端短路的情况下，彻底地关断输出电流，并且能够在故障解除时实现输出电压自恢复功能。当发生过载时，能够维持电流恒定，限制输出功率。故障时能够快速关断输出电流，减少短路故障时电源释放的能量，从而减少短路时产生的火花释放的能量，防止短路火花点燃易燃易爆气体。同时能降低短路时调整管的损耗，解决调整管散热。故障解除时，具有自恢复功能，能实现故障时关断输出电流，故障解除时自动启动，安全稳定工作，其结构简单，安全可靠，损耗低，散热好，具有广泛的实用性。Beneficial effects: the mine intrinsically safe power supply can completely cut off the output current when the output terminal is short-circuited, and can realize the output voltage self-recovery function when the fault is eliminated. When an overload occurs, it can maintain a constant current and limit the output power. When a fault occurs, the output current can be quickly shut down, reducing the energy released by the power supply during a short circuit fault, thereby reducing the energy released by the spark generated during a short circuit, and preventing the short circuit spark from igniting flammable and explosive gases. At the same time, it can reduce the loss of the adjustment tube during short circuit, and solve the heat dissipation of the adjustment tube. When the fault is removed, it has a self-recovery function, which can shut down the output current when the fault occurs, automatically start when the fault is removed, and work safely and stably. Its structure is simple, safe and reliable, low loss, good heat dissipation, and has wide practicability.

附图说明 Description of drawings

图1是本发明的结构框图。Fig. 1 is a structural block diagram of the present invention.

图2是本发明的电路原理图。Fig. 2 is a schematic circuit diagram of the present invention.

其中：1-检测电路，2-单稳态电路，3-信号隔离叠加电路，4-驱动加速调整电路，电压比较器-CP1，电流比较器-CP2、CP3，与非门-U1、U2、U3，隔离光耦-OP1、OP2，驱动芯片-U4，调整管-Q1。Among them: 1- detection circuit, 2- monostable circuit, 3- signal isolation superposition circuit, 4- drive acceleration adjustment circuit, voltage comparator-CP1, current comparator-CP2, CP3, NAND gate-U1, U2, U3, isolation optocoupler-OP1, OP2, driver chip-U4, adjustment tube-Q1.

具体实施方式 Detailed ways

下面结合附图对本发明的一个实施例作进一步的描述：An embodiment of the present invention will be further described below in conjunction with accompanying drawing:

图1所示，本发明主要由检测电路1、单稳态电路2、信号隔离叠加电路3、驱动加速调整电路4组成；检测电路1分为两路，一路与单稳态电路2相连接，另一路与信号隔离叠加电路3相连接，单稳态电路2的输出端与信号隔离叠加电路3相连接，信号隔离叠加电路3的输出端与驱动加速调整电路4相连接。As shown in Fig. 1, the present invention is mainly made up of detection circuit 1, monostable circuit 2, signal isolation superposition circuit 3, drive acceleration adjustment circuit 4; The other path is connected to the signal isolation and superposition circuit 3 , the output end of the monostable circuit 2 is connected to the signal isolation and superposition circuit 3 , and the output end of the signal isolation and superposition circuit 3 is connected to the driving acceleration adjustment circuit 4 .

图2所示，检测电路由上拉电阻R1、电压比较器CP1、电流比较器CP2、CP3、与非门U1和电阻R+、R-、R、R0以及上拉电阻R1、检测电阻R10连接组成；其中：电压比较器CP1、电流比较器CP2、CP3均有两个输入端亦即一个反相端脚1、一个同相端脚2和一个输出端脚3，与非门U1有两个输入端脚1、脚2和一个输出端脚3，电压比较器CP1的同相端脚2和反相端脚1分别与参考电压Vref和输出电压检测值KVo连接，电流比较器CP2的同相端脚2和反相端脚1分别与输出电流检测值Io和参考电流Iref连接，电压比较器CP1的输出端脚3与电流比较器CP2的输出端脚3分别连接与非门U1的输入端脚1和脚2，与非门U1的输出端脚3连接与电源Vin相连的上拉电阻R1，电流比较器CP3的同相端脚2经电阻R接地GND，反相端脚1分别连接电阻R+、R-和R0的一端，其中电阻R+、R-的另一端分别连接到检测电阻R10的电压V+、V-端，电阻R0的另一端连接到电流比较器CP3的输出端脚3，电流比较器CP3的输出端脚3连接到保护电阻R8上，电阻R+、R-、R、R0以及电流比较器CP3构成比例调节器。As shown in Figure 2, the detection circuit is composed of pull-up resistor R1, voltage comparator CP1, current comparator CP2, CP3, NAND gate U1, resistors R+, R-, R, R0, pull-up resistor R1, and detection resistor R10. ; Among them: the voltage comparator CP1, the current comparator CP2, CP3 have two input terminals, that is, an inverting terminal pin 1, a non-inverting terminal pin 2 and an output terminal pin 3, and the NAND gate U1 has two input terminals Pin 1, pin 2 and an output terminal pin 3, the non-inverting terminal pin 2 and the inverting terminal pin 1 of the voltage comparator CP1 are respectively connected to the reference voltage Vref and the output voltage detection value KVo, the non-inverting terminal pin 2 of the current comparator CP2 and The inverting terminal pin 1 is respectively connected to the output current detection value Io and the reference current Iref, and the output terminal pin 3 of the voltage comparator CP1 and the output terminal pin 3 of the current comparator CP2 are respectively connected to the input terminal pin 1 and the pin of the NAND gate U1. 2. The output terminal pin 3 of the NAND gate U1 is connected to the pull-up resistor R1 connected to the power supply Vin, the non-inverting terminal pin 2 of the current comparator CP3 is grounded to GND through the resistor R, and the inverting terminal pin 1 is respectively connected to the resistors R+, R- and One end of R0, the other end of the resistance R+, R- are respectively connected to the voltage V+, V- end of the detection resistor R10, the other end of the resistance R0 is connected to the output pin 3 of the current comparator CP3, the output of the current comparator CP3 The terminal pin 3 is connected to the protection resistor R8, and the resistors R+, R-, R, R0 and the current comparator CP3 form a proportional regulator.

单稳态电路由电容C1、C2、电阻R2、R3以及与非门U2、U3连接组成；其中：与非门U2、U3均有两个输入端脚1、脚2和一个输出端脚3；电容C1的一端连接检测电路中与非门U1的输出端脚3，电容C1的另一端连接与非门U2的输入端脚2，与非门U2的输入端脚2通过R2接地GND，与非门U2的输出端脚3连接到电容C2的一端，电容C2的另一端分别连接到与非门U3的输入端脚1和脚2，与非门U3的输入端脚1和脚2通过电阻R3接地GND，与非门U3的输出端脚3连接到与非门U2的输入端脚1。The monostable circuit is composed of capacitors C1, C2, resistors R2, R3 and NAND gates U2, U3; among them: NAND gates U2, U3 have two input pins 1, 2 and an output pin 3; One end of the capacitor C1 is connected to the output terminal pin 3 of the NAND gate U1 in the detection circuit, the other end of the capacitor C1 is connected to the input terminal pin 2 of the NAND gate U2, and the input terminal pin 2 of the NAND gate U2 is grounded to GND through R2. The output terminal pin 3 of the gate U2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is respectively connected to the input terminal pin 1 and pin 2 of the NAND gate U3, and the input terminal pin 1 and pin 2 of the NAND gate U3 pass through the resistor R3 The ground is GND, and the output terminal pin 3 of the NAND gate U3 is connected to the input terminal pin 1 of the NAND gate U2.

信号隔离叠加电路由上拉电阻R4、下拉电阻R11、光耦OP1、OP2以及保护电阻R8、R9连接组成；其中：光耦OP1、OP2均包括两个输入端脚1、脚2和两个输出端脚3、脚4；上拉电阻R4一端连接电源Vin，上拉电阻R4另一端分别连接光耦OP1的输入端脚1和OP2的输入端脚1，单稳态电路中与非门U3的输出端脚3连接到光耦OP1的输入端脚2，检测电路中电流比较器CP3的输出端脚3连接到光耦OP2的输入端脚2，光耦OP1的两个输入端脚1和脚2之间并联连接有保护电阻R9，光耦OP2的两个输入端脚1和脚2之间并联连接有保护电阻R8，光耦OP1的输出端脚3和OP2的输出端脚3共同连接到电源Vin，光耦OP1的输出端脚4和OP2的输出端脚4共同经下拉电阻R11接地GND。The signal isolation superimposition circuit is composed of pull-up resistor R4, pull-down resistor R11, optocoupler OP1, OP2 and protection resistor R8, R9; among them: optocoupler OP1, OP2 include two input pins 1, 2 and two outputs Terminal pin 3 and pin 4; one end of the pull-up resistor R4 is connected to the power supply Vin, and the other end of the pull-up resistor R4 is respectively connected to the input pin 1 of the optocoupler OP1 and the input pin 1 of OP2, and the NAND gate U3 in the monostable circuit The output pin 3 is connected to the input pin 2 of the optocoupler OP1, the output pin 3 of the current comparator CP3 in the detection circuit is connected to the input pin 2 of the optocoupler OP2, and the two input pins 1 and 2 of the optocoupler OP1 There is a protective resistor R9 connected in parallel between the two, and a protective resistor R8 is connected in parallel between the two input pins 1 and 2 of the optocoupler OP2. The output pin 3 of the optocoupler OP1 and the output pin 3 of OP2 are connected to The power supply Vin, the output pin 4 of the optocoupler OP1 and the output pin 4 of the OP2 are both grounded to GND through the pull-down resistor R11.

驱动加速调整电路由电阻R5、R6、R7、去耦电容C3、驱动芯片U4、调整管Q1连接组成；其中：电源Vin经去耦电容C3接地GND，驱动芯片U4的脚1、脚8连接到电源Vin，驱动芯片U4的脚4、脚5接地GND，驱动芯片U4的输入端脚2连接到信号隔离叠加电路中的光耦OP1的输出端脚4，驱动芯片U4的输出端脚6和脚7共同连接到R5的一端，R5的另一端接到电阻R6和R7的一端以及调整管Q1的触发端，R7的另一端与电源Vin连接，R6的另一端接地GND，调整管Q1的源极接到电源Vin，驱动加速调整电路的信号由调整管Q1的漏极输出。The drive acceleration adjustment circuit is composed of resistors R5, R6, R7, decoupling capacitor C3, driver chip U4, and adjustment tube Q1; among them, the power supply Vin is grounded to GND through the decoupling capacitor C3, and pin 1 and pin 8 of the driver chip U4 are connected to Power supply Vin, pin 4 and pin 5 of the driver chip U4 are grounded to GND, the input pin 2 of the driver chip U4 is connected to the output pin 4 of the optocoupler OP1 in the signal isolation superposition circuit, and the output pin 6 and pin 5 of the driver chip U4 7. Commonly connected to one end of R5, the other end of R5 is connected to one end of resistors R6 and R7 and the trigger end of adjustment tube Q1, the other end of R7 is connected to the power supply Vin, the other end of R6 is grounded to GND, and the source of adjustment tube Q1 Received to the power supply Vin, the signal driving the acceleration adjustment circuit is output from the drain of the adjustment transistor Q1.

当电路过流的时候，检测电阻R10两端电压V+，V-经过由电阻R+、R-、R、R0以及电流比较器CP3组成的比例调节器，电流比较器CP3将信号传送到光耦OP2的输入端脚2，光耦OP2再将信号由输出端脚4传送到驱动芯片U4的输入端脚2，驱动芯片U4产生控制信号Vg，控制调整管Q1来保证输出电流恒定。When the circuit is overcurrent, the voltage V+ and V- across the detection resistor R10 pass through a proportional regulator composed of resistors R+, R-, R, R0 and current comparator CP3, and the current comparator CP3 transmits the signal to the optocoupler OP2 The input terminal pin 2 of the optocoupler OP2 then transmits the signal from the output terminal pin 4 to the input terminal pin 2 of the driver chip U4, and the driver chip U4 generates a control signal Vg to control the adjustment tube Q1 to ensure a constant output current.

当输出发生短路故障时，本安电源的输出电压Vout降低，当电压比较器CP1检测的电压KVo小于基准电压Vref＝1.5V时，电压比较器CP1的输出端脚3输出高电平，同时在输出短路故障时，输出电流Io增大，当电流比较器CP2检测的输出电流Io大于基准电流Iref＝0.7A时，电流比较器CP2输出端脚3的电平也为高电平，从而使与非门U1的输出端脚3为低电平。上拉电阻R1确保与非门U1输出端脚3为有效电平状态。与非门U1输出端脚3的低电平触发后级的单稳态电路2。单稳态电路2的脉冲最终从与非门U3的输出端脚3输出。单稳态电路2的输出信号经信号隔离叠加电路3传送到驱动芯片U4，输出驱动信号来控制电路的调整管Q1。驱动芯片U4能够增加脉冲的陡峭沿，而且信号的延迟典型值为20ns，提高信号反应的速度，增强信号的驱动能力，能够在最短的时间内关断调整管Q1，有效地抑制输出的能量，从而达到抑制短路火花释放的能量的效果。When a short-circuit fault occurs in the output, the output voltage Vout of the intrinsically safe power supply decreases, and when the voltage KVo detected by the voltage comparator CP1 is lower than the reference voltage Vref=1.5V, the output pin 3 of the voltage comparator CP1 outputs a high level, and at the same time When the output short-circuit fault occurs, the output current Io increases. When the output current Io detected by the current comparator CP2 is greater than the reference current Iref=0.7A, the level of the pin 3 of the output terminal of the current comparator CP2 is also high, so that The output terminal pin 3 of the NOT gate U1 is low level. The pull-up resistor R1 ensures that the output pin 3 of the NAND gate U1 is in an active level state. The low level of pin 3 of the output terminal of NAND gate U1 triggers the monostable circuit 2 of the subsequent stage. The pulse of the monostable circuit 2 is finally output from the output pin 3 of the NAND gate U3. The output signal of the monostable circuit 2 is transmitted to the driving chip U4 through the signal isolation and superimposition circuit 3, and the output driving signal is used to control the adjustment tube Q1 of the circuit. The driver chip U4 can increase the steep edge of the pulse, and the typical value of the signal delay is 20ns, which improves the speed of the signal response, enhances the driving ability of the signal, and can turn off the adjustment tube Q1 in the shortest time, effectively suppressing the output energy. So as to achieve the effect of suppressing the energy released by the short-circuit spark.

当输出发生短路故障时，电压比较器CP1的输出端脚3和电流比较器CP2的输出端脚3的输出电平都为高电平，所以与非门U1的输出端脚3输出为低电平，触发单稳态电路2，使其进入暂态过程，此时单稳态电路2中的与非门U3的输出端脚3产生脉冲，该脉冲经过信号隔离叠加电路3传输到驱动芯片U4，从而产生驱动信号Vg，控制调整管Q1使电路关断，此时整个电路的输出电流Io为零，电流比较器CP2的输出端脚3输出为低电平，那么与非门U1的输出端脚3输出为高电平；当暂态过程结束，若故障已经解除，输出建立电压Vout，经检测电路1获得的电压KVo大于参考电压Vref，电压比较器CP1的输出端脚3的输出为低电平，输出电流Io小于参考电流Iref，电流比较器CP2的输出端脚3的输出为低电平，那么与非门U1的输出端脚3的输出始终为高电平，单稳态电路2始终为稳定状态，调整管Q1始终导通，该装置自动恢复正常工作，暂态过程结束，若输出故障尚未解除，电压比较器CP1的输出端脚3和电流比较器CP2的输出端脚3均为高电平，此时与非门U1的输出端脚3变为低电平，那么单稳态电路2又被触发，再次进入暂态过程，调整管Q1又被导通，进行故障检测。若故障仍未解除，该装置重复上述暂态过程，直至故障解除为止。When a short-circuit fault occurs in the output, the output levels of the output pin 3 of the voltage comparator CP1 and the output pin 3 of the current comparator CP2 are both high, so the output pin 3 of the NAND gate U1 is low. Ping, trigger the monostable circuit 2 to make it enter the transient process, at this time the output terminal pin 3 of the NAND gate U3 in the monostable circuit 2 generates a pulse, and the pulse is transmitted to the driver chip U4 through the signal isolation and superposition circuit 3 , so as to generate the drive signal Vg, control the adjustment tube Q1 to turn off the circuit, at this time the output current Io of the whole circuit is zero, and the output pin 3 of the current comparator CP2 outputs a low level, then the output terminal of the NAND gate U1 The output of pin 3 is high level; when the transient process is over, if the fault has been eliminated, the output voltage Vout is established, the voltage KVo obtained by the detection circuit 1 is greater than the reference voltage Vref, and the output of the output pin 3 of the voltage comparator CP1 is low Level, the output current Io is less than the reference current Iref, the output of the output pin 3 of the current comparator CP2 is low level, then the output of the output pin 3 of the NAND gate U1 is always high level, the monostable circuit 2 It is always in a stable state, the adjustment tube Q1 is always on, the device automatically resumes normal operation, and the transient process is over. If the output fault has not been resolved, the output pin 3 of the voltage comparator CP1 and the output pin 3 of the current comparator CP2 are both At this time, the output terminal pin 3 of the NAND gate U1 becomes low level, then the monostable circuit 2 is triggered again, enters the transient process again, and the adjustment tube Q1 is turned on again to perform fault detection. If the fault is still not resolved, the device repeats the above transient process until the fault is resolved.