CN101834603A - A Quadrature Input Quadrature Output Quadrature Divider by Two with Low Power Consumption and Low Spur - Google Patents
- ️Wed Sep 15 2010
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- CN101834603A CN101834603A CN201010186487A CN201010186487A CN101834603A CN 101834603 A CN101834603 A CN 101834603A CN 201010186487 A CN201010186487 A CN 201010186487A CN 201010186487 A CN201010186487 A CN 201010186487A CN 101834603 A CN101834603 A CN 101834603A Authority
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Abstract
本发明属于射频无线接收机集成电路技术领域，具体为一种低功耗低杂散的正交输入正交输出二分频器。该二分频器由可变负载级，输入跨导级，混频级和可变电流源偏置电路组成。与传统的源级耦合逻辑二分频电路和米勒二分频电路相比较，本发明可以在较低的功耗下实现较高的工作频率和较高的三次谐波抑制，并且工艺偏差和温度偏差不敏感。
The invention belongs to the technical field of radio frequency wireless receiver integrated circuits, in particular to a quadrature input quadrature output two frequency divider with low power consumption and low stray. This divider by two consists of a variable load stage, an input transconductance stage, a mixer stage and a variable current source bias circuit. Compared with traditional source-level coupled logic divide-by-two circuits and Miller divide-by-two circuits, the present invention can achieve higher operating frequency and higher third-harmonic suppression at lower power consumption, and the process deviation and Insensitive to temperature deviations.
Description
Technical field
The invention belongs to wireless radiofrequency receiver ic technical field, be specifically related to a kind of design that is applied to the quadrature input quadrature output frequency divider (Quadrature Input Quadrature Output Frequency Divider) in the wireless receiver integrated circuit, can realize two divided-frequency high-frequency signal.
Background technology
Along with modern information technology development, more and more stronger to the High Data Rate of wireless communication technology and big bandwidth requirement, this impels people constantly to go to develop the wireless communication technology of higher band resource and research hyperfrequency.Meanwhile, under the inexorable trend that the System on Chip/SoC direction develops, low power dissipation design has become the inevitable requirement of various communication systems to circuit design at modern integrated circuits.Along with improving constantly that systematic function requires, the harmonic suppression effect of frequency divider is required also improving constantly.Under this background, to high-frequency and low-consumption, the frequency divider research with harmonic suppression effect has great significance undoubtedly with design.Quadrature input and output two-divider utilizes the principle of Miller (Miller) divider, by output signal is fed back to single sideband mixer, finishes the two divided-frequency to input signal.And quadrature input and output frequency divider has extraordinary triple-frequency harmonics and suppresses effect.Quadrature input and output frequency divider is more stable, and is insensitive to process deviation and temperature deviation.Yet the shortcoming of quadrature input quadrature output frequency divider is that its operating frequency range is limited.
Summary of the invention
Can not handle the shortcoming of orthogonal signalling at current source class coupling logic frequency divider, it is big to the objective of the invention is to propose a kind of operating frequency range, the orthogonal input and orthogonal output frequency-halving device that power consumption is little is to realize the actual application value of this frequency divider in the frequency synthesizer system.
The orthogonal input and orthogonal output frequency-halving device that the present invention proposes, its circuit structure as shown in Figure 1, this orthogonal input and orthogonal output frequency-halving device mainly comprises following four parts: variable load level, transconductance stage, mixer stage and variable current source biasing circuit.The agent structure of circuit is made up of transconductance stage and mixer stage, and transconductance stage changes input voltage signal into current signal, finishes division function with output signal in mixer stage, exports by load stage at last; Biasing circuit is made up of two nmos pass transistors.
The annexation of the orthogonal input and orthogonal output frequency-halving device circuit that the present invention proposes is as follows: the drain terminal of PMOS transistor M35-M49 is connected to power vd D, and the source end is connected respectively to the end of resistance R 1-R12; Wherein, the other end of resistance R 1-R3 is connected to output OUTI, and the other end of resistance R 4-R6 is connected to output OUTIB, and the other end of resistance R 7-R9 is connected to output OUTQB, and the other end of resistance R 10-R12 is connected to output OUTQ; Output OUTI is connected to drain terminal and the grid end of the NMOS pipe M19 of mixer stage, the drain terminal of M21, the grid end of M22, the drain terminal of M27, the drain terminal of M29, the grid end of M31 and the grid end of M34; Output OUTIB is connected to grid end and the drain terminal of the NMOS pipe M20 of mixer stage, the grid end of M21, the drain terminal of M22, the drain terminal of M28, the drain terminal of M30, the grid end of M32 and the grid end of M33; Output OUTQB is connected to the drain terminal of the NMOS pipe M23 of mixer stage, the grid end of M24, grid end and the drain terminal of M25, the grid end of M28, the grid end of M29, the drain terminal of M32, the drain terminal of M34; Output OUTQ is connected to the grid end of the NMOS pipe M23 of mixer stage, the drain terminal of M24, grid end and the drain terminal of M26, the grid end of M27, the grid end of M30, the drain terminal of M31, the drain terminal of M33; NMOS manages M19, M20, and the source of M23 and M24 terminates to the drain terminal of the NMOS pipe M25 of transconductance stage; NMOS manages M21, M22, and the source of M25 and M26 terminates to the drain terminal of the NMOS pipe M26 of transconductance stage; NMOS manages M27, M28, and the source of M31 and M32 terminates to the drain terminal of the NMOS pipe M17 of transconductance stage; NMOS manages M27, M28, and the source of M29 and M30 terminates to the drain terminal of the NMOS pipe M2 of transconductance stage; NMOS manages M2, and M6, the drain terminal of M10 and M14 receive the drain terminal of current biasing circuit NMOS pipe M2; Grid end and drain terminal that the grid end of NMOS pipe M2 is connected to nmos pass transistor M1 constitute current mirror, and the drain terminal of nmos pass transistor M1 is directly connected to outside current source, and the source of NMOS pipe M2 and M1 terminates to ground VSS; NMOS manages M2, M6, and M10 and M14 constitute variable current source, and NMOS pipe M3 and M5 drain terminal are connected to the grid end of NMOS pipe M2, and the source end of NMOS pipe M3 and M5 is connected to the drain terminal of NMOS pipe M4 and the grid end of M6, and the source end of NMOS pipe M4 is connected to ground VSS; NMOS pipe M7 and M9 drain terminal are connected to the grid end of NMOS pipe M2, and the source end of NMOS pipe M7 and M9 is connected to the drain terminal of NMOS pipe M8 and the grid end of M10, and the source end of NMOS pipe M8 is connected to ground VSS; NMOS pipe M11 and M13 drain terminal are connected to the grid end of NMOS pipe M2, and the source end of NMOS pipe M11 and M13 is connected to the drain terminal of NMOS pipe M12 and the grid end of M14, and the source end of NMOS pipe M12 is connected to ground VSS.Behind the input signal process capacitance C1-C4, be input to transconductance stage after the resistance R 5-R8 biasing.
Existing Miller divider structure is compared, and main improvement of the present invention is, to the improvement of frequency divider input mode and feedback system, realizes the orthogonal differential input, and has significantly improved the inhibitory action of frequency-halving circuit to triple-frequency harmonics, below will do concrete introduction.
The theory diagram of the QIQO frequency divider of a simplification as shown in Figure 2.The QIQO frequency divider is based on the Miller frequency divider of traditional multiplier.But, different with single feedback control loop of traditional Miller frequency divider, used 4 multipliers and 4 feedback control loops in the QIQO frequency divider with same phase deviation.IQ two-way input signal all is fully utilized, and respectively in path 1 and 2, path 3 and 4 is finished the function of two divided-frequency.And the output current addition of path 1 and path 3 constitutes homophase output, and the output current addition of path 2 and path 4 constitutes quadrature output.
Description of drawings
The orthogonal input and orthogonal output frequency-halving device electrical block diagram of Fig. 1 ohmic load.
The quadrature input quadrature output frequency divider theory diagram that Fig. 2 simplifies.
Fig. 3 uses the phase-locked loop schematic diagram of quadrature input quadrature output frequency divider.
Embodiment
Orthogonal input and orthogonal output frequency-halving device of the present invention is applied to 6.0GHz in the frequency synthesizer system of two carrier wave OFDM ultra-widebands (Double Carrier Orthogonal Frequency Division Multiplexing Ultra-Wide Band) radio-frequency transmitter of 9.0GHz frequency range, Figure 3 shows that the structural representation of phase-locked loop in this frequency synthesizer, it is by phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider link are formed.Phase frequency detector detects the difference on the frequency and the phase difference of crystal oscillator (reference clock) and output signal of frequency divider, and the size conversion of difference is become current signal by charge pump, thereby this electric current forms the frequency that voltage signal is regulated voltage controlled oscillator after flowing into loop filter, is zero until detected frequency of phase frequency detector and phase difference value.In the practical application, the frequency divider link is made up of the divider circuit of many levels usually, and the operating frequency of each grade reduces successively.The input signal of first order frequency divider is the output signal of oscillator in the phase-locked loop, and operating frequency is the highest in entire circuit, also is that power consumption consumes maximum one-level.Quadrature input quadrature output frequency divider proposed by the invention is applied in the whole two-divider link, and its inhibition triple-frequency harmonics advantage can reduce the triple-frequency harmonics of whole frequency synthesizer.
First order frequency divider in the PLL of the present invention's design, because its operating frequency height (8GHz-10GHz), for saving power consumption, increase the consideration of output voltage swing, use the QIQO frequency divider of inductive load in first order frequency divider, other rudimentary dividers use the quadrature input and output two-divider of ohmic load.Note that the Q value of inductance is bigger when selecting the LC resonant cavity, the output impedance when improving resonance increases the amplitude of oscillation, and the Q value of inductance is not too high simultaneously, not so can limit the lock-in range of frequency divider.
Compare with the Miller frequency divider that traditional differential signal is imported, the size Selection of all crystals pipe can be identical with the Miller frequency divider.Like this, Zheng Ti power consumption also is the same with the Miller frequency divider.But in the present invention,, improve the load matched of QVCO because RF pipe in bottom so the size of each input transistors can reduce by half, so just can obviously reduce the capacitive load of QVCO through merging.
In actual use,, added variable current source for the QIQO frequency divider, so not only can make the QIQO frequency divider that the constant amplitude of oscillation is arranged under different frequency, under the condition that does not influence the frequency divider performance, can significantly reduce power consumption in order to make output voltage swing and power consumption constant.In order to increase the frequency input range of frequency divider, the present invention has used the resistance variable load level that constitutes in parallel.
Claims (5)
1.一种正交输入正交输出二分频器，其特征在于该二分频器由负载级，跨导级，混频级和电流源偏置电路经电路连接组成；其中，由跨导级和混频级组成电路的主体结构，跨导级将输入电压信号转变为电流信号，与输出信号在混频器级完成分频功能，最后通过负载级输出；偏置电路由两个NMOS晶体管组成。1. A quadrature input quadrature output two frequency divider is characterized in that this two frequency divider is made up of load stage, transconductance stage, mixing stage and current source bias circuit through circuit connection; Wherein, by transconductance The main structure of the circuit is composed of the transconductance stage and the frequency mixing stage. The transconductance stage converts the input voltage signal into a current signal, and the output signal completes the frequency division function at the mixer stage, and finally outputs through the load stage; the bias circuit consists of two NMOS transistors composition. 2.如权利要求1所述的正交输入正交输出二分频器，其特征在于：PMOS晶体管M35-M49的漏端连接到电源VDD，源端分别连接到电阻R1-R12的一端；其中，电阻R1-R3的另一端连接到输出端OUTI，电阻R4-R6的另一端连接到输出端OUTIB，电阻R7-R9的另一端连接到输出端OUTQB，电阻R10-R12的另一端连接到输出端OUTQ。2. The quadrature-input quadrature-output two-frequency divider as claimed in claim 1, characterized in that: the drain terminals of the PMOS transistors M35-M49 are connected to the power supply VDD, and the source terminals are respectively connected to one end of the resistors R1-R12; wherein , the other end of the resistor R1-R3 is connected to the output terminal OUTI, the other end of the resistor R4-R6 is connected to the output terminal OUTIB, the other end of the resistor R7-R9 is connected to the output terminal OUTQB, and the other end of the resistor R10-R12 is connected to the output terminal Terminal OUTQ. 3.如权利要求2所述的正交输入正交输出二分频器，其特征在于：输出端OUTI连接到混频器级的NMOS管M19的漏端和栅端，M21的漏端，M22的栅端，M27的漏端，M29的漏端，M31的栅端和M34的栅端；输出端OUTIB连接到混频器级的NMOS管M20的栅端和漏端，M21的栅端，M22的漏端，M28的漏端，M30的漏端，M32的栅端和M33的栅端；输出端OUTQB连接到混频器级的NMOS管M23的漏端，M24的栅端，M25的栅端和漏端，M28的栅端，M29的栅端，M32的漏端，M34的漏端；输出端OUTQ连接到混频器的NMOS管M23的栅端，M24的漏端，M26的栅端和漏端，M27的栅端，M30的栅端，M31的漏端，M33的漏端；NMOS管M19，M20，M23和M24的源端接到跨导级NMOS管M25的漏端；NMOS管M21，M22，M25和M26的源端接到跨导级的NMOS管M26的漏端；NMOS管M27，M28，M31和M32的源端接到跨导级的NMOS管M17的漏端；NMOS管M27，M28，M29和M30的源端接到跨导级的NMOS管M2的漏端。3. quadrature input quadrature output two frequency divider as claimed in claim 2, it is characterized in that: output end OUTI is connected to the drain end and gate end of the NMOS transistor M19 of mixer stage, the drain end of M21, M22 The gate terminal of M27, the drain terminal of M29, the gate terminal of M31 and the gate terminal of M34; the output terminal OUTIB is connected to the gate terminal and drain terminal of the NMOS transistor M20 of the mixer stage, the gate terminal of M21, and the gate terminal of M22 The drain terminal of M28, the drain terminal of M30, the gate terminal of M32 and the gate terminal of M33; the output terminal OUTQB is connected to the drain terminal of the NMOS transistor M23 of the mixer stage, the gate terminal of M24, and the gate terminal of M25 and drain terminal, the gate terminal of M28, the gate terminal of M29, the drain terminal of M32, the drain terminal of M34; the output terminal OUTQ is connected to the gate terminal of the NMOS tube M23 of the mixer, the drain terminal of M24, the gate terminal of M26 and The drain terminal, the gate terminal of M27, the gate terminal of M30, the drain terminal of M31, the drain terminal of M33; the source terminals of the NMOS transistors M19, M20, M23 and M24 are connected to the drain terminal of the transconductance NMOS transistor M25; the NMOS transistor M21 , the source terminals of M22, M25 and M26 are connected to the drain terminal of the NMOS transistor M26 of the transconductance stage; the source terminals of the NMOS transistors M27, M28, M31 and M32 are connected to the drain terminal of the NMOS transistor M17 of the transconductance stage; the NMOS transistor M27 , the source terminals of M28, M29 and M30 are connected to the drain terminal of the NMOS transistor M2 of the transconductance stage. 4.如权利要求3所述的正交输入正交输出二分频器，其特征在于：NMOS管M2，M6，M10和M14的漏端连接到电流偏置电路NMOS管M2的漏端；NMOS管M2的栅端连接到NMOS管M1的栅端和漏端构成电流镜，NMOS管M1的漏端连接到外部的电流源，NMOS管M2和M1的源端接到地VSS；NMOS管M2，M6，M10和M14构成可变电流源，M3和M5漏端连接到NMOS管M2的栅端，NMOS管M3和M5的源端连接到NMOS管M4的漏端和M6的栅端，NMOS管M4的源端连接到地VSS；NMOS管M7和M9漏端连接到NMOS管M2的栅端，NMOS管M7和M9的源端连接到NMOS管M8的漏端和M10的栅端，NMOS管M8的源端连接到地VSS；NMOS管M11和M13漏端连接到NMOS管M2的栅端，NMOS管M11和M13的源端连接到NMOS管M12的漏端和M14的栅端，NMOS管M12的源端连接到地VSS。4. The quadrature input quadrature output two-frequency divider as claimed in claim 3, characterized in that: the drain ends of the NMOS transistors M2, M6, M10 and M14 are connected to the drain end of the current bias circuit NMOS transistor M2; The gate terminal of the tube M2 is connected to the gate terminal and the drain terminal of the NMOS tube M1 to form a current mirror, the drain terminal of the NMOS tube M1 is connected to an external current source, and the source terminals of the NMOS tubes M2 and M1 are connected to the ground VSS; the NMOS tube M2, M6, M10 and M14 constitute a variable current source, the drains of M3 and M5 are connected to the gate of NMOS transistor M2, the sources of NMOS transistors M3 and M5 are connected to the drain of NMOS transistor M4 and the gate of M6, and the NMOS transistor M4 The source terminal of NMOS transistor M7 and M9 is connected to the gate terminal of NMOS transistor M2, the source terminal of NMOS transistor M7 and M9 is connected to the drain terminal of NMOS transistor M8 and the gate terminal of M10, and the gate terminal of NMOS transistor M8 The source end is connected to the ground VSS; the drain ends of the NMOS transistors M11 and M13 are connected to the gate end of the NMOS transistor M2, the source ends of the NMOS transistors M11 and M13 are connected to the drain end of the NMOS transistor M12 and the gate end of the M14, and the source end of the NMOS transistor M12 connected to ground VSS. 5.如权利要求4所述的正交输入正交输出二分频器，其特征在于：输入信号经过隔直电容C1-C4后，被电阻R13-R16偏置后输入到跨导级。5. The quadrature-input quadrature-output frequency divider according to claim 4, wherein the input signal is biased by resistors R13-R16 and then input to the transconductance stage after passing through DC blocking capacitors C1-C4.
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Cited By (5)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102821077A (en) * | 2011-06-09 | 2012-12-12 | 恒原微电子(上海)有限公司 | Quadrature input and quadrature output frequency-having circuit |
| CN103180329A (en) * | 2010-09-30 | 2013-06-26 | 意法爱立信有限公司 | High speed RF divider |
| CN105322952A (en) * | 2014-05-27 | 2016-02-10 | 恩智浦有限公司 | Multi-modulus frequency divider |
| CN106603067A (en) * | 2017-01-10 | 2017-04-26 | 深圳市华讯方舟微电子科技有限公司 | Orthogonal input divide-by-2 frequency divider |
| WO2020211108A1 (en) * | 2019-04-18 | 2020-10-22 | Hong Kong Applied Science and Technology Research Institute Company Limited | A 50%duty cycle quadrature-in and quadrature-out (qiqo) divide-by-3 circuit |
-
2010
- 2010-05-27 CN CN201010186487A patent/CN101834603A/en active Pending
Cited By (7)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103180329A (en) * | 2010-09-30 | 2013-06-26 | 意法爱立信有限公司 | High speed RF divider |
| CN102821077A (en) * | 2011-06-09 | 2012-12-12 | 恒原微电子(上海)有限公司 | Quadrature input and quadrature output frequency-having circuit |
| CN105322952A (en) * | 2014-05-27 | 2016-02-10 | 恩智浦有限公司 | Multi-modulus frequency divider |
| US9843329B2 (en) | 2014-05-27 | 2017-12-12 | Nxp B.V. | Multi-modulus frequency divider |
| CN105322952B (en) * | 2014-05-27 | 2018-10-16 | 恩智浦有限公司 | Multi-modulus frequency divider and communication means |
| CN106603067A (en) * | 2017-01-10 | 2017-04-26 | 深圳市华讯方舟微电子科技有限公司 | Orthogonal input divide-by-2 frequency divider |
| WO2020211108A1 (en) * | 2019-04-18 | 2020-10-22 | Hong Kong Applied Science and Technology Research Institute Company Limited | A 50%duty cycle quadrature-in and quadrature-out (qiqo) divide-by-3 circuit |
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