CN101882582A - Production method of semiconductor device - Google Patents

As shown in Figure 1a, on

100, form the active area of semiconductor device, comprise grid, source electrode and drain electrode, utilize the method (CVD) of chemical vapour deposition (CVD) to form one deck self-aligned silicide region blocks (SAB) film, this SAB film cover part source electrode, drain and gate then.The manufacture method of said structure and concrete formation thereof are irrelevant with the present invention, wherein also comprise gate lateral wall layer, gate oxide, the structures such as channel layer below the gate oxide on Semiconductor substrate between source electrode and the drain electrode, do not repeat them here, the structure that will form on

100 is called

101.

Shown in Fig. 1 b, form

102 with high tensile stress on the surface of said structure 101.SAB film in these

102 covered

101 and the gate lateral wall layer that does not have tensile stress that forms by common silicon nitride.Formation has the

102 and the difference that does not have the common silicon nitride of tensile stress of high tensile stress, parameter when mainly being to deposit is provided with difference, the difference of factor such as radio-frequency power, depositing temperature for example, just can form silicon nitride layer with different tensile stresss, this is a known technology, specifically forms method and does not disclose at this.

Wherein, requiring tensile stress to be the bigger the better certainly, is 65 nanometers even higher technology generation at critical size (CD), and the tensile stress that

102 requirements are had is also more and more higher.But method according to prior art, when tensile stress reaches 1.2GPa, discovery is easy in the corner of

102 crack (crack) take place, this is because

102 contacts with the gate lateral wall layer that does not have tensile stress that the common silicon nitride of its covering forms, high stress makes the contacted interface of silicon nitride layer of different nature that crack take place, and finally influences the performance of device.

Shown in Fig. 2 a, on

100, form the active area of semiconductor device, comprise grid, source electrode and drain electrode, utilize the CVD method to form one deck SAB film, this SAB film cover part source electrode, drain and gate then.The manufacture method of said structure and concrete formation thereof are irrelevant with the present invention, wherein also comprise gate lateral wall layer, gate oxide, the structures such as channel layer below the gate oxide on Semiconductor substrate between source electrode and the drain electrode, do not repeat them here, the structure that will form on

100 is called

101.

Next shown in Fig. 2 b, form

201, SAB film in these

201 covered

101 and the gate lateral wall layer that does not have tensile stress that forms by common silicon nitride on the surface of said structure 101.When forming

201, temperature will be controlled at below 480 degrees centigrade, promptly between 0 to 480 degree centigrade.This is because SAB film in

101 generally is made of nickel silicon (NiSi), if temperature greater than 480 degrees centigrade, NiSi is easy to sex change, and is just ineffective as the silicon and the adhesive between the tungsten in the successive process of active area.

At last, shown in Fig. 2 c, form

202 with high tensile stress on

201 surfaces.

Forming

201 is exactly for the heavily stressed process resilient coating that

202 is had all is delivered in the raceway groove, and can prevent because the crack that high stress causes.With

201 is that silicon oxide layer is an example, the formation method has inferior aumospheric pressure cvd (SACVD), low-pressure chemical vapor deposition (LPCVD), aumospheric pressure cvd (APCVD) and plasma enhanced chemical vapor deposition various deposition processs such as (PECVD), wherein PECVD comprise again with tetraethoxysilane (TEOS) be predecessor (PETEOS), be (PEOX) of predecessor, be (PESRO) or the like ionic depositing method of predecessor with the silicon rich oxide with monosilane (SiH4).Because the resilient coating that the plasma deposition method forms all is a compression, weaken greatly in the time of can making the tensile stress of

202 be delivered to raceway groove, and the resilient coating that SACVD, LPCVD and APCVD form is a tensile stress, when making the tensile stress of

202 be delivered to raceway groove still near original tensile stress size.Further, SACVD and LPCVD are the resilient coatings of thermal decomposition type growth, to not damage of

101, and the plasma deposition method, for example PETEOS, PEOX, PESRO be easy to generate the damage that plasma bombardment introduces (Plasma Induced Damage, PID), the electronics in the possible plasma can enter

101, and then enter gate oxide etc., influence the performance of device.So the formation method of

201 is preferably SACVD, LPCVD and APCVD.

For 65 nanometers even higher technology generation, the tensile stress that desired

202 has is also more and more higher, for the tensile stress that

202 is had passes to raceway groove effectively, and do not produce the crack defective, the tensile stress of

201, at first to guarantee the tensile stress that had less than

202, preferably be controlled between the 100MPa to 500MPa, if less than 100MPa, stress is difficult to control, if and greater than 500MPa, because

201 be the effect of the stress that had of transmission

202,, may produce some side effects otherwise stress is excessive so be nonsensical greater than the

201 of 500MPa, like that will be as

202, too high stress makes following structure produce crack.The THICKNESS CONTROL of

201 is between 50 dust to 150 dusts, because if then do not have the effect of transmitting stress less than 50 dusts, if and greater than 150 dusts, in close line (dense) zone, the i.e. very near place of distance between two grids, the very near place of distance between two

101 just is if form interlayer dielectric layer (ILD) on the basis of

202, the ILD layer will have a strong impact on the performance of device than other place single line (iso) zone thick a lot of for example.Further, the tensile stress of

201 is preferably 200MPa, 250MPa and 300MPa, and thickness is preferably 100 dusts, 120 dusts and 140 dusts.Like this, when formation has the

202 of 1.2GPa even higher tensile stress, also do not have crack and take place, and it is also very approaching with 1.2GPa to enter the stress of raceway groove.

201 can be silicon oxide layer, also can be silicon nitride layer, so foregoing description is equally applicable to silicon nitride layer, that is to say that the temperature that forms silicon nitride layer is between 0 to 480 degree centigrade, method is preferably SACVD, LPCVD and the APCVD method that produces tensile stress, tensile stress is controlled between the 100MPa to 500MPa, and THICKNESS CONTROL is between 50 dust to 150 dusts.Especially, tensile stress is preferably 200MPa, 250MPa and 300MPa, and thickness is preferably 100 dusts, 120 dusts and 140 dusts.

1. the manufacture method of a semiconductor device is included in and is formed with the source region on the Semiconductor substrate and forms self-aligned silicide region blocks film on active area, it is characterized in that this method also comprises:

On said structure, form resilient coating;

On described resilient coating, form silicon nitride layer with tensile stress;

The tensile stress that described resilient coating has is used to transmit described stress with silicon nitride layer of tensile stress less than the tensile stress that described silicon nitride layer has.

2. the method for claim 1 is characterized in that, described resilient coating is silicon oxide layer or silicon nitride layer.

3. method as claimed in claim 1 or 2 is characterized in that, the formation method of described resilient coating is time aumospheric pressure cvd SACVD or low-pressure chemical vapor deposition LPCVD or aumospheric pressure cvd APCVD.

4. method as claimed in claim 3 is characterized in that, the thickness of described resilient coating is 100 dusts, 120 dusts and 140 dusts; The tensile stress that has is 200MPa, 250MPa and 300MPa.

5. method as claimed in claim 3 is characterized in that, the thickness of described resilient coating is between 50 dust to 150 dusts; The tensile stress that has is between 100MPa to 500MPa.

6. method as claimed in claim 3 is characterized in that, the formation temperature of described resilient coating is between 0 to 480 degree centigrade.