CN101977058B - Sequential approximation analog to digital converter with digital correction and processing method thereof - Google Patents

The invention discloses a sequential approximation analog to digital converter with digital correction and a processing method thereof aiming at the defect of difficult composition manufacture of a coupling capacitor in the traditional sequential approximation analog to digital converter. The sequential approximation analog to digital converter comprises a main DAC (Digital Analogue Converter), a calibration DAC, a comparer, a control circuit and a storage. The sequential approximation analog to digital converter is characterized in that the main DAC comprises a high-K-bit CDAC (Capacitance Digital Analogue Converter) and a low-N-bit CDAC. Introduced system errors and capacitance matching errors are digitally corrected and eliminated, error voltages corresponding to capacitors in the high-K-bit CDAC are quantized and stored in the storage, and two-digit 0 are added behind the tail of the quantized residual error voltage digital code and participate in the calculation of the error voltages. When normal conversion is carried out, the error voltage digital codes are accumulated and then last two digits are discarded, the remain digital codes are used as the input of the calibration DAC, thus the accuracy of the analog to digital converter is improved.

带数字校正的逐次逼近模数转换器及其处理方法Successive Approximation Analog-to-Digital Converter with Digital Correction and Its Processing Method

技术领域 technical field

本发明属于模拟数字转换技术领域，特别涉及一种模数转换器及其处理方法。The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to an analog-to-digital converter and a processing method thereof.

背景技术 Background technique

逐次逼近模数(A/D，Analog/Digital)转换器的精度较高，功耗很低，尽管转换速度偏慢，但在很多不需要高速转换的场合，如触摸屏控制电路中，逐次逼近模数转换器已经成为一种常用的选择。The successive approximation analog-to-digital (A/D, Analog/Digital) converter has high precision and low power consumption. Although the conversion speed is slow, in many occasions that do not require high-speed conversion, such as touch screen control circuits, the successive approximation analog Digital converters have become a popular choice.

传统的逐次逼近A/D转换器通常采用分段的方式实现，一般有这样几种：(1)高K位采用开关电容阵列，低N位采用电阻串；(2)高K位采用电阻串，低N位采用开关电容阵列；(3)高K位和低N位均采用开关电容阵列。The traditional successive approximation A/D converter is usually implemented in a segmented manner, and there are generally several types: (1) the high K bit uses a switched capacitor array, and the low N bit uses a resistor string; (2) the high K bit uses a resistor string , the low N bit uses a switched capacitor array; (3) both the high K bit and the low N bit use a switched capacitor array.

如果采用单一的电阻串结构，会使得电阻的数目过多，如果采用单一的开关电容阵列结构，则会出现电容值非常大的电容，这些后果不仅会使得芯片面积变得很大，同时也会恶化电阻或者电容之间的匹配度。电阻串构成的子DAC可以保证电路的单调性，但是电阻的匹配度不如电容，因此精度相对较差；开关电容阵列构成的子DAC的精度比电阻串构成的子DAC高，但这种结构却可能使电路出现非单调性或者缺码。另外，对于精度为12位或者更高的逐次逼近A/D转换器来说，即使分两段也会使得电阻的数目过多或电容的取值过大，难以实现低成本高精度的电路。If a single resistor string structure is used, the number of resistors will be too many. If a single switched capacitor array structure is used, capacitors with very large capacitances will appear. These consequences will not only increase the chip area, but also Deteriorating the matching between resistors or capacitors. The sub-DAC composed of resistor strings can guarantee the monotonicity of the circuit, but the matching degree of resistors is not as good as that of capacitors, so the accuracy is relatively poor; the precision of sub-DAC composed of switched capacitor arrays is higher than that of sub-DAC composed of resistor strings, but this structure is not It may cause non-monotonicity or missing codes in the circuit. In addition, for a successive approximation A/D converter with a precision of 12 bits or higher, even if it is divided into two sections, the number of resistors or the value of the capacitor will be too large, making it difficult to realize a low-cost and high-precision circuit.

如果在逐次逼近A/D转换器中出现了上述第(3)种情况所述的两个由开关电容阵列构成的高K位子DAC和低N位子DAC，那么在这两个子DAC之间需要一个电容进行耦合。理想情况下，这个耦合电容C_s不是单位电容C的整数倍，而是一个分数值电容，例如

但是在版图设计时，在保证电容之间的匹配度的前提下，分数值电容是难以实现的。这里需要对单位电容和分数值电容作一说明：绝大多数电容的值都是某个电容C的整数倍，如C，2C，4C，8C，16C，这里的“C”就称为一个单位电容，单位电容的值可以由设计者来决定，通常在100fF～1pF以内；对于分数值电容，它的值就不是单位电容的整数倍，而是分数倍。If the two high-K sub-DACs and low-N-bit sub-DACs composed of switched capacitor arrays described in the above-mentioned case (3) appear in the successive approximation A/D converter, then a sub-DAC is required between the two sub-DACs Capacitors are coupled. Ideally, this coupling capacitance C _s is not an integer multiple of the unit capacitance C, but a fractional value capacitance, for example

But in the layout design, under the premise of ensuring the matching degree between the capacitors, it is difficult to realize the fractional value capacitor. Here we need to explain the unit capacitance and fractional value capacitance: the value of most capacitances is an integer multiple of a certain capacitance C, such as C, 2C, 4C, 8C, 16C, where "C" is called a unit Capacitance, the value of the unit capacitance can be determined by the designer, usually within 100fF ~ 1pF; for the fractional value capacitor, its value is not an integer multiple of the unit capacitance, but a fractional multiple.

发明内容 Contents of the invention

本发明的目的是为了克服现有的逐次逼近模数转换器中耦合电容排版制作困难的缺点，提出了一种带数字校正的逐次逼近模数转换器。The object of the present invention is to propose a successive approximation analog-to-digital converter with digital correction in order to overcome the disadvantage of difficulty in layout making of coupling capacitors in the existing successive approximation analog-to-digital converters.

为了实现上述目的，本发明的技术方案是：In order to achieve the above object, technical scheme of the present invention is:

一种带数字校正的逐次逼近模数转换器，包括主DAC、校准DAC、比较器、控制电路、存储器，比较器的正输入端接共模电压，负输入端接主DAC的输出，其特征在于，所述主DAC包括开关电容阵列构成的高K位CDAC和开关电容阵列构成的低N位CDAC，并且高K位CDAC和低N位CDAC之间通过一个单位电容进行耦合，校准DAC的输出端与主DAC的输出端之间通过一个耦合电容进行耦合。A successive approximation analog-to-digital converter with digital correction, including main DAC, calibration DAC, comparator, control circuit, memory, the positive input terminal of the comparator is connected to the common mode voltage, and the negative input terminal is connected to the output of the main DAC, its characteristics In that, the main DAC includes a high K-bit CDAC composed of a switched capacitor array and a low N-bit CDAC composed of a switched capacitor array, and the high K-bit CDAC and the low N-bit CDAC are coupled through a unit capacitor to calibrate the output of the DAC Coupled between the terminal and the output terminal of the main DAC through a coupling capacitor.

作为上述方案的进一步的改进，为了提高模数转换器的精度并保证一定的单调性，主DAC还包括由电阻串构成的中间M位RDAC。As a further improvement of the above scheme, in order to improve the precision of the analog-to-digital converter and ensure a certain monotonicity, the main DAC also includes an intermediate M-bit RDAC composed of a resistor string.

本发明的另一方面是为了适应上述逐次逼近模数转换器结构的改进，提出了一种与之配套的带数字校正的逐次逼近模数转换器的处理方法，该方法具体包括如下步骤：Another aspect of the present invention is in order to adapt to the improvement of the above-mentioned successive approximation analog-to-digital converter structure, proposes a kind of processing method of the successive approximation analog-to-digital converter with digital correction, this method specifically comprises the following steps:

步骤1：电路上电后，先对高K位CDAC各个电容的残差电压由从高位到低位的顺序依次进行量化，对应的电容在时钟的控制下先接地再接参考电压，比该电容位数低的所有电容，包括低N位CDAC的所有电容，则先接参考电压再接地，而比该电容位数高的所有电容一直接地，比较器的输出对控制电路中的SAR进行控制，而SAR的输出接校准DAC的输入，量化结束时，校准DAC的输出电压与共模电压之差就是对应电容的残差电压；Step 1: After the circuit is powered on, quantify the residual voltage of each capacitor of the high-K bit CDAC in sequence from high to low, and the corresponding capacitor is grounded first and then connected to the reference voltage under the control of the clock. All capacitors with low numbers, including all capacitors of low N-bit CDAC, are first connected to the reference voltage and then grounded, and all capacitors with higher digits than the capacitor are always grounded, and the output of the comparator controls the SAR in the control circuit. The output of the SAR is connected to the input of the calibration DAC. At the end of quantization, the difference between the output voltage of the calibration DAC and the common-mode voltage is the residual voltage of the corresponding capacitor;

步骤2：最高位对应的误差电压等于最高位对应的残差电压除以2；Step 2: The error voltage corresponding to the highest bit is equal to the residual voltage corresponding to the highest bit divided by 2;

高K位中除了最高位以外的各位所对应的误差电压等于该位的残差电压减去比该位高的各位的误差电压之和再除以2；The error voltage corresponding to each bit except the highest bit in the high K bit is equal to the residual voltage of the bit minus the sum of the error voltages of the bits higher than the bit and then divided by 2;

第N位(或上述改进方案中的第M+N位)对应的误差电压等于第N+1位(或上述改进方案中的第M+N+1位)对应的误差电压减去第N+1位(或上述改进方案中的第M+N+1位)对应的残差电压再除以2；The error voltage corresponding to the Nth bit (or the M+Nth bit in the above improved scheme) is equal to the error voltage corresponding to the N+1th bit (or the M+N+1th bit in the above improved scheme) minus the N+th Divide the residual voltage corresponding to 1 bit (or the M+N+1th bit in the above improvement scheme) by 2;

从第1位到第N-1位(或上述改进方案中的第M+N-1位)各位的误差电压等于比该位高一位的误差电压除以2。The error voltage of each bit from bit 1 to bit N-1 (or bit M+N-1 in the above improved scheme) is equal to the error voltage of one bit higher than the bit divided by 2.

从残差电压到误差电压的转换是以数字的方式进行的，并且在校准DAC输出的残差电压数字码末位后面增加两位一起参与运算，这两位均预设为0；The conversion from the residual voltage to the error voltage is carried out digitally, and two digits are added after the last digit of the digital code of the residual voltage output by the calibration DAC to participate in the operation together, and these two digits are preset to 0;

步骤3：进行正常转换时，由SAR确定为1的各位所对应的误差电压数字码被累加起来再舍掉最后两位，以作为校准DAC的输入。Step 3: During normal conversion, the error voltage digital codes corresponding to the bits determined to be 1 by the SAR are accumulated and the last two bits are discarded to serve as the input for calibrating the DAC.

本发明的有益效果：本发明所设计的主DAC分为两段或者三段实现，使得在逐次逼近A/D转换器精度较高时也可以避免使用过多的电阻或者过大的电容；两个开关电容阵列构成的高位CDAC和低位CDAC之间的耦合电容由理想的分数电容改为一个单位电容，避免了分数值电容的制作，提高了整个电容阵列版图的匹配度；使用单位电容进行耦合所引入的系统误差和高位CDAC电容之间的匹配误差均可以通过数字校正技术予以消除；在校准DAC输出的残差电压数字码末位后面增加两位零再参与误差电压的计算，减小了二进制数在运算过程中所带来的误差。Beneficial effects of the present invention: the main DAC designed by the present invention is divided into two sections or three sections, so that when the accuracy of the successive approximation A/D converter is high, the use of too many resistors or too large capacitors can be avoided; The coupling capacitance between the high-order CDAC and the low-order CDAC composed of two switched capacitor arrays is changed from an ideal fractional capacitor to a unit capacitor, which avoids the production of fractional value capacitors and improves the matching degree of the entire capacitor array layout; use unit capacitors for coupling The introduced system error and the matching error between high-order CDAC capacitors can be eliminated by digital correction technology; two zeros are added after the last digit of the residual voltage digital code output by the calibration DAC to participate in the calculation of the error voltage, reducing the The error caused by the binary number in the operation process.

附图说明 Description of drawings

图1为本发明的逐次逼近模数转换器系统框图。Fig. 1 is a system block diagram of the successive approximation analog-to-digital converter of the present invention.

图2为分两段实现的主DAC，校准DAC与比较器的结构示意图。Fig. 2 is a structural schematic diagram of the main DAC realized in two stages, the calibration DAC and the comparator.

图3为量化电容C₈对应的残差电压V_s8的过程示意图。FIG. 3 is a schematic diagram of the process of quantizing the residual voltage V _s8 corresponding to the capacitor C ₈ .

图4为电路实施例一中对输入模拟信号进行采样时的结构示意图。FIG. 4 is a schematic structural diagram of sampling an input analog signal in the first circuit embodiment.

图5为电路实施例一中进行正常转换时的结构示意图。FIG. 5 is a schematic diagram of the structure of the circuit embodiment 1 when normal conversion is performed.

图6为分三段实现的主DAC，校准DAC与比较器的结构示意图。Fig. 6 is a structural diagram of the main DAC, the calibration DAC and the comparator implemented in three sections.

图7为电路实施例二中对输入模拟信号进行采样时的结构示意图。FIG. 7 is a schematic structural diagram of sampling an input analog signal in the second circuit embodiment.

图8为电路实施例二中进行正常转换时的结构示意图。FIG. 8 is a schematic diagram of the structure of the second circuit embodiment when performing normal conversion.

图9为带自校准时DNL和INL的仿真结果。Figure 9 shows the simulation results of DNL and INL with self-calibration.

图10为不带自校准时DNL和INL的仿真结果。Figure 10 shows the simulation results of DNL and INL without self-calibration.

图11为带自校准与不带自校准时SNR和ENOB的仿真结果。Figure 11 shows the simulation results of SNR and ENOB with and without self-calibration.

具体实施方式 Detailed ways

下面结合附图，给出本发明的具体实施例。需要说明的是：实施例中的参数并不影响本发明的一般性。Below in conjunction with accompanying drawing, provide the specific embodiment of the present invention. It should be noted that the parameters in the examples do not affect the generality of the present invention.

本发明的一种带数字校正的逐次逼近模数转换器系统框图如图1所示，包括主DAC、校准DAC、比较器、控制电路、存储器以及数据输出级，比较器的正输入端接共模电压，负输入端接主DAC的输出，主DAC包括开关电容阵列构成的高K位CDAC和开关电容阵列构成的低N位CDAC，并且高K位CDAC和低N位CDAC之间通过一个单位电容进行耦合，校准DAC的输出端与主DAC的输出端之间通过一个耦合电容进行耦合。A system block diagram of a successive approximation analog-to-digital converter with digital correction of the present invention is shown in Figure 1, including a main DAC, a calibration DAC, a comparator, a control circuit, a memory, and a data output stage, and the positive input terminal of the comparator is connected to a common Modulus voltage, the negative input terminal is connected to the output of the main DAC, the main DAC includes a high K-bit CDAC composed of a switched capacitor array and a low N-bit CDAC composed of a switched capacitor array, and a unit is passed between the high K-bit CDAC and the low N-bit CDAC Capacitor coupling, the output terminal of the calibration DAC and the output terminal of the main DAC are coupled through a coupling capacitor.

下面结合两个实施例进行具体说明。The following is a specific description in conjunction with two embodiments.

实施例一：假设主DAC由电容阵列构成的高5位CDAC和电容阵列构成的低4位CDAC两段组成。Embodiment 1: It is assumed that the main DAC is composed of two stages, the upper 5-bit CDAC formed by the capacitor array and the lower 4-bit CDAC formed by the capacitor array.

图2为分两段实现的主DAC，校准DAC与比较器的结构示意图，包括主DAC中高5位的CDAC 101，低4位的CDAC 103，以及9位的校准DAC 104和比较器105。高位CDAC 101与低位CDAC 103之间通过单位电容Cs进行耦合，校准DAC 104的输出与主DAC的输出之间通过电容Cc进行耦合。Fig. 2 is a structural schematic diagram of the main DAC realized in two stages, the calibration DAC and the comparator, including the high 5-bit CDAC 101, the low 4-bit CDAC 103, and the 9-bit calibration DAC 104 and comparator 105 in the main DAC. The high-order CDAC 101 and the low-order CDAC 103 are coupled through the unit capacitor Cs, and the output of the calibration DAC 104 is coupled with the output of the main DAC through the capacitor Cc.

假设高位CDAC 101的各个电容分别为：Assume that the individual capacitors of the high-order CDAC 101 are:

C₈＝(2⁴+ΔC₈)C，C₇＝(2³+ΔC₇)C，C₆＝(2²+ΔC₆)C，C₅＝(2+ΔC₅)C，C₄＝(1+ΔC₄)C，其中ΔC_i是各个电容的误差，C是单位电容。C ₈ =(2 ⁴ +ΔC ₈ )C, C ₇ =(2 ³ +ΔC ₇ )C, C ₆ =(2 ² +ΔC ₆ )C, C ₅ =(2+ΔC ₅ )C, C ₄ = (1+ΔC ₄ )C, where ΔC _i is the error of each capacitor, and C is the unit capacitance.

假设低位CDAC 103的各个电容分别为：C₃＝2³C，C₂＝2²C，C₁＝2C，C₀＝C′₀＝C。Assume that the capacitances of the low-order CDAC 103 are: C ₃ =2 ³ C, C ₂ =2 ² C, C ₁ =2C, C ₀ =C′ ₀ =C.

假设校准DAC 104与主DAC之间的耦合电容为：C_C＝KC，其中K是一个正整数。Assume that the coupling capacitance between the calibration DAC 104 and the main DAC is: C _C =KC, where K is a positive integer.

在以上的假设中，低位CDAC 103的各个电容都是理想的，没有误差。这是因为高位CDAC 101中电容的匹配误差才是影响整个逐次逼近A/D转换器精度的主要因素，因此只需要校正高位CDAC 101中电容的匹配误差。In the above assumptions, each capacitor of the low-level CDAC 103 is ideal without errors. This is because the matching error of the capacitors in the high-order CDAC 101 is the main factor affecting the accuracy of the entire successive approximation A/D converter, so only the matching error of the capacitors in the high-order CDAC 101 needs to be corrected.

除了以上的假设之外，定义C′₄＝C_S||C_LSB＝C_S||16C＝(1+ΔC′₄)C，其中C_LSB是低位CDAC 103电容的总和，“||”表示并联。理想情况下，C_S||C_LSB的值应该等于一个单位电容C，但由于C_S本身就是一个单位电容，因此C_S||C_LSB的值会偏离一个单位电容，该误差用ΔC′₄表示。另外，再定义ΔC_tol＝ΔC′₄+ΔC₄+ΔC₅+ΔC₆+ΔC₇+ΔC₈。 _In addition to _the above assumptions, define C ₄ = C _S || C _LSB = C _S || in parallel. Ideally, the value of C _S ||C _LSB should be equal to a unit capacitance C, but since C _S itself is a unit capacitance, the value of C _S ||C _LSB will deviate from a unit capacitance, and the error is expressed by ΔC′ ₄ express. In addition, redefine ΔC _tol =ΔC′ ₄ +ΔC ₄ +ΔC ₅ +ΔC ₆ +ΔC ₇ +ΔC ₈ .

电路上电后，首先进行自校准，这一步是为了把高位CDAC 101的各个电容所对应的残差电压都量化出来，再通过一定的运算得到各位的误差电压并存储在存储器中，这里的存储器可以是随机存储器(RAM，Random AccessMemory)。After the circuit is powered on, self-calibration is performed first. This step is to quantify the residual voltage corresponding to each capacitor of the high-level CDAC 101, and then obtain the error voltage of each bit through a certain operation and store it in the memory. The memory here Can be random access memory (RAM, Random AccessMemory).

自校正从高位CDAC 101中的最高位C₈开始，图3为量化C₈的残差电压V_r8的过程示意图，其中V_ref是参考电压，V_cm是共模电压，在前一个状态下，C₈接地，其余所有电容接V_ref，比较器105的同相输入端和反相输入端均接V_cm，同时校准DAC 104的输出也为V_cm，此时比较器105反相输入端上的电荷为Self-calibration starts from the highest bit C ₈ in the high bit CDAC 101. Figure 3 is a schematic diagram of the process of quantifying the residual voltage V _r8 of C ₈ , where V _ref is the reference voltage, V _cm is the common-mode voltage, In the previous state, C ₈ is grounded, all other capacitors are connected to V _ref , the non-inverting input terminal and the inverting input terminal of the comparator 105 are both connected to V _cm , and the output of the calibration DAC 104 is also V _cm , at this time the comparator 105 The charge on the inverting input is

Q＝V_cmC₈+(V_cm-V_ref)(C′₄+C₄+…+C₇)Q＝V _cm C ₈ +(V _cm -V _ref )(C′ ₄ +C ₄ +...+C ₇ )

；;

＝V_cm(2⁴+ΔC₈)C+(V_cm-V_ref)(2⁴+ΔC′₄+ΔC₄+…+ΔC₇)C=V _cm (2 ⁴ +ΔC ₈ )C+(V _cm -V _ref )(2 ⁴ +ΔC′ ₄ +ΔC ₄ +...+ΔC ₇ )C

在下一个状态，C₈接V_ref，其余所有电容接地，校准DAC 104的输出为V_cal8，In the next state, C ₈ is connected to V _ref , all other capacitors are grounded, and the output of the calibration DAC 104 is V _cal8 ,

比较器105反相输入端的电压为V_X，此时比较器105反相输入端上的电荷为The voltage at the inverting input terminal of the comparator 105 is V _X , and the charge on the inverting input terminal of the comparator 105 is

Q′＝(V_X-V_ref)C₈+V_X(C′₄+C₄+…+C₇)+(V_X-V_cal)C_C Q'=(V _X -V _ref )C ₈ +V _X (C' ₄ +C ₄ +...+C ₇ )+(V _X -V _cal )C _C

；;

＝(V_X-V_ref)(2⁴+ΔC₈)C+V_X(2⁴+ΔC′₄+ΔC₄+…+ΔC₇)C+(V_X-V_cal8)KC＝(V _X -V _ref )(2 ⁴ +ΔC ₈ )C+V _X (2 ⁴ +ΔC′ ₄ +ΔC ₄ +...+ΔC ₇ )C+(V _X -V _cal8 )KC

由于电荷守恒，Q＝Q′，由此可以得到Due to the conservation of charge, Q=Q', which can be obtained

(( 22 55 ++ KK ++ ΔCΔC toltol )) (( VV cmcm -- VV Xx )) == KK [[ VV cmcm ++ VV refref KK (( ΔCΔC 44 ′′ ++ ΔCΔC 44 ++ .. .. .. ++ ΔCΔC 77 -- ΔCΔC 88 )) -- VV calcal 88 ]]

利用控制电路中的一个在校准周期内工作的9位的逐次逼近寄存器(SAR，Successive Approximation)，采用逐次逼近的方式，可以将C₈对应的残差电压进行量化。量化结束时，V_cm≈V_X，那么Using a 9-bit successive approximation register (SAR, Successive Approximation) in the control circuit that works in the calibration cycle, the residual voltage corresponding to C ₈ can be quantified in a successive approximation manner. At the end of quantization, V _cm ≈ V _X , then

VV calcal 88 == VV cmcm ++ VV refref KK (( ΔCΔC 44 ′′ ++ .. .. .. ++ ΔCΔC 77 -- ΔCΔC 88 ))

C₈的残差电压就是V_cal8与V_cm的差，即再将它除以2就得到最高位的误差电压为

以上两步操作都是用数字的方式完成的。但是在上面的运算中涉及到除以2的运算，对一个二进制数除以2相当于将其右移一位，这会带来一定的误差。比如，将十进制数3对应的二进制数011除以2后得到001，而001对应的十进制数为1。也就是说，用数字的方式进行3除以2的运算后，得到的结果是1，于是就产生了误差。为了减小数字码运算时带来的误差，在校准DAC 104输出的残差电压数字码末位后面补两位一起参与运算，这两位均预设为0。这样，将某个二进制数除以2时所可能丢掉的信息从一定程度上被保留下来，从而提高了运算的精度。残差电压与误差电压都是用补码来进行表达和运算的。The residual voltage of C ₈ is the difference between V _cal8 and V _cm , that is Then divide it by 2 to get the error voltage of the highest bit as

The above two steps are all done digitally. However, the above operation involves dividing by 2. Dividing a binary number by 2 is equivalent to shifting it to the right by one bit, which will bring a certain error. For example, divide the binary number 011 corresponding to the decimal number 3 by 2 to get 001, and the decimal number corresponding to 001 is 1. That is to say, after the operation of dividing 3 by 2 is performed digitally, the result obtained is 1, so an error occurs. In order to reduce the error caused by the digital code operation, two digits are added after the last digit of the residual voltage digital code output by the calibration DAC 104 to participate in the calculation together, and these two digits are preset to 0. In this way, the information that may be lost when dividing a certain binary number by 2 is retained to a certain extent, thereby improving the accuracy of the operation. Residual voltage and error voltage are both expressed and calculated by complement code.

利用相同的方法，可以依次得到C₇、C₆、C₅、C₄所对应的残差电压和误差电压。当需要量化某个电容的残差电压时，该电容在前后两个状态下先接地，再接V_ref；位数比该电容低的所有电容(包括C′₄)则先接V_ref，再接地；而位数比该电容高的所有电容在前后两个状态下一直接地。以下是C₇、C₆、C₅、C₄等四个电容所对应的误差电压的表达式：Using the same method, the residual voltage and error voltage corresponding to C ₇ , C ₆ , C ₅ , and C ₄ can be obtained in sequence. When it is necessary to quantify the residual voltage of a certain capacitor, the capacitor should be grounded first in the two states before and after, and then connected to V _ref ; all capacitors with lower digits than this capacitor (including C′ ₄ ) should be connected to V ref first, and then connected to V _ref ground; and all capacitors with higher digits than this capacitor are directly grounded in the two states before and after. The following is the expression of the error voltage corresponding to the four capacitors C ₇ , C ₆ , C ₅ , and C ₄ :

VV ee 77 == VV rr 77 -- VV ee 88 22 == VV refref 44 KK (( ΔCΔC 44 ′′ ++ .. .. .. ++ ΔCΔC 66 -- 33 ΔCΔC 77 ++ ΔCΔC 88 )) ;;

VV ee 66 == VV rr 66 -- VV ee 77 -- VV ee 88 22 == VV refref 88 KK (( ΔCΔC 44 ′′ ++ .. .. .. ++ ΔCΔC 55 -- 77 ΔCΔC 66 ++ ΔCΔC 77 ++ ΔCΔC 88 )) ;;

VV ee 55 == VV rr 55 -- VV ee 66 -- VV ee 77 -- VV ee 88 22 == VV refref 1616 KK (( ΔCΔC 44 ′′ ++ ΔCΔC 44 -- 1515 ΔCΔC 55 ++ ΔCΔC 66 ++ .. .. .. ++ ΔCΔC 88 )) ;;

VV ee 44 == VV rr 44 -- VV ee 55 -- VV ee 66 -- VV ee 77 -- VV ee 88 22 == VV refref 3232 KK (( ΔCΔC 44 ′′ -- 3131 ΔCΔC 44 ++ ΔCΔC 55 ++ .. .. .. ++ ΔCΔC 88 )) ..

从上面的表达式可以看出，高5位CDAC所对应的5个误差电压既包括了高位CDAC 101中各个电容之间的匹配误差，即ΔC₄～ΔC₈，又包括了用单位电容对高位CDAC 101和低位CDAC 103进行耦合所引入的系统误差，即ΔC′₄。匹配误差和系统误差除了会对高位产生影响外，也会对低位产生影响。在本发明所提出的校正方法中，还提供了低位的误差电压的计算方法，公式如下：It can be seen from the above expression that the five error voltages corresponding to the high-order CDAC 101 not only include the matching errors between the capacitors in the high-order CDAC 101, namely ΔC ₄ ~ ΔC ₈ , but also include The systematic error introduced by the coupling between CDAC 101 and low-order CDAC 103 is ΔC′ ₄ . Matching error and system error will not only affect the high bit, but also affect the low bit. In the correction method proposed by the present invention, the calculation method of the error voltage of the low position is also provided, and the formula is as follows:

VV ee 33 == VV ee 44 -- VV rr 44 22 ,, VV eiei == 11 22 VV ee (( ii ++ 11 )) ,, ii == 0,1,20,1,2

这样，得到了所有9位所对应的误差电压。不过，只有前6位的误差电压需要存储在RAM中，因为后3位的误差电压都等于前一位的误差电压除以2，因此只要知道了V_c3，后面几位的误差电压就都能得到。In this way, the error voltages corresponding to all 9 bits are obtained. However, only the error voltage of the first 6 bits needs to be stored in RAM, because the error voltage of the last 3 bits is equal to the error voltage of the previous bit divided by 2, so as long as V _c3 is known, the error voltage of the next few bits can be get.

当校正周期结束后，电路进入休眠等待状态。当启动信号到达之后，电路开始进入正常的转换周期。首先，需要对输入模拟信号进行采样，采样时，主DAC的所有电容均接输入信号V_in，比较器105的同相输入端接V_cm，反相输入端与输出短接，校准DAC 104的输出为V_cm，主DAC中低位CDAC 103所有电容的上极板也接到V_cm，如图4所示。此时，图中X点和Y点上的电荷分别为：When the calibration cycle is over, the circuit enters a dormant waiting state. When the start signal arrives, the circuit begins to enter the normal conversion cycle. First, the input analog signal needs to be sampled. During sampling, all capacitors of the main DAC are connected to the input signal V _in , the non-inverting input terminal of the comparator 105 is connected to V _cm , the inverting input terminal is short-circuited to the output, and the output of the DAC 104 is calibrated is V _cm , and the upper plates of all capacitors of the low CDAC 103 in the main DAC are also connected to V _cm , as shown in FIG. 4 . At this time, the charges on point X and point Y in the figure are respectively:

Q_X＝(V_cm-V_in)(C₄+…+C₈)＝(V_cm-V_in)(2⁵-1+ΔC₄+…+ΔC₈)C；Q _x =(V _cm -V _in )(C ₄ +...+C ₈ )=(V _cm -V _in )(2 ⁵ -1+ΔC ₄ +...+ΔC ₈ )C;

Q_Y＝(V_cm-V_in)(C′₀+…+C₃)＝(V_cm-V_in)2⁴C。Q _Y =(V _cm -V _in )(C' ₀ +...+C ₃ )=(V _cm -V _in )2 ⁴ C.

接下来，控制电路中的一个在正常转换周期内使能的9位的SAR开始工作，根据这个SAR的输出，将主DAC中的各个电容连接到不同的电位上。对于低位CDAC 103的各个电容，如果对应位为1，则将该电容接到V_ref，否则将其接到地；对于高位CDAC 101的各个电容，如果对应位为1，则将该电容接到V_ref，否则将其接到地。同时，校准DAC 104输出对应的误差电压V_e与V_cm的和，比较器105的同相输入端接V_cm。如图5所示，该图只是一个示例，表示电路在正常转换时可能出现的一种情况。Next, a 9-bit SAR enabled in the normal conversion period in the control circuit starts to work. According to the output of this SAR, each capacitor in the main DAC is connected to different potentials. For each capacitor of the low-order CDAC 103, if the corresponding bit is 1, connect the capacitor to V _ref , otherwise connect it to ground; for each capacitor of the high-order CDAC 101, if the corresponding bit is 1, connect the capacitor to V _ref , otherwise connect it to ground. At the same time, the calibration DAC 104 outputs the sum of the corresponding error voltage V _e and V _cm , and the non-inverting input terminal of the comparator 105 is connected to V _cm . As shown in Figure 5, this figure is only an example and represents a situation that may occur when the circuit is switching normally.

此时，Y点上的电荷变为：(下式V_Y和V_X分别是Y点和X点的电压)At this point, the charge on point Y becomes: (the following formulas V _Y and V _X are the voltages at point Y and point X respectively)

Q′_Y＝(V_Y-V_ref)(D₀C+…+D₃2³C)+V_Y[(1-D₀)C+…+(1-D₃)2³C]Q′ _Y ＝(V _Y -V _ref )(D ₀ C+…+D ₃ 2 ³ C)+V _Y [(1-D ₀ )C+…+(1-D ₃ )2 ³ C]

；;

+V_YC+(V_Y-V_X)C_S +V _Y C+(V _Y -V _X )C _S

由于电荷守恒，Q_Y＝Q′_Y，由此可以得到：Due to the conservation of charge, Q _Y =Q′ _Y , which can be obtained:

VV YY == 1515 -- ΔCΔC 44 ′′ 1616 [[ VV cmcm -- VV inin ++ VV refref (( DD. 33 22 ++ .. .. .. ++ DD. 00 22 44 )) ]] ++ 11 ++ ΔCΔC 44 ′′ 1616 VV Xx

而X点上的电荷则变为：And the charge at point X becomes:

Q′_X＝(V_X-V_ref)(D₄C₄+…+D₈C₈)+V_X[(1-D₄)C₄+…+(1-D₈)C₈]Q′ _X ＝(V _X -V _ref )(D ₄ C ₄ +…+D ₈ C ₈ )+V _X [(1-D ₄ )C ₄ +…+(1-D ₈ )C ₈ ]

；;

+(V_X-V_Y)C_S+(V_X-V_cm-V_e)C_C +(V _X -V _Y )C _S +(V _X -V _cm -V _e )C _C

由于电荷守恒，Q_X＝Q′_X，再将V_Y的表达式代入后可以得到：Due to charge conservation, Q _X ＝Q′ _X , after substituting the expression of V _Y , we can get:

VV inin -- VV refref [[ DD. 44 (( 11 ++ ΔCΔC 44 )) ++ .. .. .. ++ DD. 88 (( 22 44 ++ ΔCΔC 88 )) ++ (( 11 ++ ΔCΔC 44 ′′ )) (( DD. 33 22 ++ .. .. .. ++ DD. 00 22 44 )) ]] ++ KVKV ee 22 55 ++ ΔCΔC toltol == 22 55 ++ KK ++ ΔCΔC toltol 22 55 ++ ΔCΔC toltol (( VV cmcm -- VV Xx ))

而上式中

D_i是9位的SAR输出的某一位的值，即是哪些位为1，就将哪些位对应的误差电压累加起来。在电路的实际工作过程中，误差电压数字码被累加起来后需要再舍掉最后两位。将V_ei的表达式代进去，就可以得到：

And in the above formula

D _i is the value of a certain bit output by the 9-bit SAR, that is, which bits are 1, and the error voltages corresponding to which bits are accumulated. In the actual working process of the circuit, the last two digits need to be discarded after the error voltage digital codes are accumulated. Substituting the expression of V _ei into it, we can get:

由此可见，经过自校正后，最终使得输入电压与一个理想9位DAC的输出电压进行比较，如果输入电压大于理想DAC的输出电压，那么比较器105输出高电平，反之比较器105输出低电平。而高位CDAC 101电容之间的匹配误差和单位耦合电容C_S所引入的系统误差均被消除了。It can be seen that after self-calibration, the input voltage is finally compared with the output voltage of an ideal 9-bit DAC. If the input voltage is greater than the output voltage of the ideal DAC, the output of the comparator 105 is high, otherwise the output of the comparator 105 is low. level. Both the matching error between the high-level CDAC 101 capacitors and the systematic error introduced by the unit coupling capacitor C _S are eliminated.

另外，从以上的推导还可以看出，校准DAC 104与主DAC之间的耦合电容C_C的大小不影响算法的实现。C_C越大，即K越大，可以使得电路能够处理的匹配误差的范围增大，但同时会降低校准DAC的等效精度。可以取C_C等于一个单位电容的大小，即K＝1。In addition, it can also be seen from the above derivation that the size of the coupling capacitor C _C between the calibration DAC 104 and the main DAC does not affect the realization of the algorithm. The larger C _C is, that is, the larger K is, the range of matching errors that the circuit can handle can be increased, but at the same time, the equivalent precision of the calibration DAC will be reduced. C _C can be taken to be equal to the size of a unit capacitance, that is, K=1.

实施例二：为了提高模数转换器的精度并保证一定的单调性，主DAC还可以包括由电阻串构成的中间M位RDAC，其结构示意图如图6所示，包括主DAC中高5位的CDAC 101，中间3位的RDAC 102，低4位的CDAC 103，以及9位校准DAC 104和比较器105。Embodiment 2: In order to improve the accuracy of the analog-to-digital converter and ensure a certain monotonicity, the main DAC may also include an intermediate M-bit RDAC composed of a resistor string. CDAC 101, middle 3-bit RDAC 102, lower 4-bit CDAC 103, and 9-bit calibration DAC 104 and comparator 105.

在RDAC 102中，V_Ri是电阻串中某个电阻(由3-8Decoder A决定，3-8DecoderA的输入信号是D4、D5、D6)靠近地电位一端的电压，V_Ri+1是电阻串中某个电阻(由3-8Decoder B决定，3-8Decoder B的输入信号是D4、D5、D6)靠近V_ref一端的电压。因此，V_Ri和V_Ri+1分别为：In RDAC 102, _VRi is the voltage of a certain resistor in the resistor string (determined by 3-8Decoder A, the input signal of 3-8DecoderA is D4, D5, D6) close to the ground potential, and _VRi+1 is the voltage in the resistor string A certain resistance (determined by 3-8Decoder B, the input signal of 3-8Decoder B is D4, D5, D6) is close to the voltage of V _ref . Therefore, V _Ri and V _Ri+1 are:

VV RiRi == VV refref (( DD. 66 22 ++ DD. 55 44 ++ DD. 44 88 )) ,, VV RiRi ++ 11 == VV RiRi ++ VV refref 22 33 ..

对于主DAC分三段实现的方案，电路的工作原理和过程与主DAC分两段实现时相同。假设高位CDAC 101的各个电容分别为：For the scheme in which the main DAC is implemented in three sections, the working principle and process of the circuit are the same as when the main DAC is implemented in two sections. Assume that the individual capacitors of the high-order CDAC 101 are:

C₁₁＝(2⁴+ΔC₁₁)C，C₁₀＝(2³+ΔC₁₀)C，C₉＝(2²+ΔC₉)C，C₈＝(2+ΔC₈)C，C₇＝(1+ΔC₇)C，其中ΔC_i是各个电容的误差，C是单位电容。C ₁₁ =(2 ⁴ +ΔC ₁₁ )C, C ₁₀ =(2 ³ +ΔC ₁₀ )C, C ₉ =(2 ² +ΔC ₉ )C, C ₈ =(2+ΔC ₈ )C, C ₇ = (1+ΔC ₇ )C, where ΔC _i is the error of each capacitor, and C is the unit capacitance.

假设低位CDAC 103的各个电容分别为：C₃＝2³C，C₂＝2²C，C₁＝2C，C₀＝C′₀＝C。Assume that the capacitances of the low-order CDAC 103 are: C ₃ =2 ³ C, C ₂ =2 ² C, C ₁ =2C, C ₀ =C′ ₀ =C.

假设校准DAC 104与主DAC之间的耦合电容为：C_C＝KC，其中K是一个常数。Assume that the coupling capacitance between the calibration DAC 104 and the main DAC is: C _C =KC, where K is a constant.

除了以上的假设之外，定义C′₇＝C_S||C_LSB＝C_S||16C＝(1+ΔC′₇)C，其中C_LSB是低位CDAC 103电容的总和。理想情况下，C_S||C_LSB的值应该等于一个单位电容C，但由于C_S本身就是一个单位电容，因此C_S||C_LSB的值会偏离一个单位电容，该误差用ΔC′₇表示。另外，再定义ΔC_tol＝ΔC′₇+ΔC₇+ΔC₈+ΔC₉+ΔC₁₀+ΔC₁₁。In addition to the above assumptions, define C' ₇ =C _s ||C _LSB =C _s ||16C=(1+ΔC' ₇ )C, where C _LSB is the sum of the lower CDAC 103 capacitances. Ideally, the value of C _S ||C _LSB should be equal to a unit capacitance C, but since C _S itself is a unit capacitance, the value of C _S ||C _LSB will deviate from a unit capacitance, and the error is expressed by ΔC′ ₇ express. In addition, redefine ΔC _tol =ΔC′ ₇ +ΔC ₇ +ΔC ₈ +ΔC ₉ +ΔC ₁₀ +ΔC ₁₁ .

自校准阶段结束后，得到各位所对应的误差电压分别为：After the self-calibration phase is over, the error voltages corresponding to each bit are obtained as follows:

VV ee 1111 == VV rr 1111 22 == VV refref 22 KK (( ΔCΔC 77 ′′ ++ .. .. .. ++ ΔCΔC 1010 -- ΔCΔC 1111 )) ;;

VV ee 1010 == VV rr 1010 -- VV ee 1111 22 == VV refref 44 KK (( ΔCΔC 77 ′′ ++ .. .. .. ++ ΔCΔC 99 -- 33 ΔCΔC 1010 ++ ΔCΔC 1111 )) ;;

VV ee 99 == VV rr 99 -- VV ee 1010 -- VV ee 1111 22 == VV refref 88 KK (( ΔCΔC 77 ′′ ++ .. .. .. ++ ΔCΔC 88 -- 77 ΔCΔC 99 ++ ΔCΔC 1010 ++ ΔCΔC 1111 )) ;;

VV ee 88 == VV rr 88 -- VV ee 99 -- VV ee 1010 -- VV ee 1111 22 == VV refref 1616 KK (( ΔCΔC 77 ′′ ++ ΔCΔC 77 -- 1515 ΔCΔC 88 ++ ΔCΔC 99 ++ .. .. .. ++ ΔCΔC 1111 )) ;;

VV ee 77 == VV rr 77 -- VV ee 88 -- VV ee 99 -- VV ee 1010 -- VV ee 1111 22 == VV refref 3232 KK (( ΔCΔC 77 ′′ -- 3131 ΔCΔC 77 ++ ΔCΔC 88 ++ .. .. .. ++ ΔCΔC 1111 )) ;;

VV ee 66 == VV ee 77 -- VV rr 77 22 ;;

V ei = 1 2 V e ( i + 1 ) , i＝0，1，2，3，4，5。 V ei = 1 2 V e ( i + 1 ) , i=0,1,2,3,4,5.

进入正常转换阶段后，首先对输入信号进行采样，采样时，主DAC的所有电容均接输入信号V_in，比较器105的同相输入端接V_cm，反相输入端与输出短接，校准DAC 104的输出为V_cm，主DAC中低位CDAC 103所有电容的上极板也接到V_cm，如图7所示。此时，图中X点和Y点上的电荷分别为：After entering the normal conversion stage, the input signal is first sampled. During sampling, all capacitors of the main DAC are connected to the input signal V _in , the non-inverting input terminal of the comparator 105 is connected to V _cm , the inverting input terminal is short-circuited to the output, and the DAC is calibrated The output of 104 is V _cm , and the upper plates of all capacitors of the low CDAC 103 in the main DAC are also connected to V _cm , as shown in FIG. 7 . At this time, the charges on point X and point Y in the figure are respectively:

Q_X＝(V_cm-V_in)(C₇+…+C₁₁)＝(V_cm-V_in)(2⁵-1+ΔC₇+…+ΔC₁₁)C；Q _x =(V _cm -V _in )(C ₇ +...+C ₁₁ )=(V _cm -V _in )(2 ⁵ -1+ΔC ₇ +...+ΔC ₁₁ )C;

Q_Y＝(V_cm-V_in)(C′₀+…+C₃)＝(V_cm-V_in)2⁴C。Q _Y =(V _cm -V _in )(C' ₀ +...+C ₃ )=(V _cm -V _in )2 ⁴ C.

接下来，一个在正常转换周期内使能的12位的逐次逼近寄存器开始工作，根据这个SAR的输出，将主DAC中的各个电容连接到不同的电位上。对于低位CDAC 103的各个电容，如果对应位为1，则将该电容接到V_Ri+1，否则将其接到V_Ri；对于高位CDAC 101的各个电容，如果对应位为1，则将该电容接到V_ref，否则将其接到地。同时，校准DAC 104输出对应的误差电压V_e与V_cm的和，比较器105的同相输入端接V_cm，如图8所示。Next, a 12-bit successive approximation register, enabled during the normal conversion cycle, starts to work, and connects the various capacitors in the main DAC to different potentials according to the output of this SAR. For each capacitor of the low-order CDAC 103, if the corresponding bit is 1, connect the capacitor to _VRi+1 , otherwise connect it to _VRi ; for each capacitor of the high-order CDAC 101, if the corresponding bit is 1, connect the capacitor to V Ri+1; Connect the capacitor to V _ref , otherwise connect it to ground. At the same time, the calibration DAC 104 outputs the sum of the corresponding error voltage V _e and V _cm , and the non-inverting input terminal of the comparator 105 is connected to V _cm , as shown in FIG. 8 .

此时，Y点上的电荷变为：(下式V_Y和V_X分别是Y点和X点的电压)At this point, the charge on point Y becomes: (the following formulas V _Y and V _X are the voltages at point Y and point X respectively)

Q′_Y＝(V_Y-V_Ri+1)(D₀C+…+D₃2³C)+(V_Y-V_Ri)[(1-D₀)C+…+(1-D₃)2³C]Q′ _Y ＝(V _Y -V _Ri+1 )(D ₀ C+…+D ₃ 2 ³ C)+(V _Y -V _Ri )[(1-D ₀ )C+…+(1-D ₃ )2 ^3C ]

；;

+(V_Y-V_Ri)C+(V_Y-V_X)C_S +(V _Y -V _Ri )C+(V _Y -V _X )C _S

由于电荷守恒，Q_Y＝Q′_Y，由此可以得到：Due to the conservation of charge, Q _Y =Q′ _Y , which can be obtained:

VV YY == 1515 -- ΔCΔC 77 ′′ 1616 [[ VV cmcm -- VV inin ++ VV refref (( DD. 66 22 ++ .. .. .. ++ DD. 00 22 77 )) ]] ++ 11 ++ ΔCΔC 77 ′′ 1616 VV Xx

而X点上的电荷则变为：And the charge at point X becomes:

Q′_X＝(V_X-V_ref)(D₇C₇+…+D₁₁C₁₁)+V_X[(1-D₇)C₇+…+(1-D₁₁)C₁₁]Q′ _X ＝(V _X -V _ref )(D ₇ C ₇ +…+D ₁₁ C ₁₁ )+V _X [(1-D ₇ )C ₇ +…+(1-D ₁₁ )C ₁₁ ]

；;

+(V_X-V_Y)C_S+(V_X-V_cm-V_e)C_C +(V _X -V _Y )C _S +(V _X -V _cm -V _e )C _C

由于电荷守恒，Q_X＝Q′_X，再将V_Y的表达式代入后可以得到：Due to charge conservation, Q _X ＝Q′ _X , after substituting the expression of V _Y , we can get:

VV inin -- VV refref [[ DD. 77 (( 11 ++ ΔCΔC 77 )) ++ .. .. .. ++ DD. 1111 (( 22 44 ++ ΔCΔC 1111 )) ++ (( 11 ++ ΔCΔC 77 ′′ )) (( DD. 66 22 ++ .. .. .. ++ DD. 00 22 77 )) ]] -- KVKV ee 22 55 ++ ΔCΔC toltol

== 22 55 ++ KK ++ ΔCΔC toltol 22 55 ++ ΔCΔC toltol (( VV cmcm -- VV Xx ))

上式中

D_i是12位的SAR输出的某一位的值，即是哪些位为1，就将哪些位对应的误差电压累加起来。在电路的实际工作过程中，误差电压数字码被累加起来后需要再舍掉最后两位。将V_ei的表达式代进去，就可以得到：In the above formula

D _i is the value of a certain bit output by the 12-bit SAR, that is, which bits are 1, and the error voltages corresponding to which bits are accumulated. In the actual working process of the circuit, the last two digits need to be discarded after the error voltage digital codes are accumulated. Substituting the expression of V _ei into it, we can get:

VV inin -- VV refref (( DD. 1111 22 ++ .. .. .. ++ DD. 00 22 1212 )) == 22 55 ++ KK ++ ΔCΔC toltol 22 55 ++ ΔCΔC toltol (( VV cmcm -- VV Xx )) ..

由此可见，经过自校正后，最终使得输入电压与一个理想12位DAC的输出电压进行比较，如果输入电压大于理想DAC的输出电压，那么比较器105输出高电平，反之比较器105输出低电平。而高位CDAC 101电容之间的匹配误差和单位耦合电容C_S所引入的系统误差均被消除了。It can be seen that after self-calibration, the input voltage is finally compared with the output voltage of an ideal 12-bit DAC. If the input voltage is greater than the output voltage of the ideal DAC, the output of the comparator 105 is high, otherwise the output of the comparator 105 is low. level. Both the matching error between the high-level CDAC 101 capacitors and the systematic error introduced by the unit coupling capacitor C _S are eliminated.

针对包括由电阻串构成的中间M位RDAC的主DAC的电路进行仿真，得到带自校准与不带校准时电路的微分非线性DNL(Differential Nonlinearity)和积分非线性INL(Integral Nonlinearity)以及信噪比SNR(Signal to NoiseRatio)和有效位数ENOB(Effective Number of Bits)的仿真结果，如图9、图10、图11所示。The circuit of the main DAC including the middle M-bit RDAC composed of resistor strings is simulated, and the differential nonlinearity DNL (Differential Nonlinearity) and integral nonlinearity INL (Integral Nonlinearity) and signal-to-noise of the circuit with self-calibration and without calibration are obtained The simulation results of SNR (Signal to NoiseRatio) and effective number of bits ENOB (Effective Number of Bits) are shown in Figure 9, Figure 10, and Figure 11.

在仿真中，主DAC高位CDAC 101的各个电容分别为：C₁₁＝2⁴(1+mis)，C₁₀＝2³(1-mis)，C₉＝2²(1-mis)，C₈＝2(1-mis)，C₇＝1-mis。这里的mis代表电容的误差。In the simulation, the respective capacitances of the main DAC high CDAC 101 are: C ₁₁ =2 ⁴ (1+mis), C ₁₀ =2 ³ (1-mis), C ₉ =2 ² (1-mis), C ₈ =2(1-mis), C ₇ =1-mis. The mis here represents the error of the capacitance.

低位CDAC 103的各个电容分别为：C₃＝2³(1+mis)，C₂＝2²(1-mis)，C₁＝2(1-mis)，C₀＝C‘₀＝1-mis。The respective capacitances of the low-order CDAC 103 are: C ₃ =2 ³ (1+mis), C ₂ =2 ² (1-mis), C ₁ =2(1-mis), C ₀ =C' ₀ =1- mis.

高位CDAC 101和低位CDAC 103之间的耦合电容为：C_S＝1-mis。The coupling capacitance between the high-order CDAC 101 and the low-order CDAC 103 is: C _S =1-mis.

在对DNL和INL进行仿真时，mis＝13‰，带自校准时，DNL和INL均在±0.5LSB以内，说明电路的精度足以满足要求；若不进行自校准，则DNL和INL分别高达60LSB和±30LSB，这时电路已经完全失效了。在对SNR和ENOB进行仿真时，mis由0变化到13‰，带自校准时，SNR均在73.4dB以上，对应的ENOB均在11.9bit以上；若不进行自校准，则SNR和ENOB会随着失配的增加而急剧减小，当mis＝13‰时，SNR和ENOB分别只有41.6dB和6.6bit。When simulating DNL and INL, mis=13‰, with self-calibration, DNL and INL are within ±0.5LSB, indicating that the accuracy of the circuit is sufficient to meet the requirements; without self-calibration, DNL and INL are as high as 60LSB And ±30LSB, at this time the circuit has completely failed. When simulating SNR and ENOB, the mis changes from 0 to 13‰. With self-calibration, the SNR is above 73.4dB, and the corresponding ENOB is above 11.9bit; without self-calibration, the SNR and ENOB will change with the With the increase of mismatch, it decreases sharply. When mis=13‰, SNR and ENOB are only 41.6dB and 6.6bit respectively.

以上实例仅为本发明的优选例子而已，本发明的使用并不局限于该实例，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above example is only a preferred example of the present invention, and the use of the present invention is not limited to this example. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in this document. within the scope of protection of the invention.