CN102005454B - Silicon on insulator complementary metal oxide semiconductor field effect transistor - Google Patents
- ️Wed Apr 22 2015
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Publication number
- CN102005454B CN102005454B CN201010504649.9A CN201010504649A CN102005454B CN 102005454 B CN102005454 B CN 102005454B CN 201010504649 A CN201010504649 A CN 201010504649A CN 102005454 B CN102005454 B CN 102005454B Authority
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- China Prior art keywords
- effect transistor
- field effect
- compensating basin
- oxide semiconductor
- metal oxide Prior art date
- 2010-10-12 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a silicon on insulator complementary metal oxide semiconductor field effect transistor. The field effect transistor comprises a first compensation area and a second compensation area, wherein the first compensation area is arranged between a source area and a grid area of a second metal oxide semiconductor field effect transistor; the second compensation area is arranged between a drain area and a grid area of the second metal oxide semiconductor field effect transistor; the conductivity type of the first compensation area and the second compensation area is the same as that of the grid area, and the dosage concentration of the first compensation area and the second compensation area is more than that of the grid area. The field effect transistor can reduce the bypass current and improve the performance of the device.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of silicon-on-insulator complementary metal oxide semiconductor field effect transistor.
Background technology
Mos field effect transistor (MOSFET) integrated circuit, based on planar technique, makes multiple MOSFET on a single die, and to be linked together by these MOSFET executive circuit function by interconnection line.The feature of complementary metal oxide semiconductor field effect transistor (CMOS) integrated circuit is exactly that NMOS and PMOS is made on the same chip.CMOS inverter is one of the most basic logic element of CMOS integrated circuit, and CMOS inverter is widely used in integrated circuit (IC) design.
Along with the raising of integrated circuit integrated level, electronic product, more and more to high density and high-performance development, therefore, in much new Application of integrated circuit, ites is desirable to develop the less and CMOS inverter that performance is better of volume.For this reason, NMOS and PNMOS forming cmos device (such as CMOS inverter) is improved to the two-dimensional structure of arranged crosswise by the applicant from traditional one-dimentional structure be arranged side by side according to silicon-on-insulator (SOI) form, wherein, in the active area of NMOS and the active area of PNMOS, gate regions is shared; Thus reduce device architecture, and improve device performance.
Specifically please refer to Fig. 1 to Fig. 3, wherein, Fig. 1 shows the schematic diagram of the domain structure of existing cmos device, and Fig. 2 shows the sectional view of the cmos device shown in Fig. 1 along dotted line A, and Fig. 3 shows the sectional view of the cmos device shown in Fig. 1 along dotted line B.
Composition graphs 1 to Fig. 3 can find out, the CMOS structure shown in Fig. 1 comprises MOS (such as PMOS) transistor shown in Fig. 2, and the 2nd MOS (such as NMOS) transistor shown in Fig. 2; Wherein, the PMOS transistor shown in Fig. 2 and the nmos pass transistor common gate polar region 1 shown in Fig. 3; Further, in the plane shown in Fig. 1, the drain region 5 of the source area 2 of PMOS, the source area 3 of NMOS, the drain region 4 of PMOS and NMOS is furnished with successively around described gate regions 1.Further, source area 2 and drain region 4 are doped to p+, and source area 3 and drain region 5 are doped to n+, and active area 1 is doped to p-using the common gate regions as the first MOS transistor and the second MOS transistor.
Detailed, mos transistor structure shown in Fig. 2 is the structure of a kind of silicon-on-insulator (SOI); Wherein, the first MOS transistor is arranged in bottom insulator 30 on a substrate 20, and source area 2 arranges source electrode, drain region 4 arranges source electrode, gate regions 1 arranges gate electrode.The structure of the second MOS transistor shown in Fig. 3 and first MOS transistor of Fig. 2 similar, second MOS transistor is arranged in bottom insulator 30 on a substrate 20, and source area 3 arranges source electrode, drain region 5 arranges drain electrode, gate regions 1 arranges gate electrode.
When being applied to the input voltage on gate electrode and being 0V (being input as low level), because the first MOS transistor is PMOS transistor, therefore can pass through the hole conduction of gate regions 1, and the second MOS transistor is nmos pass transistor, so the non-conducting of NMOS.When being applied to the input voltage on gate electrode and being threshold voltage (being input as high level) being greater than grid, the first MOS transistor (PMOS transistor) non-conducting, and the second MOS transistor (nmos pass transistor) conducting.
Fig. 4 shows the current diagram of the CMOS inverter shown in Fig. 1.The electric current of CMOS inverter comprises three paths: the electric current I ds-n in the electric current I ds-p from top to bottom along A direction, the horizontal direction along B direction and from source area 2 (p+) to the gate regions 1 (bottom p-) of PMOS again to the by-pass current I of the drain region 5 (n+) of NMOS f.Be understandable that, designer wishes farthest to reduce this by-pass current I f, because this by-pass current I fdevice performance can be affected and increasing circuit power consumption.
Summary of the invention
The invention provides a kind of silicon-on-insulator complementary metal oxide semiconductor field effect transistor, to reduce by-pass current I f, and then reduce the power consumption of Digital Logical Circuits.
For solving the problems of the technologies described above, the invention provides a kind of silicon-on-insulator complementary metal oxide semiconductor field effect transistor, comprise: the first mos field effect transistor of the first conduction type, and the second mos field effect transistor of the second conduction type, first mos field effect transistor and the second mos field effect transistor common gate polar region, and the source area of the first mos field effect transistor is furnished with successively around gate regions, the source area of the second mos field effect transistor, the drain region of the first mos field effect transistor, and second drain region of mos field effect transistor, also comprise the first compensating basin and the second compensating basin, between the source area that described first compensating basin is arranged at the second mos field effect transistor and gate regions, between the drain region that described second compensating basin is arranged at the second mos field effect transistor and gate regions, first compensating basin is identical with the conduction type of gate regions with the second compensating basin, and, the doping content of the first compensating basin and the second compensating basin is greater than the doping content of gate regions.
In described silicon-on-insulator complementary metal oxide semiconductor field effect transistor, described first mos field effect transistor is P-type mos field-effect transistor, and described second mos field effect transistor is N-type mos field effect transistor.
In described silicon-on-insulator complementary metal oxide semiconductor field effect transistor, described gate regions is doped with p type impurity ion.Described first compensating basin and the second compensating basin are mixed with boron ion.Source area and the drain region of described second mos field effect transistor are mixed with arsenic ion.
In described silicon-on-insulator complementary metal oxide semiconductor field effect transistor, described first compensating basin and the second compensating basin utilize angled ion implantation process to be formed.The Implantation Energy of described angled ion implantation process is 10KeV ~ 20KeV.The implantation dosage of described angled ion implantation process is 1 × 10 13/ cm 2~ 9 × 10 13/ cm 2.The implant angle of described angled ion implantation process is 20 degree ~ 40 degree.
Owing to have employed above technical scheme, compared with prior art, the present invention has the following advantages:
The present invention arranges the first compensating basin between the source area and gate regions of the second mos field effect transistor, and the second compensating basin is set between the drain region and gate regions of the second mos field effect transistor, described first compensating basin is identical with the conduction type of gate regions with the second compensating basin, and, described first compensating basin and the second compensating basin doping content are greater than the doping content of gate regions, to increase the forward cut-in voltage V of p-n junction f, thus reduce by-pass current If, and then reduce the power consumption of Digital Logical Circuits, improve the performance of device.In addition, the present invention utilizes angled ion implantation process to form described first compensating basin and the second compensating basin, and this angled ion implantation process is simple and convenient.
Accompanying drawing explanation
Fig. 1 shows the schematic diagram of the domain structure of existing cmos device.
Fig. 2 shows the sectional view of the cmos device shown in Fig. 1 along dotted line A.
Fig. 3 shows the sectional view of the cmos device shown in Fig. 1 along dotted line B.
Fig. 4 shows the current diagram of the CMOS inverter shown in Fig. 1.
Fig. 5 shows the schematic diagram of the domain structure of cmos device according to the preferred embodiment of the invention.
Fig. 6 shows the sectional view of the cmos device shown in Fig. 5 along dotted line A '.
Fig. 7 shows the sectional view of the cmos device shown in Fig. 5 along dotted line B '.
Embodiment
Mention in the introduction, the electric current of CMOS inverter comprises three paths: the electric current I ds-n in the electric current I ds-p from top to bottom along A direction, the horizontal direction along B direction and from source area (p+) to the gate regions (bottom p-) of PMOS again to the by-pass current I of the drain region (n+) of NMOS f.This by-pass current I fdevice performance can be affected and increasing circuit power consumption.Even if the voltage V applied dDlower than the forward cut-in voltage V of p-n junction f, this by-pass current I fremain disadvantageous.Wherein, the forward cut-in voltage V of this p-n junction frefer to that the charge carrier (carrier) of biased p-n junction starts the extensive voltage injecting (injection), the forward cut-in voltage V of described p-n junction fclose to built-in voltage (built-in voltage) V bi, wherein, this built-in voltage V biequal V fNwith V fPdifference (this is because p district is different with the Fermi level in n district).
Be understandable that, higher in the doping content on p-n junction both sides, the forward cut-in voltage V of p-n junction fhigher, accordingly, by-pass current I flower.For common n+p-knot, the forward cut-in voltage V of its p-n junction fbe approximately 0.75V; And for n+p+ knot, the forward cut-in voltage V of its p-n junction fcan up to 0.85V.Further, the forward cut-in voltage V of this p-n junction freduce along with the rising of temperature, such as, when temperature is elevated between 300K to 400K, it approximately can reduce 0.25V or more.This means, by-pass current I frising along with temperature is sharply increased.Therefore, this by-pass current I is reduced as much as possible f, be very necessary.
Core concept of the present invention is, a kind of silicon-on-insulator complementary metal oxide semiconductor field effect transistor is provided, invention increases the first compensating basin and the second compensating basin, between the source area that described first compensating basin is arranged at the second mos field effect transistor and gate regions, between the drain region that described second compensating basin is arranged at the second mos field effect transistor and gate regions, described first compensating basin is identical with the conduction type of gate regions with the second compensating basin, and, the doping content of described first compensating basin and the second compensating basin is greater than the doping content of described gate regions, to increase the forward cut-in voltage V of p-n junction f, thus reduce by-pass current I f, and then reduce the power consumption of Digital Logical Circuits, improve the performance of device.
5 to Fig. 7 describes the preferred embodiments of the present invention with reference to the accompanying drawings.
Wherein, Fig. 5 shows the schematic diagram of the domain structure of cmos device according to the preferred embodiment of the invention, and Fig. 6 shows the sectional view of the cmos device shown in Fig. 5 along dotted line A ', and Fig. 7 shows the sectional view of the cmos device shown in Fig. 5 along dotted line B '.
Composition graphs 5 to Fig. 7 can find out, the CMOS structure shown in Fig. 5 comprises the first MOS transistor shown in Fig. 6, and the second MOS transistor shown in Fig. 7; In the present embodiment, the first MOS transistor is PMOS transistor, and the second MOS transistor is nmos pass transistor.
Wherein, the PMOS transistor shown in Fig. 6 and the nmos pass transistor common gate polar region 10 shown in Fig. 7; Further, in the plane shown in Fig. 5, the drain region 50 of the source area 20 of PMOS, the source area 30 of NMOS, the drain region 40 of PMOS and NMOS is furnished with successively around described gate regions 10.In addition, this silicon-on-insulator complementary metal oxide semiconductor field effect transistor also comprises the first compensating basin 60 and the second compensating basin 70, described first compensating basin 60 is arranged between the source area 30 of nmos pass transistor and gate regions 10, described second compensating basin 70 is arranged between the drain region 50 of nmos pass transistor and gate regions 10, described first compensating basin 60 is identical with the conduction type of gate regions 10 with the second compensating basin 70, further, the doping content of the first compensating basin 60 and the second compensating basin 70 is greater than the doping content of gate regions 10.
Detailed, active area 20,10,40 constitutes the active area of the first MOS transistor, and active area 30,10,50 constitutes the active area of the second MOS transistor.And, in the present embodiment, active area 20,40 is doped to p+ using as the source area of the first MOS transistor and drain region, active area 30,50 is doped to n+ using as the source area of the second MOS transistor and drain region, and active area 10 is doped to p-using the common gate regions as the first MOS transistor and the second MOS transistor.Described first compensating basin 60 and the second compensating basin 70 are doped to p-type.
Compared with prior art, because the doping content of described first compensating basin 60 and the second compensating basin 70 is higher than the doping content of gate regions 10, and, the doping content of the first compensating basin 60 and the second compensating basin 70 is lower than the doping content of the source/drain region of the second MOS transistor, namely the first compensating basin 60 and the second compensating basin 70 are doped to p-type, therefore, the forward cut-in voltage V of p-n junction fbe the doping content depending on p-type doped region and n+ type doped region, instead of depend on p-type doped region and n+ type doped region.Prove through present inventor's long-term experiment, adopt structure provided by the present invention, the forward cut-in voltage V of described p-n junction fcan about 100mV be increased, thus reduce by-pass current I greatly f, and then reduce the power consumption of Digital Logical Circuits.
Further, refer to Fig. 6, shown mos transistor structure is the structure of a kind of silicon-on-insulator (SOI); Wherein, first MOS transistor is arranged in bottom insulator 300 on the substrate 200, and source area 20 arranges source electrode 220, drain region 40 arranges source electrode 240, gate regions 10 arranges grid oxic horizon, and on grid oxic horizon, arranges gate electrode 210.
Referring now to Fig. 7, the structure of shown MOS transistor is a kind of structure of silicon-on-insulator; More particularly, second MOS transistor is arranged in bottom insulator 300 on the substrate 200, and source area 30 arranges source electrode 230, drain region 50 arranges drain electrode 250, gate regions 10 arranges grid oxic horizon, and on grid oxic horizon, arranges gate electrode 210.Further, the first compensating basin 60 is arranged between the source area 30 of the second MOS transistor and gate regions 10, and the second compensating basin 70 is arranged between the drain region 50 of the second MOS transistor and gate regions 10.In the present embodiment, described first compensating basin 60 and the second compensating basin 70 are positioned at immediately below described gate electrode 210.
In the present embodiment, the first compensating basin 60 and the second compensating basin 70 are mixed with the boron ion of p-type, and the source area 30 of the second MOS transistor and drain region 50 are mixed with the arsenic ion of N-shaped.Certainly, described first compensating basin 60 and the second compensating basin 70 also can mix other p-type foreign ion.
Specifically, this first compensating basin 60 and the second compensating basin 70 are formed simultaneously, and counter doping (Dual Counter Doping, DCD) technique can be utilized to form the first compensating basin 60 and the second compensating basin 70.Preferably, angle-tilt ion can be utilized to inject formation first compensating basin 60 and the second compensating basin 70, this angle-tilt ion is injected simple, only need by a step angled ion implantation process, boron ion can be made to spread fast in the horizontal direction, thus between n+ type doped region and p-type doped region, form the p-type doped region of intermediate doping concentration, and then make the forward cut-in voltage V of p-n junction fdetermined by the doping content of p-type doped region and n+ type doped region, to increase the forward cut-in voltage V of p-n junction f, reduce by-pass current I f.
In the present embodiment, when forming source area 30 and the drain region 50 of described second MOS transistor, the implantation dosage adopted can 1 × 10 15/ cm 2to 9 × 10 15/ cm 2between.Preferably, the Implantation Energy of described angled ion implantation process lower than the Implantation Energy of described arsenic ion, to guarantee that described angled ion implantation process can not affect the formation of source area and drain region.Preferably, the implantation dosage of described angled ion implantation process can 1 × 10 13/ cm 2to 9 × 10 13/ cm 2between.
In the present embodiment, the doping content of described first compensating basin 60 and the second compensating basin 70 is unsuitable too high, to prevent from causing due to too high doping content occurring interband Tunneling Phenomenon (BTBT).Preferably, the Implantation Energy of described angled ion implantation process is preferably between 10KeV to 20KeV.
In the present embodiment, the implant angle of described angled ion implantation process can between 20 degree 40 degree.Preferably, the implant angle of described angled ion implantation process is 30 degree.
Certainly, above-mentioned numerical value is not intended to limit the present invention, and those skilled in the art also according to the requirement on devices of reality, can adjust the Implantation Energy of described angled ion implantation process, implantation dosage and implant angle accordingly.
It should be noted that, although in an embodiment, in order to form the first compensating basin 60 and the second compensating basin 70, need to carry out extra boron ion implantation technology, this will cause threshold voltage V tslight rising; But this can't affect the normal operation of CMOS inverter, but can very effective reduction leakage current, and then reduce the power consumption of Digital Logical Circuits.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a silicon-on-insulator complementary metal oxide semiconductor field effect transistor, comprising: the first mos field effect transistor of the first conduction type, and the second mos field effect transistor of the second conduction type; first mos field effect transistor and the second mos field effect transistor common gate polar region (10), and the source area (20) of the first mos field effect transistor is furnished with successively around gate regions (10), the source area (30) of the second mos field effect transistor, the drain region (40) of the first mos field effect transistor, and second drain region (50) of mos field effect transistor, it is characterized in that, also comprise the first compensating basin (60) and the second compensating basin (70), described first compensating basin (60) is arranged between the source area (30) of the second mos field effect transistor and gate regions (10), described second compensating basin (70) is arranged between the drain region (50) of the second mos field effect transistor and gate regions (10), first compensating basin (60) is identical with the conduction type of gate regions (10) with the second compensating basin (70), described first compensating basin (60) and the second compensating basin (70) are p-type doping, and, the doping content of described first compensating basin (60) and the second compensating basin (70) is greater than the doping content of gate regions (10).
2. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 1, it is characterized in that, described first mos field effect transistor is P-type mos field-effect transistor, and described second mos field effect transistor is N-type mos field effect transistor.
3. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 2, it is characterized in that, described gate regions (10) are doped with p type impurity ion.
4. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 3, it is characterized in that, described first compensating basin (60) and the second compensating basin (70) are mixed with boron ion.
5. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 4, it is characterized in that, source area (30) and drain region (50) of described second mos field effect transistor are mixed with arsenic ion.
6. the silicon-on-insulator complementary metal oxide semiconductor field effect transistor as described in claim 1 or 5, is characterized in that, described first compensating basin (60) and the second compensating basin (70) utilize angled ion implantation process to be formed.
7. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 6, it is characterized in that, the Implantation Energy of described angled ion implantation process is 10KeV ~ 20KeV.
8. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 6, it is characterized in that, the implantation dosage of described angled ion implantation process is 1 × 10 13/ cm 2~ 9 × 10 13/ cm 2.
9. silicon-on-insulator complementary metal oxide semiconductor field effect transistor as claimed in claim 6, it is characterized in that, the implant angle of described angled ion implantation process is 20 degree ~ 40 degree.
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| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
| CN101593772A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Mos transistor and forming method thereof |
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| JP4515549B2 (en) * | 1999-03-12 | 2010-08-04 | 誠 石田 | Semiconductor element and semiconductor sensor |
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* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690056B1 (en) * | 1999-04-06 | 2004-02-10 | Peregrine Semiconductor Corporation | EEPROM cell on SOI |
| CN1815740A (en) * | 2004-12-16 | 2006-08-09 | 三星电子株式会社 | Thin film transistor, inverter, logic device, and method of manufacturing semiconductor device |
| CN101593772A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Mos transistor and forming method thereof |
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