CN102135859A - Flash memory card used for transmitting differential data - Google Patents

Conventionally, a flash memory card transfers data via one or more clocked serial data lines (clock serial data lines), i.e., serial data is transferred via each data line according to a clock signal provided by a single clock line. Therefore, the data transfer rate of the conventional flash memory card is limited by the host clock rate (host clock rate). For example, FIG. 1A shows an interface between a conventional Multimedia Memory Card (MMC)110 and a conventional host device 130 (i.e., an electronic device such as a digital camera or MP3 player). The host device 130 includes a socket 131 and a host memory card controller 120 for communicating with the multimedia memory card 110. The host memory card controller 120 includes a multimedia memory

121, a multimedia memory card protocol controller (processor) 122, and an

123. Meanwhile, the multimedia memory card 110 includes a multimedia memory

111, a multimedia memory card protocol controller (processor) 112, and a memory array 113.

The multimedia

121 and 111 provide the same basic functions for the host card controller 120 and the multimedia card 110, respectively, i.e., the multimedia card specific control signal CTRL and data signal DAT from the multimedia

122 and 112, respectively, are converted into the clock command signal CMD and the serial data signal SDAT, respectively, which can be transmitted between the host card controller 120 and the multimedia card 110 through the

150. The serial data signal SDAT and the clock command signal CMD are clocked by a clock signal CLK generated by the multimedia memory

121. The multimedia

121 and 111 also convert the received serial data signal SDAT and clock command signal CMD into a data signal DAT and a status signal ST specific to the multimedia card, respectively. During these data transitions, the

121 and 111 provide serial to parallel (serial to parallel) conversion of the input serial data signal SDAT and clock command signal CMD and parallel to serial (parallel to serial) conversion to produce the output serial data signal SDAT and clock command signal CMD, to perform frame detection (frame detection) to ensure correct read/write operations of the memory array 113, and to perform error checking (typically Cyclic Redundancy Check (CRC) to check the serial data signal SDAT and clock command signal CMD).

The multimedia

122 and 112 in the host card controller 120 and the multimedia card 110, respectively, perform appropriate operations in response to the multimedia card-specific control signal CTRL, the status signal ST, and the data signal DAT. The main difference between the multimedia

122 in the host card controller 120 and the multimedia

112 in the multimedia card 110 is that the multimedia

122 operates under the control of the

123 to request read and write operations of the multimedia card 110, and the multimedia

112 responds to those read and write requests by controlling the memory array 113. The multimedia memory card communication protocol is described in more detail in the multimedia memory card specification of version 3.31.

To perform data transfer between the host memory card controller 120 and the multimedia memory card 110, the multimedia memory card 110 is first inserted into the socket 131 (this insertion process is not shown in FIG. 1A for clarity of description) to initialize the multimedia memory card 110. The

123 instructs the multimedia

122 to provide appropriate multimedia card-specific control signals CTRL (e.g., to perform a read operation) and appropriately formatted data signals DAT (e.g., read addresses) to the multimedia

121 to generate multimedia card-specific command signals CMD and serial data signals SDAT (clocked by the clock signal CLK). The

123 may generally be considered as a bridge between host-specific communications and memory card-specific communications.

The multimedia

111 on the multimedia memory card 110 receives the command signal CMD and the serial data signal SDAT and converts these signals back to the appropriate status signal ST (e.g., read operation) and data signals (e.g., read address). With respect to these signals, the multimedia

112 performs a read or write operation on the memory array 113 and generates an appropriate response via the control signal CTRL (e.g., read success) and the data signal DAT (e.g., read data). The multimedia

111 converts these signals into a clock command signal CMD and a serial data signal SDAT, which are sent to the multimedia

121 on the host card controller 120, which in turn converts the clock command signal CMD and the serial data signal SDAT into an appropriate status signal ST (e.g., valid read data) and data signal DAT (e.g., read data). Finally, the multimedia

122 provides acknowledgement information and/or data signals from the status signal ST and the data signal DAT to the host device 130 (directly or through the application switch 123).

For example, fig. 1B shows the mechanical appearance specifications of a

110A of version 3.31 (i.e., the

110A conforms to the multimedia memory card specification of version 3.31). The

110A includes 7 contact pads (pins) and a pin assignment table as shown in Table 1 below.

As shown in Table 1,

3, 4, and 6 are power pins and are prepared to receive operating voltages VSS1, VDD, and VSS2, respectively.

2 is an input/output (I/O) pin for receiving and responding to the clock command signal CMD, and

5 is for receiving the clock signal CLK. Finally,

7 is an input/output (I/O) pin for transferring data to and from the

110A (

1 is not used in the multimedia memory card specification of version 3.31). Therefore, since the

110A only includes a single data pin (pin 7), the only way to increase the data transmission rate is by increasing the frequency of the clock signal CLK provided at

5. However, the maximum clock frequency of the host controller of the multimedia memory card is generally limited to 20 megahertz (MHz) due to the attenuation of the signal transmitted to the multimedia memory card bus caused by propagation delay (propagation delays) and parasitics (e.g., stray capacitance and contact resistance). Therefore, the maximum data transfer rate of the multimedia memory card is 2.5 MB/sec.

To overcome this data bandwidth limitation, the latest multimedia memory card specification 4.0 increases the pin count in the mechanical form factor. FIG. 1C shows the mechanical specifications of the

110B of the multimedia memory card specification 4.0, which has conventional pin assignments, listed in Table 2 below.

The

110B includes all the pins (as shown in FIG. 1B) of the

110A, and 6 additional pins 8-13 are added to provide additional data paths. Also,

1 is not used in the multimedia memory card specification of version 3.31, and is also used to provide the data path for the

110B of version 4.0. The pin assignment for the

110B of version 4.0, as shown in FIG. 1C, provides an 8-bit (bit) wide data bus capable of a data bandwidth of 52 MB/sec and a host clock frequency of 52 MHz.

Fig. 2A is a flow chart illustrating a conventional host performing routine memory card detection, such as a pc host, when a memory card is inserted into a slot, such as by detecting a memory Card Detect (CD) pin, which is pulled up (pullhigh) through a resistor of a secure digital memory card or a mechanical switch actuation feature on a multimedia/secure digital memory card, in

200. The host sends a sequence of commands including the CMD55 command to the inserted memory card in

202. if the memory card does not properly respond to such a CMD55 command in

204, then the inserted memory card is a multimedia memory card, rather than a secure digital memory card. In this example, a sequence of commands including the CMD1 command is sent to the multimedia card in

206, and the multimedia card is initialized with a sequence of commands, such as a sequence of commands for the host to read configuration registers located on the multimedia card in

208, and the host can then communicate with the multimedia card using the 7 pins shared by the multimedia card.

If the inserted memory card properly responds to the CMD55 command,

204, the inserted memory card may be a secure digital memory card, and then a command including the step command ACMD41 is further sent to the inserted memory card,

210, if the memory card does not properly respond to the step command ACMD41,

212, the memory card is failed,

214.

Assuming that the memory card properly responds to the ACMD41 command,

212, the memory card is a secure digital memory card, and then the secure digital memory card is initialized by a serial command, such as the host can read configuration registers (configuration registers) on the secure digital memory card,

216, the host uses 9 pins of the secure digital memory card interface to communicate with the secure digital memory card, the host can use one or more than four data signal lines of the secure digital memory card interface to communicate, depending on the environment of communication (such as data structure, quality of memory card slot connection, etc.), and the data stored in the secure digital memory card can be encrypted (encrypted) by a high-level security protocol.

Fig. 2B is a flow diagram illustrating a conventional routine detection response performed by the secure digital memory card, after being inserted into the host slot and powered on, the secure digital memory card is powered through the metal contact pads,

220, and then a memory card initialization routine is initiated,

222, which may include various internal self-checks, and the controller within the secure digital memory card will execute these routines, initiate an external interface, and then wait (and respond) for a command from the host. The secure digital memory card controller in the memory card waits for a command CMD55 from the host,

224, and a command ACDM41 from the host,

226, and then responds with an Operating Conditions Register (OCR) to the host,

228. At this time, the SD card waits for further commands from the host, in

230, all 9 pins of the SD card interface are used.

For example, FIG. 3 shows a secure digital

38 receiving a multimedia memory card (MMC card)32, a secure digital memory card (SD card)30, or a very high speed secure digital memory card (VSD card)34, the

38 including a legacy secure digital memory

39 that detects and receives either the secure

30 or the

32. When the ultra-high

34 is inserted, the SD

39 detects a card as a SD card and sets the ultra-high

34 as a SD card operating on the standard 9 pins and the

36.

The

32 has only 7 metal pads, so the digital

36 uses 2 fewer wires than the secure

30, in other words, the secure

30 has two additional metal pads, which are not included in the

32, specifically, one additional metal pad is added on the edge of the secure

30 forming the bevel, and the other additional metal pad is added on the other side of the 7 metal pads. The ultra-high speed secure

34 has the same 9-pad configuration as the secure

30 and can communicate with the secure digital

38 using standard secure digital memory card interfaces and protocols via the secure digital

36.

FIG. 4 shows an extended ultra-high speed

42 that can receive the

32, the

30, or the ultra-high

34. The extended ultra-high speed secure digital

42 is an ultra-high speed secure memory card host that detects and receives the

32, the secure

30, or the ultra-high speed secure

34. When the

32 is inserted, the extended ultra-high speed secure digital

42 communicates with the protocol using the multimedia memory card pins using the 7 pins of the ultra-high speed secure digital

40; when the

30 is inserted, the

42 uses 9 pins of the

40 to communicate with the protocol using the SD pins.

When the ultra-high-speed secure

34 is inserted, the ultra-high-speed secure digital memory

41 of the extended ultra-high-speed secure digital

42 detects an ultra-high-speed secure digital memory card and sets the ultra-high-speed secure

34 to operate in an extended mode, and performs transmission through the ultra-high-speed secure digital

40 using a high-speed serial bus standard such as a Universal Serial Bus (USB). Higher bandwidth data transfers may also be made via the ultra-high speed secure digital

40 using a serial bus standard such as universal serial bus, IEEE1394, SATA or PCI Express.

The ultra-high speed

34 has the same configuration of 9 pads as the

30, but includes an internal controller (not shown) that can couple an internal serial bus controller to the pads instead of the normal digital memory card controller. For example, when the ultra-high speed secure

34 is operating in the extended ultra-high speed secure digital memory card mode, a USB controller inside the ultra-high speed secure

34 may be coupled to the metal pads.

FIG. 6 is a flow chart illustrating the routine detection response of the ultra-high speed SD card executed by the ultra-high speed SD card. When inserted into the host slot and powered on, the ultra-high speed secure digital memory card is powered through the metal contact pads,

280, and then a memory card initialization routine is initiated,

282, which may include various internal self tests, the controller within the ultra-high speed secure digital memory card will execute these routines, initiate the external interface, and then wait for a command from the host, if it is a single mode memory card, then wait for the host to switch to the same mode for communication, and wait for a CMD55 command from the host if it is not a single mode memory card,

284.

When the CMD55 command is received from the host, the controller waits for the ACMD1 command from the host,

286, and the ultra-high speed SD card responds to the ACMD1 command from the host by indicating the available extended serial bus protocol supported by the card,

288, and the host selects an available protocol from the list that is also supported by the host, and the card changes its bus transmitter to connect one of the extended serial bus protocol processors to the 9 pins of a portion of the SD card,

290, which may support, for example, a universal serial bus.

The host sends a command to the ultra high speed secure digital memory card indicating the protocol used,

292, the ultra high speed secure digital memory card will then initialize the selected protocol processor and couple it to the appropriate pins of the ultra high speed secure digital memory card bus, and the ultra high speed secure digital memory card will then receive further commands from the host,

294.

FIG. 7 is a diagram of a

51 having an ultra-high speed SD

50 that supports extended mode communication, and an ultra-high speed SD

50 into which a

32, a

30, or an ultra-high

34 may be inserted into the

51, each of which will operate in a respective standard mode.

The

51 has a processor system 68 for executing various programs including a memory card manager, a bus scheduler, etc., and a multi-purpose bus interface (USB) system 53 for processing data from the host processor system 68 using various protocols. The processor 56 processes data by using the SD card protocol and inputs and outputs data on the SD card data signal line in the SSC

50. Other protocols for communication with the ultra-high speed secure digital memory

50 are selected through the multipurpose bus switch 52 to operate with the appropriate protocol processor.

The contact pins in the ultra high speed secure digital memory

50 are connected to the multipurpose bus switch 52 and the secure digital memory card protocol processor 56. A transmitter (not shown) located in the multipurpose bus switch 52 buffers data from and to paired transmit and receive differential data signal lines located in extended protocol metal contacts such as peripheral component interconnect express (pci express), Firewire (Firewire) IEEE1394, serial attached small computer systems interface (serial attached SCSI), and serial advanced attachment technology (SATA), even earlier Multimedia Memory Cards (MMC).

When routine initialization by the host processor system 68 determines that the inserted memory card is a multimedia memory card, the multimedia memory card protocol processor 58 is enabled to communicate with the

32 inserted into the ultra-high speed sd memory

50 and the sd memory card protocol processor 56 is disabled. When the host processor system 68 determines that the inserted memory card is a multimedia memory card, the

54 sets the multi-purpose bus switch 52 to connect the MSD

50 to the multimedia memory card protocol processor 58; when the inserted memory card is the secure

30, the secure digital memory card protocol processor 56 continues to communicate with the memory card after initialization is complete.

When routine initialization is performed by the host processor system 68 and the inserted memory card is determined to be an ultra-high speed secure

34, the SD protocol processor 56 continues to communicate with the ultra-high speed secure

34 until the capabilities of the ultra-high speed secure

34 are determined. Next, one of the higher speed serial bus protocols is selected for use, for example, when the host processor system 68 determines that the

34 supports the PCI Express (PCIE) protocol, the

54 configures the multi-purpose bus switch 52 to connect the SSC

50 to the PCIE protocol processor 62. Then, when the PCIE expansion mode is enabled, the host processor system 68 communicates with the PCIE protocol processor 62 instead of the secure digital memory card protocol processor 56.

When routine initialization is performed by the host processor system 68 and it is determined that the inserted memory card is the

34 and USB enabled, the

54 sets the multipurpose bus switch 52 to connect the VHSD

50 to the USB protocol processor 60, and then when the USB expansion mode is enabled, the host processor system 68 communicates with the USB protocol processor 60 instead of the SD protocol processor 56.

When routine initialization is performed by the host processor system 68 and it is determined that the inserted memory card is an ultra-high speed secure

34 and SATA is supported, the

54 sets the multi-purpose bus switch 52 to connect the ultra-high speed secure digital memory

50 to the

64, and then when the SATA expansion mode is enabled, the host processor system 68 communicates with the

64 instead of the secure digital memory card protocol processor 56.

When routine initialization is performed by the host processor system 68 and it is determined that the inserted memory card is an ultrafast

34 and Firewire is supported, the

54 sets the multipurpose bus switch 52 to connect the ultrafast digital memory

50 to the IEEE1394 protocol processor 66, and then, when the IEEE1394 extended mode is enabled, the host processor system 68 communicates with the IEEE1394 protocol processor 66 instead of the secure digital memory card protocol processor 56.

The ultra-high speed secure

34 may also support more than one extended protocol and the host processor system 68 may then also be selected from the supported protocols. For example, the host processor system 68 may select the fastest protocol available, noting in particular here that the

51 may not support all of the protocols as depicted in FIG. 7, but may only support a subset of the described protocols.

FIG. 8 is a block diagram of an ultra high speed

71 with a SD card connector and supporting an ultra high speed SD card extended mode communication. In one embodiment, the ultra-high speed secure digital

71 may be the ultra-high speed secure

34 shown in FIG. 7, and in another embodiment, the ultra-high speed secure

34 may be a subset of all protocol processors of the ultra-high speed secure digital

71, and similarly, the ultra-high speed secure digital memory card host system 51' may be the

51 shown in FIG. 7, or a subset of all protocol processors of the

51.

The ultra-high speed secure digital memory card plug 70 of the ultra-high speed secure digital

71 can be inserted into the ultra-high speed secure digital

50 of the ultra-high speed secure digital memory card host system 51 ', and the ultra-high speed secure digital memory card plug 70 of the ultra-high speed secure digital

71 can be inserted into the secure digital memory card socket 50' of the secure digital memory card host system 75, which does not support the ultra-high speed secure digital memory card mode; alternatively, the ultra-high speed secure digital memory card plug 70 of the ultra-high speed secure digital

71 may be inserted into the multimedia

50 "of the multimedia memory card host system 77, which also does not support the ultra-high speed secure digital memory card mode, but supports the multimedia memory card or Serial Peripheral Interface (SPI) mode.

The ultra-high speed secure digital

71 has a device processor system 88 for executing a program including memory card initialization and bus response, a multipurpose bus interface system 73 for processing data from the device processor system 88 using various protocols, a secure digital memory card protocol processor 76 for processing data using a secure digital memory card protocol and inputting/outputting data on a secure digital data signal line of the ultra-high speed secure digital memory card plug 70, and the other communication protocol processors for communicating with the ultra-high speed secure digital memory card plug 70 through a multipurpose bus switch 72, which selects one of the protocol processors for performing communication.

When the routine executed by the host processor system 88 is initialized to a command using a multimedia memory card compatible Serial Peripheral Interface (SPI) mode, and when the host is the multimedia memory card host system 77, the multimedia memory card protocol processor 78 is enabled to communicate with the multimedia memory card host system 77 connected to the ultra-high speed secure digital memory card plug 70, and the secure digital memory card protocol processor 76 is disabled. The

74 sets the multi-purpose bus switch 72 to connect the ultra-high speed SD card plug 70 to the multimedia card protocol processor 78 when the device processor system 88 is instructed to use the multimedia card compatible mode, and the SD card protocol processor 76 continues to communicate with the SD card protocol processor 76 after initialization when the host is the SD card host system 75.

When the routine initialization is performed by the host and it is determined that the ultra-high speed

71 and the ultra-high speed SD card host system 51 'both support the ultra-high speed SD card mode, the ultra-high speed SD card host system 51' sends a command to the device processor system 88 via the SD card protocol processor 76 to switch to the ultra-high speed SD card mode. Then, one of the higher speed serial bus protocols is selected for use, for example, when the processor system 88 is instructed to use PCI Express, the

74 sets the multi-purpose bus switch 72 to connect the MSD card connector plug 70 to the PCI Express protocol processor 82, and then when the PCI Express expansion mode is enabled, the processor system 88 communicates with the PCI Express protocol processor 82 instead of the SDH protocol processor 76.

When routine initialization is performed by the host and it is determined that the inserted memory card supports the UHSD memory card with USB, the device processor system 88 is commanded to switch to USB mode, the

74 sets the multi-purpose bus switch 72 to connect the UHSD card connector plug 70 to the USB protocol processor 80, and then, when the USB expansion mode is enabled, the device processor system 88 communicates with the USB protocol processor 80 instead of the SD protocol processor 76.

When routine initialization is performed by the host and it is determined that the inserted memory card supports an ultra-high speed secure digital memory card with SATA, the device processor system 88 is commanded to switch to SATA mode, the

74 sets the multi-purpose bus switch 72 to connect the ultra-high speed secure digital memory card connector plug 70 to the

84, and then, when SATA expansion mode is enabled, the processor system 88 communicates with the

84 instead of the secure digital memory card protocol processor 76.

When routine initialization is performed by the host and it is determined that the inserted memory card supports the Firewire ultra-high speed secure digital memory card, the device processor system 88 is commanded to switch to the Firewire mode, the

74 sets the multi-purpose bus switch 72 to connect the Firewire connector plug 70 to the IEEE1394 protocol processor 86, and then, when the IEEE1394 extended mode is enabled, the processor system 88 communicates with the IEEE1394 protocol processor 86 instead of the secure digital memory card protocol processor 76.

It is particularly noted that the ultra-high speed secure digital

71 may not support all of the protocols as depicted in FIG. 8, and in some embodiments the ultra-high speed secure digital

71 may only support a subset of the various protocols described.

FIG. 9 is a functional diagram of a

900, which can be incorporated in the

51 of FIG. 7 or the ultra-high-speed

71 of FIG. 8. For example, the

900 may be used to provide contacts (pins) to the

50 of the sd memory card of the

51 or the connector plug 70 of the sd memory card of the

71 with multiple functions (see fig. 10, 11, 12A and 12B, respectively).

900 is configured to provide/receive signal AIN/AOUT from interface A (not shown) or signal BIN/BOUT from interface B (not shown). For example, the interfaces a and B may be an ultra-high speed sd card or an sd card protocol processor of a host system and an ultra-high speed sd card protocol processor, respectively, and the

22 may be a connector for connecting a metal pad on a memory card or a signal line of an internal bus.

The

14 buffers the

22 to generate the signal AIN to the interface A, and the

20 buffers the

22 to generate the signal BIN to the interface B, when the input/

22 is the output or driving signal, the output enable signal OE is activated to high. When interface A is enabled, ENA is logic high AND AND

910 drives a logic high to enable

912, which drives AOUT onto

22. When interface B is enabled, ENB is logic high AND AND

16 drives a logic high to enable

18, which drives BOUT onto

22.

It is noted that additional interfaces C, D (i.e., other communication protocol processors) may be multiplexed on the

22 by adding and gates and input/output buffers.

FIG. 10 is a table of multiplex signal distribution for a SD card connector with 9 pins. The power supply VDD is provided at the

4, the ground terminal is provided at the pin 3(VSS1) and the pin 6(VSS2), respectively, the clock is input to the memory card at the

5, and the

7 is the input/output serial data DAT0 of the interfaces such as the multimedia memory card, the secure digital memory card, the universal serial bus, PCIE, STAT, IEEE1394, etc.

2 is a bidirectional command CMD signal line for multimedia memory cards, secure digital memory cards, universal serial buses, and is the data input DIN to the Serial Peripheral Interface (SPI), which is a standard for complete bidirectional, synchronous serial data communication across multiple microprocessors, microcontrollers, or peripheral devices. The serial peripheral interface starts the communication between the microprocessor and the peripheral device and/or the communication between the processors, and the serial peripheral interface mode is a subset of a multimedia memory card and a secure digital memory card protocol; the serial peripheral interface has a chip select signal CS at

1 and a data out to host signal DOUT at

7, while the serial peripheral interface and the multimedia memory card interface do not use

8 and 9.

For a secure digital memory card interface, up to four data signal lines may be used simultaneously, although only one data signal line may be used for a particular communication session, for example, during an initialization process of the memory card. Data line DAT0 is at

7, data line DAT1 is at

8, data line DAT2 is at

9, and data line DAT3 is at

1.

When the ultrafast digital memory card mode is activated and the PCIE protocol is selected, the serial PCI data is transmitted through two pairs of differential data lines (i.e., the transmission lines Tp0, Tn0 and the receiving lines Rp0, Rn 0). The transmission signal lines Tp0 and Tn0 located at

2 and 1 are the output of the memory card and are received by the host; the receiving signal lines Rp0, Rn0 on

8, 9 are the output of the host and are received by the memory card.

When the SATA mode is activated and the SATA protocol is selected, serial ATA data is transmitted over two pairs of differential data lines (i.e., A, and B lines A, B). The A data lines A + and A-respectively located at the

2 and 1 are used for the output of the host and received by the memory card; the B data lines B +, B-at

8, 9, respectively, are received by the host for the output of the memory card. When SATA is used, secure digital memory card communication is interrupted.

When the ultra-high speed secure digital memory card mode is activated and the Firewire protocol is selected, the serial IEEE1394 data is transmitted through two pairs of differential data signal lines (in other words, the a signal lines TPA and TPA)^*And B signal lines TPB, TPB^*). Signal lines TPA, TPA respectively located at the

2, 1^*Received by the host for output of the memory card; signal lines TPB, TPB respectively located at

8, 9^*Received by the memory card for output by the host. When IEEE1394 is used, the secure digital memory card communication is interrupted.

FIG. 11 is a multiplexing signal distribution table of a 7-pin connector for a multimedia memory card, where legacy hosts may only support multimedia memory cards, such as USB, SD, SPI and multimedia memory cards, but others such as SATA, IEEE1394 and PCIE are not supported. Although there are 6 pins of the multimedia memory card signal, the multimedia memory card interface has an additional, unused pin for a 7 pin physical interface. The power supply VDD is provided at

4, the ground terminals VSS1, VSS2 are provided at

3, 6, the clock input to the memory card is located at

5,

7 is the input/output serial data DAT0 for interfaces such as multimedia memory card, secure digital memory card, and universal serial bus, and the data DOUT for the serial peripheral interface.

2 is a bidirectional command CMD signal line for multimedia memory cards, secure digital memory cards, universal serial buses, and is the data input DIN for Serial Peripheral Interface (SPI). The serial peripheral interface has a chip select signal CS at

1 and a data out to host signal DOUT at

7, and the SD card interface uses signal line DAT0 at

7.

When the ultra-high speed secure digital memory card mode is enabled and the USB is selected, serial USB data is transmitted bi-directionally through the differential data lines D +, D-of the USB at

2, 1. Thus, when only 7 pins are available, the universal serial bus is still supported.

FIG. 12B is a diagram of a multiplexing pin assignment table for a 10-pin Memory stick card system, in which the expansion interface can be designed to be based on other Memory cards, such as a Memory stick card (MS), rather than a secure digital Memory card. The memory stick memory card has a connector with 10 pins, power is at

3, 9, ground is at

1, 10,

8 is the system clock input SCLK,

2 is the bus state input BS, data is carried bidirectionally by data DAT0 at

4, and

6 is the insertion pin INS, which can be pulled up by the memory stick memory card's resistor to detect the memory card that is indicated to have been inserted.

5, 7 are reserved for memory stick memory cards and are extended for use with the MS Pro Duo, which has a 4-bit data bus DAT 0-3, and pins 4, 3, 5, 7, respectively, since

3 is used as DAT1 instead of VCC and provides one less power pin.

Expansion with universal serial bus for memory stick memory cardMode, pins 4, 3 load a pair of differential data D +, D-of the USB, and the other pins are used to load the memory stick memory card or MS Pro Duo signals; for the PCIE expansion mode, the

4 and 3 are loaded with a pair of PCI transmission differential data T + and T-, and the

7 and 5 are loaded with a pair of PCI receiving differential data R + and R-; similarly, for the SATA expansion mode, the

4 and 3 carry a pair of SATA transmission differential data T +, T-, and the

7 and 5 carry a pair of SATA reception differential data R +, R-; aiming at the IEEE1394 expansion mode, the

4 and 3 are loaded with a pair of 1394A differential data TPA and TPA^*And pins 7, 5 carry a pair of 1394B differential data TPB, TPB^*。

For example, fig. 13A illustrates an embodiment of a

1302 and a

1301 communicating via differential signal DDAT, where the

1302 may be any type of electronic device and has an interface to a flash memory card, such as a digital camera, MP3 player, or recorder, and the

1301 may include any type of flash memory card, including a multimedia memory card, a secure digital memory card, a memory stick memory card, or a compact flash memory card. It is noted that when the

1301 is inserted into the slot 1303 of the

1302, communication between the

1301 and the

1302 occurs (or the

1301 is coupled to the slot 1303 through an adapter or an expander), and for clarity, the

1301 is separated from the

1302 in fig. 13A.

The

1301 includes a

1310, a

1320, a

1330, and an optional

1330L, and the

1302 includes a host card controller 1340 having an

1350, a

1360, a differential data path 1370, and an optional

1370L. The

1330, 1370 provide the same functionality for the

1301 and the host memory card controller 1340, respectively, by converting memory card specific protocol signals (such as CTRL, ST, and DAT from the

1320, 1360) into DDAT, which can be transmitted between the

1301 and the host memory card controller 1340 across the

1390.

Similar to the

111, 121 of the conventional multimedia memory card shown in FIG. 1A, the

1330, 1370 can provide serial-to-parallel input and parallel-to-serial output, frame detection to ensure proper read/write operations of the memory array 113, and error checking (typical CRC checking of the SDAT and CMD signals). However, the

1330, 1370 may also provide encoding and decoding of differential data to enable differential data communication between the

1301 and the host memory card controller 1340.

Meanwhile, the

1320, 1360 located in the

1301 and the host memory card controller 1340, respectively, may operate substantially as the multimedia memory

112, 122 shown in FIG. 1A. In particular, the

1320 of the

1301 can perform appropriate operations (such as read/write operations of the

1310 and handling of packet value errors detected through the differential data path 1330) in response to the input status signal ST and data signal DAT, and generate appropriate output control signals CTRL and data signals DAT (such as pass or fail indication values and data for read/write) when such operations are completed.

Similarly, the

1360 of the host memory card controller 1340 generates appropriate output control signals CTRL and data signals DAT (such as read/write commands and memory addresses) in response to commands from the

1350, and performs appropriate operations (such as providing read data or confirmation of a write operation) in response to input status signals ST and data signals DAT. It is noted that the data signal DAT and the status signal ST can be provided to the

1302 directly through the

1360, or can be converted from a specific memory card communication protocol to a specific host communication protocol by the

1350. As described with respect to the

123 of fig. 1A, the

1350 may serve as a bridge between certain host communications and certain memory card communications.

Communication between the

1301 and the

1302 is initiated by inserting the

1301 into the slot 1303 and activating the

1301, and the

1350 provides commands (e.g., read or write commands) from the

1302 to the

1360, which in turn provides appropriate control signals CTRL and data signals DAT to the differential data path 1370. The differential data path 1370 then converts the control signal CTRL and the data signal DAT into a differential signal DDAT, which can be transmitted through the

1330 of the

1301, and the

1330 decodes the differential data DDAT into a status signal ST and a data signal DAT, so that the

1320 can perform the required operations on the memory array 1310 (unless an error occurs and is indicated by the differential data path 1330).

1320 responds with a response and any associated data from

1310 by sending control signal CTRL and data signal DAT to

1330. after converting CTRL and DAT to DDAT,

1330 sends the differential data signal DDAT back to differential data path 1370 of host card controller 1340. The differential data path 1370 then decodes the input differential data signal DDAT into a status signal ST and a data signal DAT, which can be converted into appropriately specific host signals for use by the

1302.

Communication between the

1301 and the

1302 can be viewed as a hierarchical transaction, at different levels of abstraction (at varying levels of abstraction), information is passed through the different levels (across the differential layers), for example, fig. 13B illustrates a communication between the

1301 and the

1302, showing the various levels that make up the communication stack, the

1392 and the

1393 are virtual connections (shown as dashed lines) between the

1302 and the

1301, at the

1393, the

1350 of the

1302 accesses the

1310 of the

1301, and this uppermost transaction can be accomplished through the

1392, where application specific communications are translated across the

1320, 1360 into memory card specific communications. Protocol layer communication may be implemented via a physical layer 1391, in which physical signals (i.e., differential signals DDAT and optionally legacy signals SDAT, CMD, and CLK) are transmitted between the

1302 and the

1301 via a

1390.

The function of differential data transfer between the

1302 and the

1301 can be realized by the physical layer 1391, and thus the

1360 and 1320 can be realized by using any memory card protocol. For example, in this embodiment, the

1360, 1320 may include standard multimedia card protocol controllers for using standard specific multimedia card protocol signals (such as signals CTRL, ST, and DAT). In other variations, the

1320, 1360 may include standard SD, SMRC or compact flash protocol controllers that generate and operate in response to protocol signals for a particular SD, SMRC or SMRC, as is known to be used to facilitate high speed differential communication.

For example, a conventional host device that communicates with a multimedia memory card using conventional clock data can be reconfigured for differential data communication by simply replacing the existing standard multimedia memory card data path with a differential data path (e.g., replacing the multimedia memory

121 in FIG. 1A with the differential data path 1370), and if the multimedia memory card data path is implemented in firmware (or other reprogrammable format), the reconfiguration is made easier by simply updating the firmware to implement the differential data path.

It is also specifically noted that the use of a standard specific memory card protocol controller (such as a multimedia memory card protocol controller or a secure digital memory card protocol controller) may allow the host memory card controller 1340 and/or the flash memory card 1301 (see fig. 13A) to selectively perform differential data transfer and clock data transfer depending on the characteristics of the interface device/memory card. For example, the

1360 may comprise a standard multimedia memory card protocol controller coupled to both the differential data path 1370 and the

1370L, and then communicate via the standard clock command signal CMD and the serial data signal SDAT, and the

1370L may become the standard multimedia memory card data path, according to which the host memory card controller 1340 may communicate with conventional multimedia memory cards using conventional clock data transmission, as well as using higher speed, lower power differential data transmission when using a differential data enabled multimedia memory card.

Similarly, the

1320 of the

1301 can also include a conventional multimedia memory card protocol controller coupled to both the

1330 and the

1330L, wherein the

1330L can include a conventional multimedia memory card data path; in this way, the

1301 can communicate with a conventional multimedia memory card based host device using conventional clock data transmission, and can switch between using higher speed, lower power differential data transmission when using a host device with differential data enable.

The memory card 1310A includes pins P1-P7, which are equivalent to the conventional multimedia memory card of version 3.31 (such as the

110A shown in fig. 1B), pins P3, P4, and P6 are power pins for receiving voltages VSS1, VDD, and VSS2, respectively, however, unlike the case where only pin P7 is used as the data (DAT0) pin, the memory card 1301A uses pins P1 and P7 to transmit/receive complementary signals D-, D + (in other words, the differential signal DDAT of fig. 13A) constituting differential signals, respectively.

If the multimedia memory card compatible memory card 1301A also includes a standard multimedia memory card data path (such as the

1330L shown in FIG. 13A), the pins P2, P5, P7 can be used in a conventional manner for the signals CMD, CLK, and the serial data signal DAT0 (such as the serial data signal SDAT of FIG. 1A), where the pin P7 is a dual-purpose pin that provides the serial data signal DAT0 for clock data transmission and the differential signal D + for differential data transmission, in this way, the multimedia memory card enabled for differential data transmission can maintain its appearance and pin configuration, and is compatible with host devices based on conventional multimedia memory cards.

Fig. 14B is a schematic diagram showing a mechanical form factor (mechanical form factor) of the multimedia memory card

1301B of version 4.0 to provide a differential data transmission function, and pin assignment of the multimedia memory card

1301B of version 4.0 is shown in table 4 below.

The multimedia memory card

1301B is similar to the memory card 1301A of FIG. 14A except that additional pins P8-P13 are used for the complementary signals A +, A-, B +, B-, C +, C-, as indicated in the pin configuration table above, so that three additional differential data channels (A +/A-, B +/B-, and C +/C-) can be provided, it is noted that the pins P8-P13 can be dual-purpose pins for providing compatibility with the conventional version 4.0 of the multimedia memory card device, and can provide clock serial data signals DAT 1-

7 during clock data transmission, respectively.

The flash memory card can be similarly modified for other types of flash memory cards without changing the appearance specification or the pin compatibility. For example, fig. 14C is a schematic diagram of a mechanical form factor (mechanical form factor) of the secure

1301C with a function of differential data transmission, and the pin assignment of the secure

1301C is shown in table 5 below.

The secure

1301C includes pins S1-S9, wherein the pins S3, S4, S6 are power pins for receiving voltages VSS1, VDD, VSS2, respectively, and the pins S1, S7 transmit/receive complementary signals D-, D + forming a differential signal, respectively, so that the secure

1301C and the host device can communicate with each other by using the differential signal. In one embodiment, the pins S8, S9 provide additional differential data paths for the complementary signals A +, A-, if the

1301C also includes a standard SD card data path (i.e., the

1330L shown in FIG. 13A), the

1301C receives the clock signal CLK at the pin S5, and the pins S7, S8, S9, S1 provide the clock serial data signals DAT0, DAT1, DAT2, DAT3, respectively (the pins S1, S7 or possibly both S8 and S9 are dual-purpose pins).

For another example, fig. 14D is a schematic diagram of a mechanical form factor (mechanical form factor) of a memory

1301D with a differential data transmission function, and the pin assignment of the memory

1301D is shown in the following table 6.

The memory

1301D includes pins M1-M10, wherein the pins M1, M9, M10 are power pins for receiving voltages VSS, VCC, VSS, respectively, and the pins M2, M6 provide the bus status signal BS and the insertion signal INS required by the memory stick memory card specification, respectively, so that the pins M3, M4 are used for complementary signals D-, D + forming a differential signal, respectively, so that the memory

1301D and the host device can communicate with each other by using the differential signal. Alternatively, the pins M5, M7 may provide additional differential data paths for the complementary signals A +, A-, respectively, if the memory

1301D also includes a standard memory stick memory card data path (in other words, the

1330L shown in FIG. 13A), then the memory

1301D may receive the clock signal SCLK at pin M8, and pins M4, M3, M5, M7 may be used to provide the clock serial data signals DAT0, DAT1, DAT2, DAT3, respectively (pins M3, M4 or possibly both M5, M7 are dual-purpose pins).

FIG. 15A is a diagram showing a detailed embodiment of the

1301 of FIG. 13A; the

1320 includes a

1321, an optional buffer random access memory (buffer ram)1322, and an optional Error Checking Circuit (ECC)1323, the

1321 controls the

1310 according to the status signal ST and the input data signal DAT, and generates a control signal CTRL and an output data signal DAT (as described above with reference to fig. 13A) in response. Buffer RAM 1322 may be included to buffer input and output data signals DAT and compensate for slower access times of

1310, and finally, Error Checking Circuit (ECC)1323 may be included in

1320 to verify and properly maintain signal integrity (integrity) of signals CTRL, ST, DAT.

In one embodiment, the

1330 includes a differential

1331 and a differential transceiver (transceiver)1332, the differential

1331 providing any encoding/decoding, serialization/deserialization, and packetization (packetization) of the signals CTRL, ST, DAT to meet the requirements for proper differential signal transmission (see description below for FIG. 16A). The differential

1331 generates/receives the SERS signal and converts it into DDAT signal through the

1332, thereby enabling the differential data transmission between the

1301 and the host device.

Fig. 15B is a diagram showing a detailed embodiment of the

1302 of fig. 13A, which can also be connected with the

1301 in fig. 15A. The

1360 includes a

1361, an optional buffer RAM 1362, and an optional Error Checking Circuit (ECC) 1363, and in response to the

1350, the

1361 generates appropriate output control signals CTRL and data signals DAT, and processes the input status signals ST and data signals DAT for the application converter 1350 (as described above with respect to fig. 13A). The buffer ram 1362 may be included to buffer the input and output data signals DAT and compensate for differences (differences) between the data bandwidth of the data signals DAT and the data processing capabilities of the application converter 1350 (or host device), and finally, the

1363 may be included in the

1360 to verify and properly maintain the signal integrity (integrity) of the signals CTRL, ST, DAT.

Meanwhile, the differential data path 1370 includes a differential

1371 and a differential transceiver (transceiver)1372, as with the differential

1331 in the flash card 1301 (see fig. 15A), the differential

1371 provides any encoding/decoding, serialization/deserialization, and packetization (packetization) of signals CTRL, ST, DAT to meet the requirements for proper differential signal transmission (please refer to the description corresponding to fig. 16B below for details). The differential

1371 generates/receives the SERS signal and converts the SERS signal into the DDAT signal through the

1372, thereby enabling the differential data transmission between the

1302 and the differential data transmission enabled flash card.

Fig. 16A is a schematic diagram showing a detailed embodiment of the differential

1331 in fig. 15A. The differential

1331 includes a read First In First Out (FIFO)

1621, a parallel to serial converter 1622, an encoder 1623, a Cyclic Redundancy Check (CRC)

1624, a command/data setting circuit 1625, a sync generator 1626, an end of packet (EOP) generator 1627, a

1631, a serial to

1632, a

1633, a

1634, a command/data detector 1635, a sync detector 1636, an end of

1637, a start frame (SOF) detector 1638, and a Phase Locked Loop (PLL) 1639. The differential

1331 as shown in fig. 16A may enable serial data transmission through data packetization, thereby eliminating the need for clock data transmission, wherein it is specifically noted that the underlying memory card protocol (e.g., multimedia memory card protocol) may itself include some packetization format, such that the differential Serial Interface Engine (SIE)1331 may simply perform packetization on the underlying packet data.

1633 is coupled to and receives serial signal SSER from

1332 to decode according to a predetermined coding protocol, for example, in one embodiment, a non return to zero (NRZI) code may be used to enable differential data transmission, while a bit stuffing (bitstuffing) may be incorporated to facilitate frame detection. In such an environment, the

1633 may include non-return to zero (NRZI) decoding and bit mining (bit un-stuffing) logic, and the

1633 may also include clock recovery logic and elastic store buffers to compensate for local clock problems, such as jitter (jitter).

The decoded signal generated by the

1633 can be parallelized (parallelized) by the

1632 to make it more efficient to process, and then the data is sent to the

1631, the

1634, the command/data detector 1635, the sync detector 1636, the end of

1637, and the start-of-frame (SOF) detector 1638. The sync detector 1636 identifies a synchronization field (sync field) from the input signal, and when detecting the sync field, STARTs receiving the packet by providing a START signal START to the

1631, the

1634, the command/data detector 1635, and the START frame (SOF) detector 1638.

In response to the START signal START, the write operation STARTs to the

1631 to store the content of the input signal (the signal from the serializer 1632), and the

1634 performs crc on the input data. If different CRC formats are used to check the command and data signals (e.g., CRC7 is used to check the command and CRC16 is used to check the data), a determination is made by the command/data detector 1635 whether the incoming data block is a command block or a data block, and the

1634 is indicated, noting that if the CRC fails, various error handling procedures can be performed, including termination procedures, request for retransmission of command/data, etc.

Meanwhile, the start frame detector 1638 detects the start frame burst with respect to the input data and provides the frame timing frequency (frame timing) to the

1639, which in response generates the local clock signal LCLK (the start frame burst is inserted into the input signal by the host device at regular intervals). As a result, the local clock signal LCKL is synchronized with the clock of the original system used in the host device to encode the original input signal, and can be used as a recovered clock of the input signal.

Finally, when the end-of-

1637 detects the end-of-packet, the end-of-

1637 ends the reception of the packet by issuing a STOP signal STOP to the

1631, the

1634, the command/data detector 1635, the end-of-

1637, and the start frame detector 1638, and then the

1320 reads the packet data (which may be the status signal ST or the data signal DAT) from the

1631 before starting the reception of the next packet. In this way, the

1631,

1634, command/data detector 1635, end-of-

1637, and start frame detector 1638 may be implemented as de-packetization logic of the differential

1331.

The control signal CTRL and/or data signal DAT are recovered by the

1320 and stored in the

1621, and the

1624 and the sync generator 1626 generate crc and sync sets for the output signals, respectively, noting that if different crc formats are used for the command and data packets, the command/data setting circuit 1625 will provide an appropriate indication to the

1624. The contents of the

1621 are then sent to the serializer 1622 for serialization, and at the end of each packet, the end of packet generator 1627 issues an end of packet message, in such a way that the

1621, the

1624, the command/data set circuit 1625, the Sync generator 1626, and the end of packet generator 1627 act as packetizing logic for the differential

1331.

The parallel-to-serial converter 1622 then converts the input parallel data into a serial bit stream (bitstream) which is then encoded by the encoder 1623. as described above with respect to the

1633, the encoder 1623 also applies a predetermined encoding protocol to the bitstream from the parallel-to-serial converter 1622 to generate the output stream signal SSER, which is then converted into the differential data signal DDAT via the

1332. For example, in one embodiment, the encoder 1623 may include bit stuffing (bit stuffing) and reverse non-return to zero (NRZI) encoding logic.

Fig. 16B is a schematic diagram showing a detailed embodiment of the differential

1371 in fig. 15B. The differential

1371 includes a First In First Out (FIFO)

1641, a serializer 1642, an encoder 1643, a Cyclic Redundancy Check (CRC)

1644, a command/

1645, a

1646, a start of frame (SOF)/end of packet (EOP)

1647, a

1651, a serializer 1652, a

1653, a

1654, a command/data detector 1655, a sync detector 1656, an end of packet detector 1657, and a Phase Locked Loop (PLL) 1659. Like the differential

1331 of FIG. 16A, the differential

1371 of FIG. 16B enables serial differential data transmission via data packetization, thereby eliminating the need for clock data transmission.

The control signal CTRL and/or data signal DAT stored in the

1641 and from the

1360 will begin to communicate with the flash memory card, while the

1644 and the

1646 will generate crc sets and sync sets, respectively, for the output signals, noting that if different crc formats are used for the command and data packets, the command/

1645 will provide the appropriate indication to the

1644.

The contents of the

1641 are then sent to the serializer 1642 for serialization, and at the beginning of each frame, the start frame/end of

1647 issues a start frame packet; at the end of each packet, the start frame/end of

1647 issues an end of packet message packet. It is noted that the system clock signal SCLK generated by the

1659 is used to provide the frame clock to the start frame/end of

1647, and specifically, the system clock signal SCLK is used by the start frame/end of

1647 to provide the start frame information set at appropriate time intervals. In this manner, the

1641, the

1644, the command/

1645, the

1646, and the Start frame/end of

1647 may be implemented as packetized logic of the differential

1371.

The serializer 1642 then converts the input parallel data into a serial bit stream (bitstream) which is then encoded by the encoder 1643. the encoder 1643 also applies a predetermined encoding protocol (e.g., bit-stuffing encoding or reverse non-return-to-zero encoding) to the bitstream from the serializer 1642 to generate an output stream signal SSER which is then converted into a differential data signal DDAT by the

1372.

The input serial signal SSER (generated by the

1372 based on the input differential signal DDAT) is decoded by the

1653 according to a predetermined encoding protocol (e.g., bit-stuffing encoding or reverse non-return to zero encoding). in one embodiment, the

1653 may also include clock recovery logic and a flexible storage buffer to compensate for local clock problems (e.g., jitter).

The decoded signal generated by the

1653 can be parallelized by the serializer 1652 and sent to the

1651, the

1654, the command/data detector 1655, the sync detector 1656, and the end of packet detector 1657. The sync detector 1656 identifies sync blocks from the input signal and, when a sync block is detected, begins reception of a packet by providing a START signal START to the

1651, the

1654, the command/data detector 1655, and the end of packet detector 1657.

In response to the START signal START, the

1651 begins to store the contents of the input signal (the signal from the serial-to-parallel converter 1652), while the

1654 performs CRC on the input data (optionally based on the signal from the command/data detector 1655). It should be noted that if the crc fails, various error handling procedures may be performed, including termination procedures, request for retransmission of commands/data, etc.

Finally, when the end of packet detector 1657 detects an end of packet, the end of packet detector 1657 terminates the reception of the packet by issuing a STOP signal STOP to the

1651, the

1654, the command/data detector 1655, and the end of packet detector 1657, and the

1360 reads the packet data (which may be a status signal ST or a data signal DAT) from the

1651 before starting the reception of the next packet. In this manner, the

1651,

1654, command/data detector 1655, and end-of-packet detector 1657 may serve as de-packetization logic for the differential

1371.

1. A flash memory card, comprising:

a pin configuration predetermined based on the number of pins of the flash memory card, the pin configuration including at least one dual-purpose pin for providing a legacy data path and a differential data path;

a flash memory array;

a protocol controller for accessing the flash memory array; wherein,

the differential data path has a function of converting an input differential signal into a status signal and an input data signal to the protocol controller, and a function of converting a control signal and an output data signal from the protocol controller into an output differential signal, wherein the differential data path includes a differential transceiver and a differential serial interface engine, wherein:

the differential transceiver is used for converting the input differential signal into an input multipurpose serial signal and converting an output multipurpose serial signal into the output differential signal; and

the differential serial interface engine is used for converting the input multipurpose serial signal into at least one status signal and the input data signal, and converting at least one control signal and the output data signal into the output multipurpose serial signal, wherein the differential serial interface engine comprises:

a decoder for decoding the input multipurpose serial signal according to a predetermined encoding protocol and converting the input multipurpose serial signal into an input serial bit stream;

a first converter for converting the input serial bit stream into a first signal set;

a synchronization detector for identifying a synchronization packet with respect to the first signal set and starting packet reception by generating an initial signal when detecting the synchronization packet;

a write FIFO for storing the contents of the first set of signals in response to the start signal and outputting the at least one status signal and the input data signal;

a cyclic redundancy check detector for performing a cyclic redundancy check on the first signal set in response to the start signal;

a command/data detector for determining whether the first set of signals is a command signal or a data signal in response to the start signal and providing the determination to the CRC detector;

an initial frame detector for detecting a plurality of initial frame packets of the first signal set in response to the initial signal and triggering generation of a local clock during detection;

a packet end detector for detecting an end-of-packet message of the first set of signals in response to the start signal and, upon detection, issuing a stop signal to terminate packet reception;

a read FIFO for storing the at least one control signal and the contents of the output data signal outputted through the protocol controller, and outputting a second set of signals;

a synchronous generator for generating a synchronous information set for the second signal set;

a cyclic redundancy check generator for generating a cyclic redundancy check information set for the second signal set;

a command/data setting circuit for determining whether the second set of signals is a command signal or a data signal and providing the determination to the CRC generator;

a packet end generator for generating a packet end message set for the second signal set;

a second converter for converting the second signal group, the cyclic redundancy check information group, the synchronization information group and the packet end information group received in parallel into an output serial bit stream; and

an encoder for applying the predetermined encoding protocol to the output serial bit stream and converting the encoded output serial bit stream into the output multipurpose serial signal;

wherein the flash memory card comprises one of a multimedia memory card, a secure digital memory card, a compact flash memory card, and a memory stick memory card.

2. The flash memory card of claim 1 wherein the legacy data path is configured to convert an input clock command signal to the status signal and an input clock data signal to the input data signal, and is configured to convert the control signal to an output clock command signal and the output data signal to an output clock data signal.

3. The flash memory card of claim 2 wherein the flash memory card is a multimedia memory card comprising a first pin and a second pin, wherein the input differential signal and the output differential signal are provided at the first pin and the second pin, respectively, and the input/output clock data signal is provided at one of the first pin and the second pin.

4. The flash memory card of claim 1 wherein the crc detector performs crc using a first crc format when the input serial bitstream includes the status signal; when the input serial bit stream contains the input data signal, the crc detector performs crc using a second crc format.

5. The flash memory card of claim 1 further comprising a phase-locked loop configured to generate a local clock signal for use in reading data from the input data signal and to generate an output serial bit stream.

6. An electronic device, comprising:

a pin configuration predetermined based on a number of pins of a flash memory card, the pin configuration including at least one dual-purpose pin for providing a legacy data path and a differential data path;

a host memory card adapter for connecting the flash memory card, the host memory card adapter comprising a protocol controller, an application adapter and a differential data path, wherein:

a protocol controller, responsive to the application converter, for providing a function of the specific flash card communication protocol;

the application adapter is used for controlling the protocol controller and provides a bridge between the communication of a specific device and the communication of the specific flash memory card; and

a differential data path having a function of converting an input differential signal into a status signal and an input data signal to the protocol controller, and a function of converting a control signal and an output data signal from the protocol controller into an output differential signal, wherein the differential data path comprises a differential transceiver and a differential serial interface engine:

a differential transceiver for converting the input differential signal into an input multipurpose serial signal and for converting an output multipurpose serial signal into the output differential signal; and

a differential serial interface engine for converting the input multipurpose serial signal into at least one status signal and the input data signal, and converting at least one control signal and the output data signal into the output multipurpose serial signal, wherein the differential serial interface engine comprises:

a decoder for decoding the input multipurpose serial signal according to a predetermined encoding protocol and converting the input multipurpose serial signal into an input serial bit stream;

a first converter for converting the input serial bit stream into a first signal set;

a synchronization detector for identifying a synchronization packet with respect to the first signal set and starting packet reception by generating an initial signal when detecting the synchronization packet;

a read FIFO for storing the contents of the first set of signals in response to the start signal and outputting the at least one status signal and the input data signal;

a cyclic redundancy check detector for performing a cyclic redundancy check on the first signal set in response to the start signal;

a command/data detector for determining whether the first set of signals is a command signal or a data signal in response to the start signal and providing the determination to the CRC detector;

a packet end detector for detecting an end-of-packet message of the first set of signals in response to the start signal and, upon detection, issuing a stop signal to terminate packet reception;

a write FIFO for storing the at least one control signal and the contents of the output data signal outputted through the protocol controller, and outputting a second set of signals;

a synchronous generator for generating a synchronous information set for the second signal set;

a cyclic redundancy check generator for generating a cyclic redundancy check information set for the second signal set;

a command/data setting circuit for determining whether the second set of signals is a command signal or a data signal and providing the determination to the CRC generator;

a start frame and end of packet generator for generating a start frame field and an end of packet field for the second set of signals;

a second converter for converting the second signal group, the cyclic redundancy check information group, the synchronization information group, the start frame information group and the end of packet information group received in parallel into an output serial bit stream; and

an encoder for applying the predetermined encoding protocol to the output serial bit stream and converting the encoded output serial bit stream into the output multipurpose serial signal;

wherein the flash memory card comprises one of a multimedia memory card, a secure digital memory card, a compact flash memory card, and a memory stick memory card.

7. The electronic device of claim 6 further comprising a legacy data path for converting an input clock command signal to the status signal and an input clock data signal to the input data signal, and for converting the control signal to an output clock command signal and the output data signal to an output clock data signal.

8. The electronic device of claim 6, wherein the CRC generator applies a first CRC format to the output serial bit stream when the output serial bit stream is generated from the control signal; and the crc generator applies a second crc format to the output serial bitstream when the output serial bitstream is generated from the output data signal; wherein the input serial bit stream includes the status signal, the crc detector performing a crc using the first crc format; when the input serial bit stream contains the input data signal, the crc detector performs crc using the second crc format.

9. The electronic device of claim 6 further comprising a phase-locked loop for generating a system clock signal, wherein the start frame information is generated in response to the system clock signal.