CN102623455A - Nonvolatile memory cell and method for manufacturing same - Google Patents
- ️Wed Aug 01 2012
CN102623455A - Nonvolatile memory cell and method for manufacturing same - Google Patents
Nonvolatile memory cell and method for manufacturing same Download PDFInfo
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- CN102623455A CN102623455A CN2011100301927A CN201110030192A CN102623455A CN 102623455 A CN102623455 A CN 102623455A CN 2011100301927 A CN2011100301927 A CN 2011100301927A CN 201110030192 A CN201110030192 A CN 201110030192A CN 102623455 A CN102623455 A CN 102623455A Authority
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Abstract
The invention discloses a nonvolatile memory cell and a method for manufacturing the same. The nonvolatile memory cell comprises: a transistor consists of a drain, a source, a grid and a substrate, wherein the transistor includes: a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, the substrate, an asymmetrical lightly doped zone, a first sidewall, a second sidewall and a silicon oxide layer; the silicon oxide layer is positioned on the substrate; the polycrystalline silicon layer, the first sidewall and the second sidewall are all located on the silicon oxide layer; the first sidewall and the second sidewall are arranged on the two sides of the polycrystalline silicon layer respectively; the asymmetrical lightly doped zone adjoins the second heavily doped region and the silicon oxide layer. The nonvolatile memory cell and the method for manufacturing the same provided by the invention are completely compatible with the prior logic process, particularly the deep submicron logic process; the memory cell area is able to be reduced with the reduction of the prior logic process.
Description
Technical Field
The present invention relates generally to semiconductor memory devices, and more particularly to a nonvolatile memory cell and a method of fabricating the same.
Background
Non-volatile memory chips are widely used in electronic products, computers, communication devices, consumer electronics, and other applications requiring power-down storage of data. The non-volatile Memory includes various types, wherein the types of EPROM, Flash Memory, and the like have programming and erasing functions.
Disclosure of Invention
It is therefore an object of the present invention to provide a non-volatile memory cell and a method for fabricating the same, which is fully compatible with the existing logic processes, especially the deep submicron logic process, and the area of the memory cell can be reduced with the reduction of the process.
According to an aspect of the present invention, there is provided a nonvolatile memory cell including:
a transistor composed of a drain, a source, a gate, and a substrate;
the transistor includes:
the silicon substrate comprises a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, a substrate, an asymmetric lightly doped region, a first side wall, a second side wall and a silicon oxide layer; wherein,
the silicon oxide layer is positioned on the substrate;
the polycrystalline silicon layer, the first side wall and the second side wall are all positioned on the silicon oxide layer;
the first side wall and the second side wall are respectively positioned at two sides of the polycrystalline silicon layer;
the asymmetric lightly doped region is adjacent to the second heavily doped region and the silicon oxide layer.
In accordance with one feature of the present invention,
the first side wall is used for storing electric charges.
In accordance with a further feature of the present invention,
the thickness of the silicon oxide layer is equal to that of the silicon oxide layer of the thick gate oxide transistor under the standard semiconductor logic process.
In accordance with a further feature of the present invention,
the transistor is an NMOS transistor.
According to another aspect of the present invention, there is provided a non-volatile memory fabricated in accordance with the non-volatile memory cell.
According to another aspect of the present invention, there is provided a layout of a non-volatile memory cell, comprising:
an active region layer, a polysilicon layer, a drain-source implant region layer, and an auxiliary layer, wherein,
the auxiliary layer is used for covering the active region layer on one of two sides of the polysilicon layer.
In accordance with a further feature of the present invention,
the size and shape of the auxiliary layer can be set according to predetermined design rules.
According to another aspect of the present invention, there is provided a reticle pattern generated according to the layout, including:
an active region layer, a polysilicon layer, a drain-source implant region layer, and an asymmetric lightly doped implant layer, wherein,
and performing logic operation on the drain-source injection region layer and the auxiliary layer according to a preset logic operation formula, so that light doping injection is not performed in the active region layer covered by the auxiliary layer, and the asymmetric light doping injection layer is obtained.
In accordance with one feature of the present invention,
the predetermined logical operation formula is:
SM5＝SL3-SL4-SX5
wherein，SM5Representing the area of the lightly doped implant layer in the reticle pattern,
SL3the area of the drain-source injection region layer in the layout is shown,
SL4representing the area of the auxiliary layer in the layout,
SX5indicating the preset area correction value of the lightly doped implantation layer when the layout is converted into the mask graph.
According to another aspect of the invention, a method for manufacturing the mask pattern nonvolatile memory cell is provided.
The nonvolatile memory cell and the manufacturing method thereof are completely compatible with the existing logic process, particularly the deep submicron logic process, and the area of the memory cell can be reduced along with the reduction of the existing logic process. The nonvolatile memory cell stores charges by utilizing the side wall of the transistor of the asymmetric lightly doped region, controls the on-resistance between the source and the drain of the memory cell by controlling the amount of the stored charges of the side wall so as to change the on-current between the source and the drain of the memory cell, and thus, the stored data can be determined according to the on-current between the source and the drain of the memory cell.
Drawings
FIG. 1 is a circuit diagram of a transistor as a non-volatile memory cell in an embodiment of the present invention;
FIG. 2 is a block diagram of a standard thick gate oxide based logic process;
FIG. 3 is a diagram showing a structure of a transistor as a nonvolatile memory cell in the embodiment of the present invention;
FIG. 4 is a layout of a standard thick gate oxide transistor based on a logic process;
FIG. 5 is a layout of a transistor as a non-volatile memory cell in an embodiment of the present invention;
FIG. 6 is a mask pattern of a standard thick gate oxide transistor based on logic processing;
FIG. 7 is a mask pattern of a transistor as a non-volatile memory cell in an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a circuit diagram of a transistor as a nonvolatile memory cell in an embodiment of the present invention, and in fig. 1, the transistor as a nonvolatile memory cell in an embodiment of the present invention based on a logic process includes:
drain electrode D, source electrode S, grid electrode G and substrate B.
Fig. 2 is a structural diagram of a standard thick gate oxide transistor based on a logic process, and in fig. 2, the standard thick gate oxide transistor includes:
a first heavily doped
region201, a second heavily doped
region202, a
polysilicon layer203, a
substrate204, a first lightly doped
region205, a second lightly doped
region206, a
first sidewall207, a
second sidewall208, and a
silicon oxide layer209.
As shown in fig. 2, the standard thick-gate oxide transistor includes a first lightly doped
region205 and a second lightly doped
region206 that are symmetrical. The first heavily doped
region201 and the second heavily doped
region202 are N-type heavily doped regions, and the
substrate204 is a P-type well. Standard thick-gate oxide transistors are used in logic processes to implement input-output circuits. The thickness of the
silicon oxide layer209 of a standard thick gate oxide transistor is typically 6-8 nanometers for a 0.13 micron semiconductor fabrication process. The thickness of the
silicon oxide layer209 of a standard thick gate oxide transistor varies from semiconductor manufacturing process to semiconductor manufacturing process.
Fig. 3 is a structural diagram of a transistor as a nonvolatile memory cell in the embodiment of the present invention, and in fig. 3, the transistor as a nonvolatile memory cell in the embodiment of the present invention includes:
a first heavily doped
region301, a second heavily doped
region302, a
polysilicon layer303, a
substrate304, a lightly doped
region305, a
first sidewall306, a
second sidewall307, and a
silicon oxide layer308. Wherein,
a
silicon oxide layer308 is located on the
substrate304;
the
polysilicon layer303, the
first side wall306 and the
second side wall307 are all positioned on the
silicon oxide layer308;
the
first side wall306 and the
second side wall307 are respectively located at two sides of the
polysilicon layer303;
the lightly doped
region305 is adjacent to the second heavily doped
region302 and the
silicon oxide layer308.
The thickness of the
silicon oxide layer308 is equal to the thickness of the silicon oxide layer of a thick gate oxide transistor under standard semiconductor logic processing.
As can be seen from fig. 3, the transistor as the nonvolatile memory cell in the embodiment of the present invention includes only the lightly doped
region305, and belongs to the asymmetric lightly doped region type transistor.
The storage region of the transistor serving as the nonvolatile memory cell in the embodiment of the present invention is disposed at the
first sidewall306, that is, the
first sidewall306 is used to store charges, and the number of the charges stored in the
first sidewall306 is controlled to control the on-resistance between the source and the drain of the transistor serving as the nonvolatile memory cell, so as to change the magnitude of the on-current between the source and the drain of the transistor of the nonvolatile memory cell, so that the stored data can be determined according to the magnitude of the on-current between the source and the drain of the transistor of the nonvolatile memory cell.
The transistor serving as the nonvolatile memory unit in the embodiment of the invention not only reduces the programming and erasing voltage, but also improves the programming and erasing speed by using the asymmetric lightly doped region.
Fig. 4 is a layout of a standard thick gate oxide transistor based on a logic process, where fig. 4 includes:
an active region layer L1, a polysilicon layer L2, and a drain-source implant region layer L3.
The standard thick gate oxide transistor in fig. 2 was generated from the layout in fig. 4.
Fig. 5 is a layout of a transistor as a nonvolatile memory cell in the embodiment of the present invention, where fig. 5 includes:
an active region layer L1, a polysilicon layer L2, a drain-source implant region layer L3, and an auxiliary layer L4.
The transistor in the embodiment of the present invention in fig. 3 as a nonvolatile memory cell is manufactured according to the layout in fig. 5.
As can be seen from comparing fig. 4 and 5, the layout in fig. 5 is different from the layout in fig. 4 in that an auxiliary layer L4 is added, and the auxiliary layer L4 does not affect the patterns of other layers in the layout, such as the active region layer L1, the polysilicon layer L2, and the drain-source implantation region layer L3.
The auxiliary layer L4 may be set according to design rules provided by a foundry (integrated circuit chip manufacturing factory). The auxiliary layer L4 in fig. 5 is only an example, and is not intended to limit the specific size and shape of the auxiliary layer L4, and a designer may design the size and shape of the auxiliary layer L4 according to the design rules and practical requirements provided by a wafer foundry, as long as the active region on one of the two sides of the polysilicon layer L2 in the layout in fig. 5 can be covered.
The manufacturing of the transistor is completed by copying a mask graph of the transistor to a silicon wafer, the mask graph of the transistor is obtained by converting a layout of the transistor, a wafer factory can provide a calculation method for converting the layout to the mask graph, namely a predetermined logic operation formula, and different wafer factories have different predetermined logic operation formulas. For example, for an NMOS transistor, a P-well is not generally drawn in a layout, but obtained by performing logic operation on a P-well layer of an NMOS according to a predetermined logic operation formula provided by a wafer foundry during a process of manufacturing a mask pattern. Similarly, the present invention utilizes this process to implement an asymmetric lightly doped region for a transistor as a non-volatile memory cell. Specifically, in the embodiment of the present invention, an auxiliary layer is added to the layout of the transistor as the nonvolatile memory cell, and the auxiliary layer is used for performing logic operation on the lightly doped region layer when the mask pattern is generated. That is, asymmetric lightly doped regions are realized on the mask pattern by modifying the logical operation method of the mask pattern.
FIG. 6 is a mask pattern of a standard thick gate oxide transistor based on a logic process, wherein FIG. 6 includes: an active region layer M1, a polysilicon layer M2, a drain-source implant region layer M3, and a lightly doped implant layer M4.
Performing logical operation on the active region layer L1 in fig. 4 according to a predetermined logical operation formula to obtain an active region layer M1; the predetermined logical operation formula of the active area layer M1 may be:
SM1＝SL1-SX1
SM1the area of the active area layer M1 in the reticle pattern is shown,
SL1the area of the active region layer L1 in the layout is represented,
SX1indicating a predetermined area correction value S for the active area layer at the time of a layout-to-reticle pattern transitionX1And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the polycrystalline silicon layer L2 in FIG. 4 according to a predetermined logical operation formula to obtain a polycrystalline silicon layer M2; the predetermined logical operation formula of the polysilicon layer M2 may be:
SM2＝SL2-SX2
SM2indicating the area of the polysilicon layer M2 in the reticle pattern,
SL2indicates the area of the polysilicon layer L2 in the layout,
SX2indicating a predetermined area correction value S of the polysilicon layer at the time of switching from the layout to the reticle patternX2And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the drain-source injection region layer L3 in fig. 4 according to a predetermined logical operation formula to obtain a drain-source injection region layer M3; the predetermined logical operation formula of the drain-source implantation region layer M3 may be:
SM3＝SL3-SX3
SM3the area of the drain-source implantation region layer M3 in the reticle pattern is shown,
SL3the area of the drain-source implant region layer L3 in the layout is represented,
SX3indicating a predetermined area correction value S of the source/drain implant layer at the time of switching from the layout to the reticle patternX3And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the drain-source implantation region layer L3 in fig. 4 according to a predetermined logical operation formula to obtain a lightly doped implantation layer M4; the predetermined logical operation formula of the lightly doped implantation layer M4 may be:
SM4＝SL3-SX4
SM4the area of the lightly doped implant layer M4 in the reticle pattern is shown,
SL3the area of the drain-source implant region layer L3 in the layout is represented,
SX4indicating a predetermined area correction value S for the lightly doped implant layer at the time of a layout-to-reticle pattern transitionX4And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
A standard thick gate oxygen transistor implemented by the reticle layout in fig. 6 has symmetric lightly doped regions as shown in fig. 2.
FIG. 7 is a mask pattern of a transistor as a non-volatile memory cell in an embodiment of the present invention, where FIG. 7 includes: an active region layer M1, a polysilicon layer M2, a drain-source implant region layer M3, and a lightly doped implant layer M5.
Performing logical operation on the active region layer L1 in fig. 5 according to a predetermined logical operation formula to obtain an active region layer M1; the predetermined logical operation formula of the active area layer M1 may be:
SM1＝SL1-SX1
SM1the area of the active area layer M1 in the reticle pattern is shown,
SL1the area of the active region layer L1 in the layout is represented,
SX1indicating a predetermined area correction value S for the active area layer at the time of a layout-to-reticle pattern transitionX1And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the polycrystalline silicon layer L2 in FIG. 5 according to a predetermined logical operation formula to obtain a polycrystalline silicon layer M2; the predetermined logical operation formula of the polysilicon layer M2 may be:
SM2＝SL2-SX2
SM2indicating the area of the polysilicon layer M2 in the reticle pattern,
SL2indicates the area of the polysilicon layer L2 in the layout,
SX2indicating a predetermined area correction value S of the polysilicon layer at the time of switching from the layout to the reticle patternX2And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the drain-source injection region layer L3 in fig. 5 according to a predetermined logical operation formula to obtain a drain-source injection region layer M3; the predetermined logical operation formula of the drain-source implantation region layer M3 may be:
SM3＝SL3-SX3
SM3the area of the drain-source implantation region layer M3 in the reticle pattern is shown,
SL3the area of the drain-source implant region layer L3 in the layout is represented,
SX3indicating a predetermined area correction value S of the source/drain implant layer at the time of switching from the layout to the reticle patternX3And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
Performing logical operation on the drain-source injection region layer L3 and the auxiliary layer L4 in fig. 5 according to a predetermined logical operation formula to obtain a lightly doped injection layer M5; the predetermined logical operation formula of the lightly doped implantation layer M5 may be:
SM5＝SL3-SL4-SX5，
SM5the area of the lightly doped implant layer M5 in the reticle pattern is shown,
SL3the area of the drain-source implant region layer L3 in the layout is represented,
SL4indicating the area of the auxiliary layer L4 in the layout,
SX5indicating a predetermined area correction value S for the lightly doped implant layer at the time of a layout-to-reticle pattern transitionX5And may be set to a positive value, a negative value, or zero (i.e., no correction) depending on actual design requirements.
That is, the mask pattern of the asymmetric lightly doped region is realized by removing the area part of the auxiliary layer L4 in the layout of the transistor as the nonvolatile memory cell in the logic calculation of the mask pattern of the transistor as the nonvolatile memory cell to produce the asymmetric lightly doped region, and the lightly doped implantation is performed only in the region where the lightly doped implantation layer M5 is present.
The transistor as a nonvolatile memory cell in the embodiment of the present invention implemented by the mask layout in fig. 7 has an asymmetric lightly doped region as shown in fig. 3.
The logical calculation formula for the calculation of the active region layer M1, the polysilicon layer M2, and the drain-source implantation region layer M3 in fig. 7 is the same as the logical calculation formula for the calculation of the active region layer M1, the polysilicon layer M2, and the drain-source implantation region layer M3 in fig. 6. While the logical calculation formula for calculating the obtained lightly doped implanted layer M5 in fig. 7 is different from the logical calculation formula for calculating the obtained lightly doped implanted layer M4 in fig. 6.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, alterations, combinations, equivalents, improvements and the like made to the embodiments of the present invention within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A non-volatile memory cell, comprising:
a transistor composed of a drain, a source, a gate, and a substrate;
the transistor includes:
the silicon substrate comprises a first heavily doped region, a second heavily doped region, a polycrystalline silicon layer, a substrate, an asymmetric lightly doped region, a first side wall, a second side wall and a silicon oxide layer; wherein,
the silicon oxide layer is positioned on the substrate;
the polycrystalline silicon layer, the first side wall and the second side wall are all positioned on the silicon oxide layer;
the first side wall and the second side wall are respectively positioned at two sides of the polycrystalline silicon layer;
the asymmetric lightly doped region is adjacent to the second heavily doped region and the silicon oxide layer.
2. The non-volatile memory cell of claim 1,
the first side wall is used for storing electric charges.
3. The non-volatile memory cell of claim 1,
the thickness of the silicon oxide layer is equal to that of the silicon oxide layer of the thick gate oxide transistor under the standard semiconductor logic process.
4. The non-volatile memory cell of claim 1,
the transistor is an NMOS transistor.
5. A non-volatile memory fabricated in accordance with the non-volatile memory cell of claim 1.
6. A layout of a non-volatile memory cell, comprising:
an active region layer, a polysilicon layer, a drain-source implant region layer, and an auxiliary layer, wherein,
the auxiliary layer is used for covering the active region layer on one side of two sides of the polycrystalline silicon layer.
7. The layout according to claim 6,
the size and shape of the auxiliary layer can be set according to predetermined design rules.
8. A reticle pattern generated from a layout according to claim 6 comprising:
an active region layer, a polysilicon layer, a drain-source implant region layer, and an asymmetric lightly doped implant layer, wherein,
and performing logical operation on the drain-source injection region layer and the auxiliary layer in the layout according to a preset logical operation formula, so that light doping injection is not performed in the active region layer covered by the auxiliary layer, and the asymmetric light doping injection layer is obtained.
9. The reticle pattern of claim 8,
the predetermined logical operation formula is:
SM5＝SL3-SL4-SX5
wherein S isM5Representing the area of the lightly doped implant layer in the reticle pattern,
SL3the area of the drain-source injection region layer in the layout is represented,
SL4representing the area of the auxiliary layer in the layout,
SX5indicating the preset area correction value of the lightly doped implantation layer when the layout is converted into the mask graph.
10. A method of manufacturing a reticle patterned non-volatile memory cell according to claim 8.
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| CN2011100301927A CN102623455A (en) | 2011-01-27 | 2011-01-27 | Nonvolatile memory cell and method for manufacturing same |
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| CN2011100301927A CN102623455A (en) | 2011-01-27 | 2011-01-27 | Nonvolatile memory cell and method for manufacturing same |
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| CN106610561A (en) * | 2015-10-20 | 2017-05-03 | 无锡华润上华半导体有限公司 | Forming method of mask |
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Application publication date: 20120801 |