CN102709235A - Array base board as well as manufacturing method and display device thereof - Google Patents
- ️Wed Oct 03 2012
CN102709235A - Array base board as well as manufacturing method and display device thereof - Google Patents
Array base board as well as manufacturing method and display device thereof Download PDFInfo
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- CN102709235A CN102709235A CN2011103296013A CN201110329601A CN102709235A CN 102709235 A CN102709235 A CN 102709235A CN 2011103296013 A CN2011103296013 A CN 2011103296013A CN 201110329601 A CN201110329601 A CN 201110329601A CN 102709235 A CN102709235 A CN 102709235A Authority
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- photoresist
- reserve area
- layer
- active layer
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Abstract
The invention provides an array base board as well as a manufacturing method and a display device thereof, the manufacturing method comprises that transparent conductive film and grid metal film are formed on the base board, and a first pattern layer of a pixel electrode, a grid wire and a grid electrode is formed through a composition process; a grid insulation layer and an active layer are formed, and patterns of the active layer are formed through the composition process; an insulation layer is formed, patterns of a protective layer and a stop layer are formed through the composition process, and the stop layer is arranged on a channel zone of the active layer; and the transparent conductive film and source-drain metal film is formed, and a second pattern layer of the pixel electrode, a source-drain electrode and a data wire is formed through the composition process. By the adoption of four composition processes provide by the invention, the manufacture of the array base board is realized, the manufacture time can be shortened, the production efficiency is increased, and the production cost is lowered.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte and manufacturing approach thereof, display unit.
Background technology
Flat-panel monitor is the display of present main flow, and it comprises active matrix organic light emitting diode display (AMOLED), Thin Film Transistor-LCD (TFT-LCD) etc.TFT-LCD has characteristics such as volume is little, low in energy consumption, radiationless, in current flat panel display market, has occupied leading position.According to the direction of an electric field that drives liquid crystal, TFT-LCD is divided into vertical electric field type and horizontal electric field type.And vertical electric field type comprises twisted nematic (TN) TFT-LCD, and horizontal electric field type comprises the TFT-LCD of fringing field effect (FFS), copline field effect (IPS) TFT-LCD.FFS type TFT-LCD has advantages such as wide visual angle, high aperture, has obtained using widely in field of liquid crystal display.
In the manufacture craft of thin-film transistor, in some cases, in order to prevent when forming source-drain electrode, crossing of active layer to be carved; Need on active layer, deposit one deck etching barrier layer, this needs once extra photoetching process to form etching barrier layer, for example; For bottom gate type TFT, generally need five composition technologies to accomplish and make complex process; Manufacturing time is longer, and manufacturing cost is also higher.
In addition, the size of LCD is in continuous increase, and the frequency of drive circuit is improving constantly, because the mobility of amorphous silicon film transistor is generally at 0.5cm 2About/VS, and the LCD size is when surpassing 80in, and driving frequency surpasses 120Hz, needs 1cm 2The mobility that/VS is above, existing amorphous silicon film transistor mobility is difficult to satisfy the demands.The mobility of metal oxide thin-film transistor is high, homogeneity is good, transparent; Can satisfy the demand of large scale liquid crystal display and active organic electroluminescent better; Therefore the high-performance metal oxide thin film transistor enjoys people's attention, has become nearest research focus.
Summary of the invention
The purpose of this invention is to provide a kind of array base palte and manufacturing approach thereof, display unit, adopt the manufacturing that four times composition technology realizes array base palte, thereby shorten the production time, enhance productivity, reduce production costs.
To achieve these goals, the present invention provides a kind of manufacturing approach of array base palte, comprising:
The figure of
step1, formation ground floor pixel electrode, grid line and gate electrode;
The figure of
step2, formation active layer;
The figure on
step3, formation protective layer and barrier layer;
The figure of
step4, formation second layer pixel electrode, source-drain electrode and data wire
Above-mentioned manufacturing approach, wherein:
Said
step1 comprises: on substrate, form transparent conductive film and grid metallic film, form the figure of ground floor pixel electrode, grid line and gate electrode through composition technology;
Said
step2 comprises: form gate insulation layer and active layer, form the figure of active layer through composition technology;
Said
step3 comprises: form insulating barrier, through the figure on composition technology formation protective layer and barrier layer, said barrier layer is positioned at the channel region top of said active layer;
Said
step4 comprises: form transparent conductive film and source and leak metallic film, form the figure of second layer pixel electrode, source-drain electrode and data wire through composition technology.
Above-mentioned manufacturing approach, wherein, the material of said active layer is a metal oxide.
To achieve these goals, the present invention also provides a kind of array base palte, comprising:
Be formed on ground floor pixel electrode, grid line and gate electrode on the substrate;
Be formed on the gate insulation layer on ground floor pixel electrode, grid line and the gate electrode;
Be formed on active layer and protective layer on the gate insulation layer, and the barrier layer that is formed on the channel region top of active layer;
Be formed on the source-drain electrode and the data wire of active layer top, and be formed on the second layer pixel electrode on the protective layer.
Above-mentioned array base palte, wherein, the material of said active layer is a metal oxide.
To achieve these goals, the present invention also provides a kind of display unit, wherein, comprises above-mentioned array base palte.
Can find out from the above; Technique scheme provided by the invention in the process of making FFS type TFT, utilizes a composition technology to accomplish etching barrier layer and protective layer; Just can realize the manufacturing of array base palte like this through four composition technology; Thereby shortened the production time, improved production efficiency, reduced production cost.
Description of drawings
Fig. 1 is the sectional view of the array base palte of the embodiment of the invention;
Fig. 2 is the manufacturing approach flow chart of the array base palte of the embodiment of the invention;
Fig. 3 is the sectional view of the embodiment of the invention behind deposit transparent conductive film and grid metallic film;
Fig. 4 is the sectional view of the embodiment of the invention after passing through gray tone or half-tone mask plate exposure imaging in the composition technology first time;
Fig. 5 is the sectional view of the embodiment of the invention after accomplishing the composition technology first time;
Fig. 6 is the sectional view of the embodiment of the invention after accomplishing the composition technology second time;
Fig. 7 is the sectional view of the embodiment of the invention after accomplishing composition technology for the third time;
Fig. 8 is the sectional view of the embodiment of the invention behind deposit transparent conductive film and source leakage metallic film;
Fig. 9 is the sectional view the embodiment of the invention is passed through gray tone or half-tone mask plate exposure imaging in the 4th composition technology after.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing and specific embodiment to describe the present invention below.
Fig. 1 is the sectional view of the array base palte of the embodiment of the invention, and with reference to Fig. 1, this array base palte comprises:
Be formed on ground
floor pixel electrode2, grid line (not shown) and
gate electrode3 draws on the
substrate1;
Be formed on the
gate insulation layer4 on ground
floor pixel electrode2, grid line and the
gate electrode3;
Be formed on
active layer5 and protective layer 6 on the
gate insulation layer4, and the
barrier layer7 that is formed on the channel region top of
active layer5;
Be formed on the source-
drain electrode9 and data wire (not shown) of
active layer5 tops, and be formed on the second
layer pixel electrode8 on the protective layer 6.
The method that forms above-mentioned each layer pattern of array base palte can be the deposition of advanced row metal; Adopt then to comprise that the composition technology of mask, etching etc. realizes, can also directly carry out composition technologies commonly used such as silk screen printing, printing for the deposition of not carrying out metal and realize.Those skilled in the art can select according to concrete demand.
The mobility of metal oxide thin-film transistor is high, homogeneity is good, transparent, can satisfy the demand of large scale liquid crystal display and active organic electroluminescent better.Therefore, as a preferred version, the material of the said
active layer5 in the above-mentioned array base palte of the embodiment of the invention is a metal oxide, for example, and IGZO, IZO, ZnO etc.High mobility and FFS molded breadth visual angle through with metal oxide combine, and make this array base palte in large scale TFT-LCD, to be widely used, and possess high aperture simultaneously, advantage such as high mobility and wide visual angle.
In addition, for the array base palte of this kind structure, can protective layer 6 and
barrier layer7 be combined into a mask plate (Mask) and accomplish; Just can realize the manufacturing of array base palte like this through four composition technology; So, can simplify the manufacturing process of array base palte, reduce production costs.
Fig. 2 is the manufacturing approach flow chart of the array base palte of the embodiment of the invention, and with reference to Fig. 2, this manufacturing approach comprises the steps:
Step 100: deposit transparent conductive film and grid metallic film successively on substrate, through the first time composition technology form the figure of ground floor pixel electrode, grid line and gate electrode;
One substrate at first is provided, and said substrate can be selected glass substrate or quartz base plate for use; Then; As shown in Figure 3; Adopt sputter, thermal evaporation or other film build method on substrate successively deposit thickness be the transparent conductive film 21 of 30-50nm and the metal level 31 that thickness is 200-400nm, said transparent conductive film can be tin indium oxide, zinc-tin oxide etc., metal level 31 can be Cu, Al, Mo, Ti etc.; Said transparent conductive film 21 is used to form said ground floor pixel electrode, and said metal level 31 is used to form said grid line and said gate electrode; At last, as shown in Figure 5, through the figure of composition technology formation first time ground floor pixel electrode, grid line and gate electrode.
Step 200: on the substrate of completing
steps100, deposit gate insulation layer and active layer successively, through the figure of composition technology formation second time active layer;
At first; Using plasma strengthens chemical vapour deposition (CVD) (PECVD) or magnetically controlled sputter method; Deposit thickness is that gate insulation layer and the thickness of 30nm-80nm is the active layer of 20nm-50nm successively on the substrate of completing
steps100, and wherein, gate insulation layer can be selected oxide or nitride for use; The material of active layer is preferably metal oxide, and said metal oxide can be IGZO, ZnO or IZO etc.; Then, as shown in Figure 6, through the figure of composition technology formation second time active layer.
Step 300: depositing insulating layer on the substrate of completing
steps200, form the figure on protective layer and barrier layer through composition technology for the third time, said barrier layer is positioned at above the channel region of said active layer;
At first, adopt PECVD or magnetically controlled sputter method, deposit thickness is the insulating barrier of 100nm-200nm on the substrate of completing
steps200, and wherein, insulating barrier can be selected oxide or nitride for use; Then, as shown in Figure 7, form the figure on protective layer and barrier layer through composition technology for the third time.
Step 400: metallic film is leaked in deposit transparent conductive film and source successively on the substrate of completing
steps300, forms the figure of second layer pixel electrode, source-drain electrode and data wire through the 4th composition technology.
At first; As shown in Figure 8; Adopt sputter, thermal evaporation or other film build method on the substrate of completing
steps300 successively deposit thickness be that transparent conductive film and the thickness of 30-50nm is the metal level of 200-400nm, said transparent conductive film can be tin indium oxide, zinc-tin oxide etc., metal level can be Cu, Al, Mo, Ti etc.; Said transparent conductive film is used to form said second layer pixel electrode, and said metal level is used to form said data wire and said source-drain electrode; Then, as shown in Figure 1, through the figure of the 4th composition technology formation second layer pixel electrode, source-drain electrode and data wire.
Below provide the detailed process of composition technology in the above-mentioned manufacturing approach.
In
step100, said figure through the ground floor of composition technology formation for the first time pixel electrode, grid line and gate electrode specifically comprises:
Step S11: on the grid metallic film, apply one
deck photoresist10;
Step S12: adopt gray tone or half-tone mask plate that photoresist is made public; Make photoresist form photoresist not reserve area, photoresist part reserve area and the complete reserve area of photoresist; Wherein, The figure region of corresponding grid line of the complete reserve area of photoresist and gate electrode, the corresponding ground floor pattern of pixel electrodes of photoresist part reserve area region, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Step S13: carry out development treatment, the photoresist not photoresist of reserve area is removed fully, the photoresist thickness attenuation of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
The figure that development obtains is as shown in Figure 4, and among the figure, WP is a not reserve area of photoresist, and HP is a photoresist part reserve area, and NP is the complete reserve area of photoresist.
Step S14: etch away photoresist not the grid metallic film and the transparent conductive film of reserve area, form the figure of grid line and gate electrode;
Step S15:, keep the photoresist of the complete reserve area of photoresist through the photoresist of cineration technics removal photoresist part reserve area;
Step S16: etch away the grid metallic film of photoresist part reserve area, form the ground floor pattern of pixel electrodes;
Step S17: remove remaining photoresist.
In
step200, said figure through the active layer of composition technology formation for the second time specifically comprises:
Step S21: on active layer, apply one deck photoresist;
Step S22: adopt mask plate that photoresist is made public; Make not reserve area of photoresist formation photoresist reserve area and photoresist; Wherein, the figure region of the corresponding active layer of photoresist reserve area, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Step S23: carry out development treatment, the photoresist not photoresist of reserve area is removed fully, and the photoresist thickness of photoresist reserve area remains unchanged;
Step S24: etch away the not active layer of reserve area of photoresist, form the figure of active layer;
Step S25: remove remaining photoresist.
In
step300, saidly form the figure on protective layer and barrier layer through composition technology for the third time, specifically comprise:
Step S31: on insulating barrier, apply one deck photoresist;
Step S32: adopt mask plate that photoresist is made public; Make not reserve area of photoresist formation photoresist reserve area and photoresist; Wherein, the figure region on corresponding protective layer of photoresist reserve area and barrier layer, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Step S33: carry out development treatment, the photoresist not photoresist of reserve area is removed fully, and the photoresist thickness of photoresist reserve area remains unchanged;
Step S34: etch away the not insulating barrier of reserve area of photoresist, form the figure on protective layer and barrier layer;
Step S35: remove remaining photoresist.
Through composition technology for the third time, formed TFT raceway groove via hole, be used for the electric connection of source-drain electrode and active layer.In addition, in composition technology for the third time, also can form the external via hole of grid line simultaneously.
In
step400, the said figure that passes through the 4th composition technology formation second layer pixel electrode, source-drain electrode and data wire specifically comprises:
Step S41: leak coating one
deck photoresist11 on the metallic film in the source;
Step S42: adopt gray tone or half-tone mask plate that photoresist is made public; Make photoresist form photoresist not reserve area, photoresist part reserve area and the complete reserve area of photoresist; Wherein, The figure region of corresponding source-drain electrode of the complete reserve area of photoresist and data wire, the corresponding second layer pattern of pixel electrodes of photoresist part reserve area region, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Step S43: carry out development treatment, the photoresist not photoresist of reserve area is removed fully, the photoresist thickness attenuation of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
The figure that development obtains is as shown in Figure 9, and among the figure, WP is a not reserve area of photoresist, and HP is a photoresist part reserve area, and NP is the complete reserve area of photoresist.
Step S44: etch away photoresist and do not leak metallic film and transparent conductive film in the source of reserve area, form the figure of source-drain electrode and data wire;
Step S45:, keep the photoresist of the complete reserve area of photoresist through the photoresist of cineration technics removal photoresist part reserve area;
Step S46: metallic film is leaked in the source that etches away photoresist part reserve area, forms second layer pattern of pixel electrodes;
Step S47: remove remaining photoresist.
In the above-mentioned composition technology, the formation of photoresist is to be example with the mode that applies, can certainly adopt mode such as deposition to form photoresist.
The embodiment of the invention also provides a kind of display unit, it is characterized in that, comprising: color membrane substrates; Be engaged in the thin-film transistor array base-plate of said color membrane substrates; Be located in the liquid crystal layer between said color membrane substrates and the said thin-film transistor array base-plate.Said thin-film transistor array base-plate comprises:
Be formed on ground floor pixel electrode, grid line and gate electrode on the substrate;
Be formed on the gate insulation layer on grid line, gate electrode and the ground floor pixel electrode;
Be formed on active layer and protective layer on the gate insulation layer, and the barrier layer that is formed on the channel region top of active layer;
Be formed on the source-drain electrode and the data wire of active layer top, and be formed on the second layer pixel electrode on the protective layer.
Preferably, the material of said active layer is a metal oxide.
Need to prove that above-mentioned display unit can not limit it at this for display panels, LCD, LCD TV, AMOLED display floater, AMOLED display etc.
In sum; The technique scheme that the embodiment of the invention provides in the process of making FFS type TFT, utilizes a composition technology to accomplish etching barrier layer and protective layer; Just can realize the manufacturing of array base palte like this through four composition technology; Thereby shortened the production time, improved production efficiency, reduced production cost.
Should be noted that at last; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. the manufacturing approach of an array base palte is characterized in that, comprising:
The figure of step 1, formation ground floor pixel electrode, grid line and gate electrode;
The figure of step 2, formation active layer;
The figure on step 3, formation protective layer and barrier layer;
The figure of step 4, formation second layer pixel electrode, source-drain electrode and data wire.
2. manufacturing approach as claimed in claim 1 is characterized in that:
Said step 1 comprises: on substrate, form transparent conductive film and grid metallic film, form the figure of ground floor pixel electrode, grid line and gate electrode through composition technology;
Said step 2 comprises: form gate insulation layer and active layer, form the figure of active layer through composition technology;
Said step 3 comprises: form insulating barrier, through the figure on composition technology formation protective layer and barrier layer, said barrier layer is positioned at the channel region top of said active layer;
Said step 4 comprises: form transparent conductive film and source and leak metallic film, form the figure of second layer pixel electrode, source-drain electrode and data wire through composition technology.
3. manufacturing approach as claimed in claim 2 is characterized in that, said figure through composition technology formation ground floor pixel electrode, grid line and gate electrode comprises:
On the grid metallic film, form one deck photoresist;
Adopt gray tone or half-tone mask plate that photoresist is made public; Make photoresist form photoresist not reserve area, photoresist part reserve area and the complete reserve area of photoresist; Wherein, The figure region of corresponding grid line of the complete reserve area of photoresist and gate electrode, the corresponding ground floor pattern of pixel electrodes of photoresist part reserve area region, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Carry out development treatment, the photoresist not photoresist of reserve area is removed fully, the photoresist thickness attenuation of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
Remove photoresist not the grid metallic film and the transparent conductive film of reserve area, form the figure of grid line and gate electrode;
Through the photoresist of cineration technics removal photoresist part reserve area, keep the photoresist of the complete reserve area of photoresist;
Remove the grid metallic film of photoresist part reserve area, form the ground floor pattern of pixel electrodes;
Remove remaining photoresist.
4. manufacturing approach as claimed in claim 2 is characterized in that, said figure through composition technology formation active layer comprises:
On active layer, form one deck photoresist;
Adopt mask plate that photoresist is made public, make not reserve area of photoresist formation photoresist reserve area and photoresist, wherein, the figure region of the corresponding active layer of photoresist reserve area, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Carry out development treatment, the photoresist not photoresist of reserve area is removed fully, and the photoresist thickness of photoresist reserve area remains unchanged;
Remove the not active layer of reserve area of photoresist, form the figure of active layer;
Remove remaining photoresist.
5. manufacturing approach as claimed in claim 2 is characterized in that, said figure through composition technology formation protective layer and barrier layer comprises:
On insulating barrier, form one deck photoresist;
Adopt mask plate that photoresist is made public; Make not reserve area of photoresist formation photoresist reserve area and photoresist; Wherein, the figure region on corresponding protective layer of photoresist reserve area and barrier layer, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Carry out development treatment, the photoresist not photoresist of reserve area is removed fully, and the photoresist thickness of photoresist reserve area remains unchanged;
Remove the not insulating barrier of reserve area of photoresist, form the figure on protective layer and barrier layer;
Remove remaining photoresist.
6. manufacturing approach as claimed in claim 2 is characterized in that, said figure through composition technology formation second layer pixel electrode, source-drain electrode and data wire comprises:
Leak formation one deck photoresist on the metallic film in the source;
Adopt gray tone or half-tone mask plate that photoresist is made public; Make photoresist form photoresist not reserve area, photoresist part reserve area and the complete reserve area of photoresist; Wherein, The figure region of corresponding source-drain electrode of photoresist reserve area and data wire, the corresponding second layer pattern of pixel electrodes of photoresist part reserve area region, photoresist is the zone beyond the corresponding above-mentioned figure of reserve area not;
Carry out development treatment, the photoresist not photoresist of reserve area is removed fully, the photoresist thickness attenuation of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
Remove photoresist and do not leak metallic film and transparent conductive film in the source of reserve area, form the figure of source-drain electrode and data wire;
Through the photoresist of cineration technics removal photoresist part reserve area, keep the photoresist of the complete reserve area of photoresist;
Metallic film is leaked in the source of removing photoresist part reserve area, forms second layer pattern of pixel electrodes;
Remove remaining photoresist.
7. manufacturing approach as claimed in claim 1 is characterized in that:
The material of said active layer is a metal oxide.
8. an array base palte is characterized in that, comprising:
Be formed on ground floor pixel electrode, grid line and gate electrode on the substrate;
Be formed on the gate insulation layer on ground floor pixel electrode, grid line and the gate electrode;
Be formed on active layer and protective layer on the gate insulation layer, and the barrier layer that is formed on the channel region top of active layer;
Be formed on the source-drain electrode and the data wire of active layer top, and be formed on the second layer pixel electrode on the protective layer.
9. array base palte as claimed in claim 8 is characterized in that:
The material of said active layer is a metal oxide.
10. a display unit is characterized in that, comprises like claim 8 or 9 described array base paltes.
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