CN102723340B - A kind of SOI BJT two strain plane BiCMOS integrated device and preparation method - Google Patents

本发明公开了一种SOI BJT双应变平面BiCMOS集成器件及制备方法，SOI衬底片上生长N型Si外延作集电区，制备深槽隔离，在双极器件区域制造常规的Si双极晶体管；利用干法刻蚀工艺刻蚀出MOS器件有源区深槽，在槽中分别选择性外延生长：P型Si层、P型SiGe渐变层、P型SiGe层、P型应变Si层作为NMOS器件有源区和N型Si层、N型应变SiGe层、N型Si帽层作为PMOS器件有源区；制备虚栅极，分别进行MOS器件LDD注入，淀积SiO₂，制备侧墙，自对准形成NMOS和PMOS器件源漏；刻蚀虚栅，淀积SiON栅介质层和W-TiN复合栅，最终构成沟道为22～45nm的BiCMOS集成器件。该方法充分利用电子迁移率高的张应变Si和空穴迁移率高的压应变SiGe分别作为NMOS和PMOS器件的导电沟道，有效地提高了BiCMOS集成器件及电路的性能。

The invention discloses an SOI BJT dual-strain plane BiCMOS integrated device and a preparation method thereof, wherein N-type Si epitaxy is grown on an SOI substrate as a collector area, deep groove isolation is prepared, and conventional Si bipolar transistors are manufactured in the bipolar device area; Use the dry etching process to etch deep grooves in the active area of MOS devices, and selectively epitaxially grow in the grooves: P-type Si layer, P-type SiGe gradient layer, P-type SiGe layer, and P-type strained Si layer as NMOS devices The active area and N-type Si layer, N-type strained SiGe layer, and N-type Si cap layer are used as the active area of the PMOS device; dummy gates are prepared, LDD implantation of MOS devices is performed respectively, SiO ₂ is deposited, side walls are prepared, and self-alignment Form the source and drain of NMOS and PMOS devices; etch the dummy gate, deposit SiON gate dielectric layer and W-TiN composite gate, and finally form a BiCMOS integrated device with a channel of 22-45nm. The method makes full use of tensile-strained Si with high electron mobility and compressive-strained SiGe with high hole mobility as the conductive channels of NMOS and PMOS devices, respectively, and effectively improves the performance of BiCMOS integrated devices and circuits.

一种SOI BJT双应变平面BiCMOS集成器件及制备方法A kind of SOI BJT dual-strain plane BiCMOS integrated device and its preparation method

技术领域 technical field

本发明属于半导体集成电路技术领域，尤其涉及一种SOI BJT、双应变平面BiCMOS集成器件及制备方法。 The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to an SOI BJT and double strain plane BiCMOS integrated device and a preparation method.

背景技术 Background technique

1958年出现的集成电路是20世纪最具影响的发明之一。基于这项发明而诞生的微电子学已成为现有现代技术的基础，加速改变着人类社会的知识化、信息化进程，同时也改变了人类的思维方式；它不仅为人类提供了强有力的改造自然的工具，而且还开拓了一个广阔的发展空间。 The integrated circuit, which appeared in 1958, is one of the most influential inventions of the 20th century. Microelectronics based on this invention has become the basis of existing modern technology, accelerating the process of knowledge and informationization of human society, and at the same time changing the way of thinking of human beings; it not only provides human beings with powerful It is not only a tool for transforming nature, but also opens up a broad space for development.

半导体集成电路已成为电子工业的基础，人们对电子工业的巨大需求，促使该领域的发展十分迅速；在过去的几十年中，电子工业的迅猛发展对社会发展及国民经济产生了巨大的影响；目前，电子工业已成为世界上规模最大的工业，在全球市场中占据着很大的份额，产值已经超过了10000亿美元。 Semiconductor integrated circuits have become the basis of the electronics industry. People's huge demand for the electronics industry has prompted the rapid development of this field; in the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. ; At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars.

硅材料作为半导体材料应用经历了50多年，传统的Si CMOS和BiCMOS技术以其低功耗、低噪声、高输入阻抗、高集成度、可靠性好等优点在集成电路领域占据着主导地位，并按照摩尔定律不断的向前发展；目前，全球90%的半导体市场中，都是Si基集成电路。 Silicon materials have been used as semiconductor materials for more than 50 years. Traditional Si CMOS and BiCMOS technologies occupy a dominant position in the field of integrated circuits due to their low power consumption, low noise, high input impedance, high integration, and good reliability. Continuously develop according to Moore's Law; at present, 90% of the global semiconductor market is Si-based integrated circuits.

但是随着器件特征尺寸减小、集成度和复杂性的增强，出现了一系列涉及材料、器件物理、器件结构和工艺技术等方面的新问题；特别是当IC芯片特征尺寸进入纳米尺度，从器件角度看，纳米尺度器件中的短沟效应、强场效应、量子效应、寄生参量的影响、工艺参数涨落等问题对器件泄漏电流、亚阈特性、 开态、关态电流等性能的影响越来越突出，电路速度和功耗的矛盾也将更加严重，另一方面，随着无线移动通信的飞速发展，对器件和电路的性能，如频率特性、噪声特性、封装面积、功耗和成本等提出了更高的要求，传统硅基工艺制备的器件和集成电路尤其是模拟和混合信号集成电路，越来越无法满足新型、高速电子系统的需求。 However, with the reduction of device feature size and the enhancement of integration and complexity, a series of new issues involving materials, device physics, device structure and process technology have emerged; especially when the feature size of IC chips enters the nanometer scale, from From the perspective of devices, the effects of short channel effects, strong field effects, quantum effects, parasitic parameters, process parameter fluctuations and other issues in nanoscale devices on device leakage current, sub-threshold characteristics, on-state, off-state current and other performance As it becomes more and more prominent, the contradiction between circuit speed and power consumption will become more serious. On the other hand, with the rapid development of wireless mobile communication, the performance of devices and circuits, such as frequency characteristics, noise characteristics, packaging area, power consumption and Higher requirements have been put forward for cost, etc. Devices and integrated circuits prepared by traditional silicon-based processes, especially analog and mixed-signal integrated circuits, are increasingly unable to meet the needs of new, high-speed electronic systems.

Si材料的优良特性，特别是能方便地形成极其有用的绝缘膜——SiO₂膜和Si₃N₄膜，从而能够利用Si材料实现最廉价的集成电路工艺，发展至今，全世界数以万亿美元的设备和技术投入，已使Si基工艺形成了非常强大的产业能力；同时，长期的科研投入也使人们对Si及其工艺的了解，达到十分深入、透彻的地步，因此在集成电路产业中，Si技术是主流技术，Si集成电路产品是主流产品，占集成电路产业的90％以上；在Si集成电路中以双极晶体管作为基本结构单元的模拟集成电路在电子系统中占据着重要的地位，随着Si技术的发展，Si双极晶体管的性能也获得了大幅的提高。 The excellent characteristics of Si materials, especially the ability to easily form extremely useful insulating films - SiO ₂ film and Si ₃ N ₄ film, so that Si materials can be used to realize the cheapest integrated circuit technology, so far, tens of thousands of The investment of US$100 million in equipment and technology has enabled Si-based technology to form a very strong industrial capability; at the same time, long-term scientific research investment has also enabled people to understand Si and its technology to a very deep and thorough level. In the industry, Si technology is the mainstream technology, and Si integrated circuit products are the mainstream products, accounting for more than 90% of the integrated circuit industry; in the Si integrated circuit, the analog integrated circuit with bipolar transistor as the basic structural unit occupies an important position in the electronic system. With the development of Si technology, the performance of Si bipolar transistors has also been greatly improved.

为了提高器件及集成电路的性能，研究人员借助新型的半导体材料如：GaAs、InP等，以获得适于无线移动通信发展的高速器件及集成电路；尽管GaAs和InP基化合物器件频率特性优越，但其制备工艺比Si工艺复杂、成本高，大直径单晶制备困难、机械强度低，散热性能不好，与Si工艺难兼容以及缺乏像SiO₂那样的钝化层等因素限制了它的广泛应用和发展。 In order to improve the performance of devices and integrated circuits, researchers use new semiconductor materials such as GaAs, InP, etc. to obtain high-speed devices and integrated circuits suitable for the development of wireless mobile communications; although GaAs and InP-based compound devices have superior frequency characteristics, but Its preparation process is more complicated than Si process, high cost, difficult to prepare large-diameter single crystal, low mechanical strength, poor heat dissipation performance, incompatibility with Si process and lack of passivation layer like SiO ₂ and other factors limit its wide application And development.

因此，目前工业界在制造大规模集成电路尤其是数模混合集成电路时，仍然采用Si BiCMOS（Si BiCMOS为Si双极晶体管BJT+Si CMOS）。 Therefore, the industry still uses Si BiCMOS (Si BiCMOS is Si bipolar transistor BJT+Si CMOS) when manufacturing large-scale integrated circuits, especially digital-analog hybrid integrated circuits.

今年开发出利用绝缘表面上存在有较薄的单晶半导体层的SOI（Silicon on Insulator:绝缘体上硅）衬底来代替大块状硅片的集成电路，通过使用SOI衬底，可以减小晶体管的漏极与衬底间的寄生电容，为此SOI衬底因其可以提高半导体集成电路的性能而受到瞩目。 This year, an integrated circuit that uses an SOI (Silicon on Insulator: silicon on insulator) substrate with a thinner single crystal semiconductor layer on the insulating surface to replace a large silicon wafer has been developed. By using the SOI substrate, the transistor can be reduced The parasitic capacitance between the drain and the substrate, so the SOI substrate has attracted attention because it can improve the performance of semiconductor integrated circuits.

发明内容 Contents of the invention

本发明的目的在于提供一种SOI BJT、双应变平面BiCMOS集成器件及制备方法，以实现在不改变现有设备和增加成本的条件下，制备出22～45nm的SOI BJT、双应变平面BiCMOS集成器件及集成电路。 The object of the present invention is to provide a kind of SOI BJT, dual-strain plane BiCMOS integrated device and its preparation method, to realize the SOI BJT of 22～45nm, double strain plane BiCMOS integrated device under the condition of not changing existing equipment and increasing cost. devices and integrated circuits.

本发明的目的在于提供一种SOI BJT、双应变平面BiCMOS集成器件，采用SOI普通Si双极晶体管，应变Si平面沟道NMOS器件和应变SiGe平面沟道PMOS器件。 The object of the present invention is to provide a kind of SOI BJT, double strain plane BiCMOS integrated device, adopt SOI ordinary Si bipolar transistor, strain Si planar channel NMOS device and strain SiGe planar channel PMOS device.

进一步、NMOS器件导电沟道为应变Si材料，沿沟道方向为张应变。 Further, the conduction channel of the NMOS device is a strained Si material, and the tensile strain is in the direction of the channel.

进一步、PMOS器件导电沟道为应变SiGe材料，沿沟道方向为压应变。 Further, the conduction channel of the PMOS device is a strained SiGe material, and the direction of the channel is a compressive strain.

进一步、在同一个SOI衬底上双极器件采用体Si材料制备。  Further, the bipolar device is fabricated using bulk Si material on the same SOI substrate. the

进一步、PMOS器件采用量子阱结构。 Further, the PMOS device adopts a quantum well structure.

本发明的另一目的在于提供一种SOI BJT、双应变平面BiCMOS集成器件的制备方法，该制备方法包括如下步骤： Another object of the present invention is to provide a kind of preparation method of SOI BJT, double strain plane BiCMOS integrated device, and this preparation method comprises the steps:

第一步、选取氧化层厚度为150~400nm，上层Si厚度为100～150nm，N型掺杂浓度为1×10¹⁶～1×10¹⁷cm^-3的SOI衬底片； The first step is to select an SOI substrate with an oxide layer thickness of 150-400nm, an upper Si thickness of 100-150nm, and an N-type doping concentration of 1×10 ¹⁶ to 1×10 ¹⁷ cm ^-3 ;

第二步、在SOI衬底上外延生长一层掺杂浓度为1×10¹⁶～1×10¹⁷cm^-3的Si层，厚度为300～400nm，作为集电区； The second step is to epitaxially grow a Si layer with a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁷ cm ^-3 on the SOI substrate, with a thickness of 300 to 400 nm, as the collector region;

第三步、在衬底表面热氧化一层厚度为300～500nm的SiO₂层，光刻隔离区域，利用干法刻蚀工艺，在深槽隔离区域刻蚀出深度为3~5μm的深槽；利用化学汽相淀积（CVD）的方法，在600～800℃，在深槽内填充SiO₂，用化学机械抛光（CMP）方法，去除表面多余的氧化层，形成深槽隔离； The third step is to thermally oxidize a layer of _SiO2 with a thickness of 300-500nm on the surface of the substrate, photolithographically isolate the area, and use a dry etching process to etch a deep groove with a depth of 3-5μm in the deep groove isolation area ;Using chemical vapor deposition (CVD) method, at 600-800 ℃, fill SiO ₂ in the deep groove, and use chemical mechanical polishing (CMP) method to remove the redundant oxide layer on the surface to form deep groove isolation;

第四步、光刻集电区接触区，对集电区进行N型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为1×10¹⁹～1×10²⁰cm^-3的重掺杂集电极； Step 4: Lithograph the contact area of the collector region, implant N-type impurities into the collector region, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 1×10 ¹⁹ to 1×10 ²⁰ cm ^-3 heavily doped collector;

第五步、在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为1×10¹⁸～5×10¹⁸cm^-3的基区； The fifth step is to thermally oxidize a _SiO2 layer on the surface of the substrate, photolithography the base area, implant P-type impurities into the base area, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 1 Base area of ×10 ¹⁸ ～5×10 ¹⁸ cm ^-3 ;

第六步、在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为5×10¹⁹～5×10²⁰cm^-3的重掺杂发射区，在衬底表面利用化学汽相淀积（CVD）的方法，在600～800℃，淀积一SiO₂层； The sixth step is to thermally oxidize a _SiO2 layer on the surface of the substrate, photolithography the emission area, implant N-type impurities into the substrate, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 5 For the heavily doped emitter region of ×10 ¹⁹ to 5×10 ²⁰ cm ^-3 , a SiO ₂ layer is deposited on the surface of the substrate by chemical vapor deposition (CVD) at 600-800°C;

第七步、光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区刻蚀出深度为1.92～2.82μm的深槽；然后在深槽中，利用化学汽相淀积（CVD）的方法，在600～750℃，连续生长四层材料：第一层是厚度为200～400nm的P型Si缓冲层，掺杂浓度为5×10¹⁵～5×10¹⁶cm^-3，第二层是厚度为1.5～2μm的P型SiGe渐变层，底部Ge组分是0%，顶部Ge组分是15～25%，掺杂浓度为5×10¹⁵～5×10¹⁶cm^-3，第三层是Ge组分为15～25%，厚度为200～400nm的P型SiGe层，掺杂浓度为5×10¹⁶～5×10¹⁷cm^-3，第四层是厚度为15～20nm的P型应变Si层，掺杂浓度为5×10¹⁶～5×10¹⁷cm^-3作为NMOS器件的沟道，形成NMOS器件有源区； The seventh step is to lithographically etch the active area of the NMOS device, and use a dry etching process to etch a deep groove with a depth of 1.92 to 2.82 μm in the active area of the NMOS device; then in the deep groove, use chemical vapor deposition (CVD) method, at 600-750°C, continuously grow four layers of materials: the first layer is a P-type Si buffer layer with a thickness of 200-400nm, and the doping concentration is 5×10 ¹⁵ ～5×10 ¹⁶ cm ^-3 , the second layer is a P-type SiGe graded layer with a thickness of 1.5-2 μm, the bottom Ge composition is 0%, the top Ge composition is 15-25%, and the doping concentration is 5×10 ¹⁵ ～5×10 ¹⁶ cm ^{- 3.} The third layer is a P-type SiGe layer with a Ge composition of 15-25% and a thickness of 200-400nm. The doping concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 . ~20nm P-type strained Si layer with a doping concentration of 5×10 ¹⁶ ~5×10 ¹⁷ cm ^-3 as the channel of the NMOS device, forming the active region of the NMOS device;

第八步、利用化学汽相淀积（CVD）的方法，在600～800℃，在衬底表面淀积一层SiO₂，光刻PMOS器件有源区，利用干法刻蚀工艺，在PMOS器件有源区刻蚀出深度为1.92～2.82μm的深槽；然后在深槽中利用化学汽相淀积（CVD）的方法，在600～750℃，选择性外延生长三层材料：第一层是厚度为1.9～2.8μm的N型弛豫Si层，掺杂浓度为5×10¹⁶～5×10¹⁷cm^-3；第二层是厚 度为12～15nm的N型应变SiGe层，掺杂浓度为5×10¹⁶～5×10¹⁷cm^-3，Ge组分为15～25%；第三层是厚度为3～5nm的本征弛豫Si层，形成PMOS器件有源区；利用湿法腐蚀，刻蚀掉表面的层SiO₂； Step 8: Deposit a layer of SiO ₂ on the surface of the substrate at 600-800°C by chemical vapor deposition (CVD), photolithographically etch the active area of the PMOS device, and use a dry etching process to place a layer of SiO 2 on the surface of the PMOS A deep groove with a depth of 1.92-2.82 μm is etched in the active area of the device; then, in the deep groove, chemical vapor deposition (CVD) is used to selectively grow three layers of materials at 600-750°C: the first The first layer is an N-type relaxed Si layer with a thickness of 1.9-2.8 μm, and the doping concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 ; the second layer is an N-type strained SiGe layer with a thickness of 12-15 nm, doped The dopant concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 , and the Ge composition is 15-25%; the third layer is an intrinsically relaxed Si layer with a thickness of 3-5nm, which forms the active region of the PMOS device; Wet etching, etching away the SiO ₂ layer on the surface;

第九步、利用化学汽相淀积（CVD）的方法，在600～800℃，在衬底表面淀积一层厚度为3～5nm的SiO₂，作为NMOS器件和PMOS器件的栅介质层，然后再利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积一层厚度为200～300nm的Poly-Si，刻蚀Poly-Si和SiO₂层，形成NMOS器件和PMOS器件的虚栅； Step 9: Deposit a layer of SiO ₂ with a thickness of 3-5nm on the surface of the substrate at 600-800°C by chemical vapor deposition (CVD) as the gate dielectric layer of NMOS devices and PMOS devices. Then use the chemical vapor deposition (CVD) method to deposit a layer of Poly-Si with a thickness of 200-300nm on the surface of the substrate at 600-800°C, etch the Poly-Si and _SiO2 layers to form NMOS devices. and the dummy gate of the PMOS device;

第十步、光刻NMOS器件有源区，对NMOS器件进行N型离子注入，形成掺杂浓度为1～5×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）；光刻PMOS器件有源区，对PMOS器件进行P型离子注入，形成掺杂浓度为1～5×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）； Step 10: Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and form an N-type lightly doped source-drain structure (N-LDD) with a doping concentration of 1 to 5×10 ¹⁸ cm ^-3 ; Lithograph the active area of the PMOS device, and perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1 to 5×10 ¹⁸ cm ^-3 ;

第十一步、利用化学汽相淀积（CVD）的方法，在600～800℃，在衬底表面上淀积一层厚度为3～5nm的SiO₂，利用干法刻蚀，刻蚀衬底表面上的SiO₂，保留Ploy-Si侧壁部分，形成NMOS器件和PMOS器件栅电极侧墙；光刻NMOS器件有源区，对NMOS器件进行N型离子注入，自对准生成杂质浓度为5×10¹⁹～1×10²⁰cm^-3的NMOS器件源漏区；光刻PMOS器件有源区，对PMOS器件进行P型离子注入，自对准生成杂质浓度为5×10¹⁹～1×10²⁰cm^-3的PMOS器件源漏区； The eleventh step, using chemical vapor deposition (CVD), deposit a layer of SiO ₂ with a thickness of 3-5nm on the surface of the substrate at 600-800°C, and use dry etching to etch the lining. SiO ₂ on the bottom surface, retaining the sidewall part of Poly-Si, forming NMOS device and PMOS device gate electrode sidewall; photolithography of NMOS device active area, N-type ion implantation for NMOS device, self-alignment generated impurity concentration is 5×10 ¹⁹ ～1×10 ²⁰ cm ^-3 source and drain regions of NMOS devices; photolithography of PMOS device active regions, P-type ion implantation for PMOS devices, and self-alignment to generate impurity concentrations of 5×10 ¹⁹ ～1× 10 ²⁰ cm ^-3 source and drain regions of PMOS devices;

第十二步、利用化学汽相淀积（CVD）的方法，在600～800℃，在衬底表面淀积一层厚度为400～500nm的SiO₂层；利用化学机械抛光（CMP）方法平整表面，再用干法刻蚀工艺刻蚀表面SiO₂至虚栅上表面，露出虚栅；湿法刻蚀虚栅，在栅电极处形成一个凹槽；利用化学汽相淀积（CVD）的方法，在600～800℃，在衬底表面淀积一层SiON，厚度为1.5~5nm；利用物理气相沉积（PVD） 的方法，淀积W-TiN复合栅，利用化学机械抛光（CMP）方法去掉表面的金属，以W-TiN复合栅作为化学机械抛光（CMP）的终止层，从而形成NMOS器件和PMOS器件栅极； The twelfth step, using the chemical vapor deposition (CVD) method, at 600-800 ° C, deposit a SiO ₂ layer with a thickness of 400-500 nm on the substrate surface; use chemical mechanical polishing (CMP) method to smooth surface, and then use dry etching process to etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate; wet etch the dummy gate to form a groove at the gate electrode; use chemical vapor deposition (CVD) The method is to deposit a layer of SiON on the surface of the substrate at 600-800°C with a thickness of 1.5-5nm; use physical vapor deposition (PVD) to deposit W-TiN composite gate, and use chemical mechanical polishing (CMP) method Remove the metal on the surface, and use the W-TiN composite gate as the stop layer of chemical mechanical polishing (CMP), so as to form NMOS device and PMOS device gate;

第十三步、利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积SiO₂层，光刻引线窗口，在整个衬底上溅射一层金属，合金，自对准形成金属硅化物，清洗表面多余的金属，淀积金属，光刻引线，形成漏极、源极和栅极金属引线，构成导电沟道为22～45nm的SOI BJT、双应变平面BiCMOS集成器件。 The thirteenth step, using the chemical vapor deposition (CVD) method, at 600-800 ° C, deposit a SiO ₂ layer on the surface of the substrate, lithography the lead window, and sputter a layer of metal and alloy on the entire substrate. Form metal silicide by self-alignment, clean excess metal on the surface, deposit metal, photolithography leads, form drain, source and gate metal leads, and form SOI BJT and double-strained planar BiCMOS with a conductive channel of 22-45nm Integrated devices.

进一步、该制备方法中SOI BJT、双应变平面BiCMOS集成器件制造过程中所涉及的最高温度根据第七步、第八步、第九步、第十步、第十一步、第十二步和第十三步中的化学汽相淀积（CVD）工艺温度决定，最高温度小于等于800℃。 Further, the highest temperature involved in the manufacturing process of SOI BJT and double strain plane BiCMOS integrated devices in this preparation method is according to the seventh step, the eighth step, the ninth step, the tenth step, the eleventh step, the twelfth step and The chemical vapor deposition (CVD) process temperature in the thirteenth step is determined, and the maximum temperature is less than or equal to 800°C.

本发明的另一目的在于提供一种SOI BJT、双应变平面BiCMOS集成电路的制备方法，该制备方法包括如下步骤： Another object of the present invention is to provide a kind of preparation method of SOI BJT, double strain plane BiCMOS integrated circuit, and this preparation method comprises the steps:

步骤1，外延生长的实现方法为： Step 1, the implementation method of epitaxial growth is:

（1a）选取SOI衬底片，该衬底下层支撑材料为Si，中间层为SiO₂，厚度为150nm，上层材料为掺杂浓度为1×10¹⁶cm^-3的N型Si，厚度为100nm； (1a) Select an SOI substrate, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 150nm, and the upper layer is N-type Si with a doping concentration of 1×10 ¹⁶ cm ^-3 with a thickness of 100nm;

（1b）在衬底表面热氧化一层厚度为300nm的SiO₂层； (1b) Thermally oxidize a _SiO2 layer with a thickness of 300nm on the substrate surface;

步骤2，隔离区制备的实现方法为： Step 2, the implementation method of isolation area preparation is:

（2a）在SOI衬底上外延生长一层掺杂浓度为1×10¹⁶cm^-3的Si层，厚度为200nm，作为集电区； (2a) Epitaxially grow a Si layer with a doping concentration of 1×10 ¹⁶ cm ^-3 on the SOI substrate, with a thickness of 200 nm, as the collector region;

（2b）在衬底表面热氧化一层厚度为300nm的SiO₂层； (2b) Thermally oxidize a _SiO2 layer with a thickness of 300nm on the substrate surface;

（2c）光刻隔离区域，利用干法刻蚀工艺，在深槽隔离区域刻蚀出深度为3μm的深槽； (2c) In the photolithographic isolation area, a deep trench with a depth of 3 μm is etched in the deep trench isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在600℃，在深槽内填充SiO₂； (2d) Filling the deep groove with SiO ₂ at 600°C by chemical vapor deposition (CVD);

（2e）用化学机械抛光（CMP）方法，去除表面多余的氧化层，形成深槽隔离； (2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep groove isolation;

步骤3，双极器件制备的实现方法为： Step 3, the implementation method of bipolar device preparation is:

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁹cm^-3的重掺杂集电极； (3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 800°C for 90 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁸cm^-3的基区； (3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 800°C for 90 minutes to form a doping concentration of 1×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800℃，退火90min激活杂质，成掺杂浓度为5×10¹⁹cm^-3的重掺杂发射区，构成双极晶体管； (3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 800°C for 90 minutes to activate the impurities, resulting in a doping concentration of 5×10 ¹⁹ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在600℃，淀积一SiO₂层； (3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 600°C;

步骤4，NMOS器件外延材料制备的实现方法为： Step 4, the realization method of NMOS device epitaxial material preparation is:

（4a）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区刻蚀出深度为1.92μm的深槽； (4a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.92 μm in the active area of the NMOS device;

（4b）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为200nm的P型Si缓冲层，掺杂浓度为5×10¹⁵cm^-3； (4b) Using chemical vapor deposition (CVD), at 750°C, selectively grow a P-type Si buffer layer with a thickness of 200nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁵ cm ^-3 ;

（4c）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源 区选择性的生长厚度为1.5μm的P型SiGe渐变层，底部Ge组分是0%，顶部Ge组分是25%，掺杂浓度为5×10¹⁵cm^-3； (4c) Using chemical vapor deposition (CVD), at 750 ° C, a P-type SiGe graded layer with a thickness of 1.5 μm is selectively grown in the active region of the NMOS device, the bottom Ge composition is 0%, and the top Ge The composition is 25%, and the doping concentration is 5×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为200nm的P型SiGe层，Ge组分为25％，掺杂浓度为5×10¹⁶cm^-3； (4d) Using chemical vapor deposition (CVD), at 750°C, a P-type SiGe layer with a thickness of 200nm was selectively grown in the active region of the NMOS device, the Ge composition was 25%, and the doping concentration was 5 ×10 ¹⁶ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为20nm的P型应变Si层，掺杂浓度为5×10¹⁶cm^-3作为NMOS器件的沟道； (4e) Using chemical vapor deposition (CVD), at 750°C, selectively grow a P-type strained Si layer with a thickness of 20nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 As a channel of an NMOS device;

步骤5，PMOS器件有源区制备的实现方法为： In step 5, the method for preparing the active region of the PMOS device is as follows:

（5a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层SiO₂； (5a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用干法刻蚀工艺，在PMOS器件有源区刻蚀出深度为2.82μm的深槽； (5b) Photoetching the active area of the PMOS device, using a dry etching process to etch a deep groove with a depth of 2.82 μm in the active area of the PMOS device;

（5c）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区选择性的生长一层厚度为2.8μm的N型弛豫Si层，掺杂浓度为5×10¹⁷cm^-3； (5c) Using chemical vapor deposition (CVD), at 600°C, a layer of N-type relaxed Si layer with a thickness of 2.8 μm was selectively grown in the active region of the PMOS device with a doping concentration of 5×10 ¹⁷ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区选择性的生长一层厚度为15nm的N型应变SiGe层，Ge组分为15%，掺杂浓度为5×10¹⁷cm^-3； (5d) Using the chemical vapor deposition (CVD) method, at 600 ° C, a layer of N-type strained SiGe layer with a thickness of 15 nm is selectively grown in the active region of the PMOS device, the Ge composition is 15%, and the doped The concentration is 5×10 ¹⁷ cm ^-3 ;

（5e）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区选择性的生长一层厚度5nm的本征弛豫Si帽层，形成PMOS器件有源区； (5e) using a chemical vapor deposition (CVD) method at 600°C to selectively grow an intrinsically relaxed Si cap layer with a thickness of 5 nm in the active region of the PMOS device to form the active region of the PMOS device;

（5f）利用湿法腐蚀，刻蚀掉表面的层SiO₂； (5f) using wet etching to etch away the SiO ₂ layer on the surface;

步骤6，MOS虚栅制备的实现方法为： Step 6, the implementation method of MOS dummy gate preparation is:

（6a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积厚度为3.5nm的SiO₂层，作为NMOS器件和PMOS器件的栅介质层； (6a) Deposit a _SiO2 layer with a thickness of 3.5nm on the substrate surface at 600°C by chemical vapor deposition (CVD) as the gate dielectric layer of NMOS devices and PMOS devices;

（6b）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层厚度为300nm的Poly-Si，刻蚀Poly-Si、SiO₂层，形成NMOS器件虚栅和PMOS器件虚栅； (6b) Deposit a layer of Poly-Si with a thickness of 300nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD), etch the Poly-Si and _SiO2 layers to form the dummy gate and PMOS device virtual gate;

（6c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）； (6c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and form an N-type lightly doped source-drain structure (N-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

（6d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）； (6d) Lithograph the active region of the PMOS device, perform P-type ion implantation on the PMOS device, and form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

步骤7，NMOS器件和PMOS器件源漏区制备的实现方法为： Step 7, the implementation method of preparing the source and drain regions of the NMOS device and the PMOS device is as follows:

（7a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面上淀积一层厚度为5nm的SiO₂； (7a) Deposit a layer of SiO ₂ with a thickness of 5 nm on the surface of the substrate at 600° C. by chemical vapor deposition (CVD);

（7b）利用干法刻蚀，刻蚀衬底表面上的SiO₂，保留Ploy-Si侧壁部分，形成NMOS器件栅电极侧墙和PMOS器件栅电极侧墙； (7b) Etching the SiO ₂ on the surface of the substrate by dry etching, retaining the sidewall part of the Poly-Si, and forming the gate electrode sidewall of the NMOS device and the gate electrode sidewall of the PMOS device;

（7c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，自对准生成杂质浓度为5×10¹⁹cm^-3的NMOS器件源区和漏区； (7c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and self-align to generate the source and drain regions of the NMOS device with an impurity concentration of 5×10 ¹⁹ cm ^-3 ;

（7d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，自对准生成杂质浓度为5×10¹⁹cm^-3的PMOS器件源区和漏区； (7d) Lithograph the active region of the PMOS device, perform P-type ion implantation on the PMOS device, and self-align to generate the source and drain regions of the PMOS device with an impurity concentration of 5×10 ¹⁹ cm ^-3 ;

步骤8，NMOS器件和PMOS器件栅制备的实现方法为： Step 8, the implementation method of NMOS device and PMOS device gate preparation is:

（8a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层厚度为500nm的SiO₂层； (8a) Deposit a _SiO2 layer with a thickness of 500nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（8b）利用化学机械抛光（CMP）方法平整表面，再用干法刻蚀工艺刻蚀表面SiO₂至虚栅上表面，露出虚栅； (8b) Use chemical mechanical polishing (CMP) to flatten the surface, and then use a dry etching process to etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate;

（8c）湿法刻蚀虚栅，在栅电极处形成一个凹槽； (8c) Wet etching the dummy gate to form a groove at the gate electrode;

（8d）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层SiON，厚度为5nm； (8d) Deposit a layer of SiON on the surface of the substrate at 600° C. with a thickness of 5 nm by chemical vapor deposition (CVD);

（8e）利用物理气相沉积（PVD）的方法，淀积W-TiN复合栅； (8e) Depositing a W-TiN composite gate by physical vapor deposition (PVD);

（8f）利用化学机械抛光（CMP）方法去掉表面的金属，以W-TiN复合栅作为化学机械抛光（CMP）的终止层，从而形成NMOS器件栅极和PMOS器件栅极； (8f) Use chemical mechanical polishing (CMP) to remove the metal on the surface, and use the W-TiN composite gate as the stop layer of chemical mechanical polishing (CMP), thereby forming the NMOS device gate and the PMOS device gate;

步骤9，构成BiCMOS集成电路的实现方法为： Step 9, the implementation method of forming a BiCMOS integrated circuit is:

（9a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积SiO₂层； (9a) Deposit a _SiO2 layer on the substrate surface at 600°C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属，合金，自对准形成金属硅化物； (9b) Lithographic lead window, sputtering a layer of metal, alloy, and self-alignment to form metal silicide on the entire substrate;

（9c）淀积金属，光刻引线，形成NMOS器件漏极、源极和栅极，PMOS器件漏极、源极和栅极，双极晶体管发射极、基极、集电极金属引线，构成导电沟道为45nm的SOI BJT、双应变平面BiCMOS集成器件及电路。 (9c) Deposit metal, lithography leads, form NMOS device drain, source and gate, PMOS device drain, source and gate, bipolar transistor emitter, base, collector metal leads to form conductive SOI BJT with a channel of 45nm, double strained plane BiCMOS integrated devices and circuits.

本发明具有如下优点：The present invention has the following advantages:

1．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，PMOS器件应用了空穴迁移率比体Si材料高的压应变SiGe材料作为导电沟道，有效地提升PMOS器件的电学性能；而NMOS器件应用了电子迁移率比体Si材料高的张应变Si材料作为导电沟道，有效地提升NMOS器件的电学性能，因此本发 明制备的BiCMOS集成器件及其电路的电学性能较体Si材料制备的BiCMOS集成器件及其电路性能优异； 1. In the SOI BJT prepared by the present invention, in the double-strain plane BiCMOS integrated device, the PMOS device uses the pressure-strained SiGe material with higher hole mobility than the bulk Si material as the conductive channel, which effectively improves the electrical performance of the PMOS device; and the NMOS device The tensile strain Si material with higher electron mobility than the bulk Si material is used as the conductive channel, which effectively improves the electrical performance of the NMOS device. Therefore, the electrical performance of the BiCMOS integrated device and its circuit prepared by the present invention is better than that prepared by the bulk Si material. BiCMOS integrated device and its circuit have excellent performance;

2．本发明制备的SOI BJT、双应变平面BiCMOS集成器件，采用选择性外延技术，分别在NMOS器件和PMOS器件有源区选择性生长张应变Si和压应变SiGe材料，使NMOS器件和PMOS器件频率性能和电流驱动能力等电学性能能够获得同时提升，从而BiCMOS器件与集成电路性能获得了增强； 2. The SOI BJT prepared by the present invention and the dual-strain plane BiCMOS integrated device adopt selective epitaxy technology to selectively grow tensile strain Si and compressive strain SiGe materials in the active regions of NMOS devices and PMOS devices respectively, so that the frequency performance of NMOS devices and PMOS devices can be improved. Electrical properties such as electrical and current driving capabilities can be simultaneously improved, thereby enhancing the performance of BiCMOS devices and integrated circuits;

3．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，为了有效抑制短沟道效应，引入轻掺杂源漏（LDD）工艺，提高了器件性能； 3. In the SOI BJT and dual strain plane BiCMOS integrated devices prepared by the present invention, in order to effectively suppress the short channel effect, a lightly doped source-drain (LDD) process is introduced to improve device performance;

4．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，PMOS器件为量子阱器件，即应变SiGe层处于Si帽层和体Si层之间，与表面沟道器件相比，降低了沟道载流子输运过程中的界面散射，抑制了迁移率的降低；同时Si帽层与应变SiGe层之间的空穴势垒，抑制了热载流子向栅介质中注入，提高了BiCMOS集成器件和电路的可靠性； 4. In the SOI BJT prepared by the present invention, in the double-strained plane BiCMOS integrated device, the PMOS device is a quantum well device, that is, the strained SiGe layer is between the Si cap layer and the bulk Si layer, and compared with the surface channel device, the channel load is reduced. The interface scattering during carrier transport suppresses the reduction of mobility; at the same time, the hole barrier between the Si cap layer and the strained SiGe layer suppresses the injection of hot carriers into the gate dielectric, improving the performance of BiCMOS integrated devices. and circuit reliability;

5．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，采用高介电常数的SiON代替传统的纯SiO₂做栅介质，增强了MOS器件的栅控能力，提高了器件的可靠性； 5. In the SOI BJT and double-strained plane BiCMOS integrated devices prepared by the present invention, SiON with high dielectric constant is used instead of traditional pure _SiO2 as the gate dielectric, which enhances the gate control capability of MOS devices and improves the reliability of the devices;

6．本发明制备的SOI BJT、双应变平面BiCMOS集成器件过程中，采用了金属栅镶嵌工艺（damascene process）制备栅电极，该栅电极为金属W-TiN复合结构，由于下层的TiN与应变Si和应变SiGe材料功函数差较小，改善了器件的电学特性，上层的W则可以降低栅电极的电阻，实现了栅电极的优化； 6. In the process of the SOI BJT and double-strained planar BiCMOS integrated device prepared by the present invention, a metal gate damascene process (damascene process) is used to prepare the gate electrode. The gate electrode is a metal W-TiN composite structure. The difference in work function of SiGe material is small, which improves the electrical characteristics of the device, and the W on the upper layer can reduce the resistance of the gate electrode, realizing the optimization of the gate electrode;

7．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，双极器件采用SOI衬底的集电区厚度较传统器件薄，因此，该器件存在集电区横向扩展效应，并能够在集电区形成二维电场，从而提高了该器件的反向击穿电压和Early电压，在相同的击穿特性下，具有比传统器件更优异的特征频率。 7. In the SOI BJT and double strain plane BiCMOS integrated devices prepared by the present invention, the thickness of the collecting area of the SOI substrate used in the bipolar device is thinner than that of the traditional device. Therefore, the device has the lateral expansion effect of the collecting area, and can A two-dimensional electric field is formed, thereby improving the reverse breakdown voltage and Early voltage of the device, and having the same breakdown characteristics, it has a more excellent characteristic frequency than traditional devices.

附图说明 Description of drawings

图1是本发明提供的SOI BJT、双应变平面BiCMOS集成器件制备方法的实现流程图。 Fig. 1 is the realization flow chart of SOI BJT, double strain plane BiCMOS integrated device preparation method provided by the present invention.

具体实施方式 detailed description

为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。 In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

本发明实施例提供了一种SOI BJT、双应变平面BiCMOS集成器件，采用SOI普通Si双极晶体管，应变Si平面沟道NMOS器件和应变SiGe平面沟道PMOS器件。 The embodiment of the present invention provides an SOI BJT and double strained planar BiCMOS integrated device, which adopts SOI ordinary Si bipolar transistor, strained Si planar channel NMOS device and strained SiGe planar channel PMOS device.

作为本发明实施例的一优化方案，NMOS器件导电沟道为应变Si材料，沿沟道方向为张应变。 As an optimization scheme of the embodiment of the present invention, the conduction channel of the NMOS device is made of strained Si material, and the tensile strain is applied along the channel direction.

作为本发明实施例的一优化方案，PMOS器件导电沟道为应变SiGe材料，沿沟道方向为压应变。 As an optimization scheme of the embodiment of the present invention, the conduction channel of the PMOS device is made of strained SiGe material, and the direction of the channel is compressively strained.

作为本发明实施例的一优化方案，在同一个SOI衬底上双极器件采用体Si材料制备。  As an optimized solution of the embodiment of the present invention, the bipolar device is fabricated using bulk Si material on the same SOI substrate. the

作为本发明实施例的一优化方案，PMOS器件采用量子阱结构。 As an optimization scheme of the embodiment of the present invention, the PMOS device adopts a quantum well structure.

以下参照附图1，对本发明SOI BJT、双应变平面BiCMOS集成器件及电路的制备工艺流程作进一步详细描述。 Referring to the accompanying drawing 1, the preparation process flow of the SOI BJT, double strain plane BiCMOS integrated device and circuit of the present invention will be further described in detail.

实施例1：制备导电沟道为45nm的SOI BJT、双应变平面BiCMOS集成器件及电路，具体步骤如下： Embodiment 1: the SOI BJT of 45nm, double-strained plane BiCMOS integrated device and circuit are prepared with a conductive channel, and the specific steps are as follows:

步骤1，外延生长。  Step 1, epitaxial growth. the

（1a）选取SOI衬底片，该衬底下层支撑材料为Si，中间层为SiO₂，厚度为150nm，上层材料为掺杂浓度为1×10¹⁶cm^-3的N型Si，厚度为100nm； (1a) Select an SOI substrate, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 150nm, and the upper layer is N-type Si with a doping concentration of 1×10 ¹⁶ cm ^-3 with a thickness of 100nm;

（1b）在衬底表面热氧化一层厚度为300nm的SiO₂层。 (1b) Thermally oxidize a _SiO2 layer with a thickness of 300 nm on the substrate surface.

步骤2，隔离区制备。 Step 2, isolation area preparation.

（2a）在SOI衬底上外延生长一层掺杂浓度为1×10¹⁶cm^-3的Si层，厚度为200nm，作为集电区； (2a) Epitaxially grow a Si layer with a doping concentration of 1×10 ¹⁶ cm ^-3 on the SOI substrate, with a thickness of 200 nm, as the collector region;

（2b）在衬底表面热氧化一层厚度为300nm的SiO₂层； (2b) Thermally oxidize a _SiO2 layer with a thickness of 300nm on the substrate surface;

（2c）光刻隔离区域，利用干法刻蚀工艺，在深槽隔离区域刻蚀出深度为3μm的深槽； (2c) In the photolithographic isolation area, a deep trench with a depth of 3 μm is etched in the deep trench isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在600℃，在深槽内填充SiO₂； (2d) Filling the deep groove with SiO ₂ at 600°C by chemical vapor deposition (CVD);

（2e）用化学机械抛光（CMP）方法，去除表面多余的氧化层，形成深槽隔离。 (2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

步骤3，双极器件制备。 Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁹cm^-3的重掺杂集电极； (3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 800°C for 90 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁸cm^-3的基区； (3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 800°C for 90 minutes to form a doping concentration of 1×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800℃，退火90min激活杂质，成掺杂浓度为5×10¹⁹cm^-3的重掺杂发射区，构成双极晶体管； (3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 800°C for 90 minutes to activate the impurities, resulting in a doping concentration of 5×10 ¹⁹ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在600℃，淀积一SiO₂层。 (3d) Deposit a SiO ₂ layer on the substrate surface by chemical vapor deposition (CVD) at 600°C.

步骤4，NMOS器件外延材料制备。 Step 4, preparation of epitaxial materials for NMOS devices.

（4a）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区刻蚀出深度为1.92μm的深槽； (4a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.92 μm in the active area of the NMOS device;

（4b）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为200nm的P型Si缓冲层，掺杂浓度为5×1015cm^-3； (4b) Using chemical vapor deposition (CVD), at 750°C, selectively grow a P-type Si buffer layer with a thickness of 200nm in the active region of the NMOS device, with a doping concentration of 5×1015cm ^-3 ;

（4c）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为1.5μm的P型SiGe渐变层，底部Ge组分是0%，顶部Ge组分是25%，掺杂浓度为5×10¹⁵cm^-3； (4c) Using chemical vapor deposition (CVD), at 750 ° C, a P-type SiGe graded layer with a thickness of 1.5 μm is selectively grown in the active region of the NMOS device, the bottom Ge composition is 0%, and the top Ge The composition is 25%, and the doping concentration is 5×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为200nm的P型SiGe层，Ge组分为25%，掺杂浓度为5×10¹⁶cm^-3； (4d) Using the chemical vapor deposition (CVD) method, at 750°C, a P-type SiGe layer with a thickness of 200nm is selectively grown in the active region of the NMOS device, the Ge composition is 25%, and the doping concentration is 5% ×10 ¹⁶ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性的生长厚度为20nm的P型应变Si层，掺杂浓度为5×10¹⁶cm^-3作为NMOS器件的沟道。 (4e) Using chemical vapor deposition (CVD), at 750°C, selectively grow a P-type strained Si layer with a thickness of 20nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 as the channel of an NMOS device.

步骤5，PMOS器件有源区制备。 Step 5, preparing the active region of the PMOS device.

（5a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层SiO₂； (5a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用干法刻蚀工艺，在PMOS器件有源区刻蚀出深度为2.82μm的深槽； (5b) Photoetching the active area of the PMOS device, using a dry etching process to etch a deep groove with a depth of 2.82 μm in the active area of the PMOS device;

（5c）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源 区选择性的生长一层厚度为2.8μm的N型弛豫Si层，掺杂浓度为5×10¹⁷cm^-3； (5c) Using chemical vapor deposition (CVD), at 600°C, a layer of N-type relaxed Si layer with a thickness of 2.8 μm was selectively grown in the active region of the PMOS device with a doping concentration of 5×10 ¹⁷ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区选择性的生长一层厚度为15nm的N型应变SiGe层，Ge组分为15%，掺杂浓度为5×10¹⁷cm^-3； (5d) Using the chemical vapor deposition (CVD) method, at 600 ° C, a layer of N-type strained SiGe layer with a thickness of 15 nm is selectively grown in the active region of the PMOS device, the Ge composition is 15%, and the doped The concentration is 5×10 ¹⁷ cm ^-3 ;

（5e）利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区选择性的生长一层厚度5nm的本征弛豫Si帽层，形成PMOS器件有源区； (5e) using a chemical vapor deposition (CVD) method at 600°C to selectively grow an intrinsically relaxed Si cap layer with a thickness of 5 nm in the active region of the PMOS device to form the active region of the PMOS device;

（5f）利用湿法腐蚀，刻蚀掉表面的层SiO₂。 (5f) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，MOS虚栅制备。 Step 6, MOS dummy gate preparation.

（6a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积厚度为3.5nm的SiO₂层，作为NMOS器件和PMOS器件的栅介质层； (6a) Deposit a _SiO2 layer with a thickness of 3.5nm on the substrate surface at 600°C by chemical vapor deposition (CVD) as the gate dielectric layer of NMOS devices and PMOS devices;

（6b）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层厚度为300nm的Poly-Si，刻蚀Poly-Si、SiO₂层，形成NMOS器件虚栅和PMOS器件虚栅； (6b) Deposit a layer of Poly-Si with a thickness of 300nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD), etch the Poly-Si and _SiO2 layers to form the dummy gate and PMOS device virtual gate;

（6c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）； (6c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and form an N-type lightly doped source-drain structure (N-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

（6d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）。 (6d) Lithograph the active region of the PMOS device, and perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 .

步骤7，NMOS器件和PMOS器件源漏区制备。 Step 7, preparing the source and drain regions of the NMOS device and the PMOS device.

（7a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面上淀积一层厚度为5nm的SiO₂； (7a) Deposit a layer of SiO ₂ with a thickness of 5 nm on the surface of the substrate at 600° C. by chemical vapor deposition (CVD);

（7b）利用干法刻蚀，刻蚀衬底表面上的SiO₂，保留Ploy-Si侧壁部分， 形成NMOS器件栅电极侧墙和PMOS器件栅电极侧墙； (7b) Etching the SiO ₂ on the surface of the substrate by dry etching, retaining the sidewall part of the Poly-Si, and forming the gate electrode sidewall of the NMOS device and the gate electrode sidewall of the PMOS device;

（7c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，自对准生成杂质浓度为5×10¹⁹cm^-3的NMOS器件源区和漏区； (7c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and self-align to generate the source and drain regions of the NMOS device with an impurity concentration of 5×10 ¹⁹ cm ^-3 ;

（7d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，自对准生成杂质浓度为5×10¹⁹cm^-3的PMOS器件源区和漏区。 (7d) Lithograph the active region of the PMOS device, perform P-type ion implantation on the PMOS device, and self-align to generate the source and drain regions of the PMOS device with an impurity concentration of 5×10 ¹⁹ cm ^-3 .

步骤8，NMOS器件和PMOS器件栅制备。 Step 8, gates of NMOS devices and PMOS devices are prepared.

（8a）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层厚度为500nm的SiO₂层； (8a) Deposit a _SiO2 layer with a thickness of 500nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（8b）利用化学机械抛光（CMP）方法平整表面，再用干法刻蚀工艺刻蚀表面SiO₂至虚栅上表面，露出虚栅； (8b) Use chemical mechanical polishing (CMP) to flatten the surface, and then use a dry etching process to etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate;

（8c）湿法刻蚀虚栅，在栅电极处形成一个凹槽； (8c) Wet etching the dummy gate to form a groove at the gate electrode;

（8d）利用化学汽相淀积（CVD）的方法，在600℃，在衬底表面淀积一层SiON，厚度为5nm； (8d) Deposit a layer of SiON on the surface of the substrate at 600° C. with a thickness of 5 nm by chemical vapor deposition (CVD);

（8e）利用物理气相沉积（PVD）的方法，淀积W-TiN复合栅； (8e) Depositing a W-TiN composite gate by physical vapor deposition (PVD);

（8f）利用化学机械抛光（CMP）方法去掉表面的金属，以W-TiN复合栅作为化学机械抛光（CMP）的终止层，从而形成NMOS器件栅极和PMOS器件栅极。 (8f) The metal on the surface is removed by chemical mechanical polishing (CMP), and the W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP), thereby forming the NMOS device gate and the PMOS device gate.

步骤9，构成BiCMOS集成电路。  Step 9, forming a BiCMOS integrated circuit. the

（9a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积SiO₂层； (9a) Deposit a _SiO2 layer on the substrate surface at 600°C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属，合金，自对准形成金 属硅化物； (9b) Lithographic lead window, sputtering a layer of metal, alloy, and self-alignment to form metal silicide on the entire substrate;

（9c）淀积金属，光刻引线，形成NMOS器件漏极、源极和栅极，PMOS器件漏极、源极和栅极，双极晶体管发射极、基极、集电极金属引线，构成导电沟道为45nm的SOI BJT、双应变平面BiCMOS集成器件及电路。 (9c) Deposit metal, lithography leads, form NMOS device drain, source and gate, PMOS device drain, source and gate, bipolar transistor emitter, base, collector metal leads to form conductive SOI BJT with a channel of 45nm, double strained plane BiCMOS integrated devices and circuits.

实施例2：制备导电沟道为30nm的SOI BJT、双应变平面BiCMOS集成器件及电路，具体步骤如下： Embodiment 2: the SOI BJT of 30nm, double-strained plane BiCMOS integrated device and circuit are prepared with a conductive channel, and the specific steps are as follows:

步骤1，外延生长。  Step 1, epitaxial growth. the

（1a）选取SOI衬底片，该衬底下层支撑材料为Si，中间层为SiO₂，厚度为300nm，上层材料为掺杂浓度为5×10¹⁶cm^-3的N型Si，厚度为120nm； (1a) Select the SOI substrate sheet, the support material of the lower layer of the substrate is Si, the middle layer is SiO ₂ , the thickness is 300nm, and the upper layer material is N-type Si with a doping concentration of 5×10 ¹⁶ cm ^-3 , the thickness is 120nm;

（1b）在衬底表面热氧化一层厚度为400nm的SiO₂层。 (1b) Thermally oxidize a _SiO2 layer with a thickness of 400 nm on the substrate surface.

步骤2，隔离区制备。 Step 2, isolation area preparation.

（2a）在SOI衬底上外延生长一层掺杂浓度为5×10¹⁶cm^-3的Si层，厚度为350nm，作为集电区； (2a) Epitaxially grow a Si layer with a doping concentration of 5×10 ¹⁶ cm ^-3 on the SOI substrate, with a thickness of 350 nm, as the collector region;

（2b）在衬底表面热氧化一层厚度为400nm的SiO₂层； (2b) Thermally oxidize a SiO layer with a thickness of 400 nm on the substrate surface _;

（2c）光刻隔离区域，利用干法刻蚀工艺，在深槽隔离区域刻蚀出深度为4μm的深槽； (2c) In the photolithographic isolation area, a deep trench with a depth of 4 μm is etched in the deep trench isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在700℃，在深槽内填充SiO₂； (2d) Filling the deep groove with SiO ₂ at 700°C by chemical vapor deposition (CVD);

（2e）用化学机械抛光（CMP）方法，去除表面多余的氧化层，形成深槽隔离。 (2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

步骤3，双极器件制备。 Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在900℃，退火90min激活杂质，形成掺杂浓度为5×10¹⁹cm^-3的重掺杂集电极； (3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 900°C for 90 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 5×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在900℃，退火45min激活杂质，形成掺杂浓度为3×10¹⁸cm^-3的基区； (3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 900°C for 45 minutes to form a doping concentration of 3×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在900℃，退火45min激活杂质，成掺杂浓度为1×10²⁰cm^-3的重掺杂发射区，构成双极晶体管； (3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 900°C for 45min to activate the impurities, resulting in a doping concentration of 1×10 ²⁰ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在700℃，淀积一SiO₂层。 (3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 700°C.

步骤4，NMOS器件外延材料制备。 Step 4, preparation of epitaxial materials for NMOS devices.

（4a）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区刻蚀出深度为1.92μm的深槽； (4a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.92 μm in the active area of the NMOS device;

（4b）利用化学汽相淀积（CVD）的方法，在700℃，在NMOS器件有源区选择性生长厚度为300nm的P型Si缓冲层，掺杂浓度为1×10¹⁶cm^-3； (4b) Selectively grow a P-type Si buffer layer with a thickness of 300nm in the active region of the NMOS device at 700°C by chemical vapor deposition (CVD), with a doping concentration of 1×10 ¹⁶ cm ^-3 ;

（4c）利用化学汽相淀积（CVD）的方法，在700℃，在NMOS器件有源区选择性生长厚度为1.8μm的P型SiGe渐变层，底部Ge组分是0%，顶部Ge组分是20%，掺杂浓度为1×10¹⁶cm^-3； (4c) Using the chemical vapor deposition (CVD) method, at 700 ° C, a P-type SiGe graded layer with a thickness of 1.8 μm is selectively grown in the active region of the NMOS device. The Ge composition at the bottom is 0%, and the Ge composition at the top is 0%. The concentration is 20%, and the doping concentration is 1×10 ¹⁶ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在700℃，在NMOS器件有源区选择性生长厚度为300nm的P型SiGe层，Ge组分为20％，掺杂浓度为1×10¹⁷cm^-3； (4d) Using chemical vapor deposition (CVD), at 700 ° C, a P-type SiGe layer with a thickness of 300 nm is selectively grown in the active region of the NMOS device, the Ge composition is 20%, and the doping concentration is 1× 10 ¹⁷ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在700℃，在NMOS器件有源区选择性生长厚度为18nm的P型应变Si层，掺杂浓度为1×10¹⁷cm^-3作为NMOS 器件的沟道。 (4e) Using the chemical vapor deposition (CVD) method, at 700 ° C, a P-type strained Si layer with a thickness of 18 nm was selectively grown in the active region of the NMOS device, and the doping concentration was 1×10 ¹⁷ cm ^-3 as The channel of an NMOS device.

步骤5，PMOS器件有源区制备。 Step 5, preparing the active region of the PMOS device.

（5a）利用化学汽相淀积（CVD）的方法，在700℃，在衬底表面淀积一层SiO₂； (5a) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用干法刻蚀工艺，在PMOS器件有源区刻蚀出深度为2.42μm的深槽； (5b) Photoetching the active area of the PMOS device, using a dry etching process to etch a deep groove with a depth of 2.42 μm in the active area of the PMOS device;

（5c）利用化学汽相淀积（CVD）的方法，在700℃，在PMOS器件有源区选择性的生长一层厚度为2.4μm的N型弛豫Si层，掺杂浓度为1×10¹⁷cm^-3； (5c) Using chemical vapor deposition (CVD), at 700 ° C, a layer of N-type relaxed Si layer with a thickness of 2.4 μm was selectively grown in the active region of the PMOS device, and the doping concentration was 1×10 ¹⁷ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在700℃，在PMOS器件有源区选择性的生长一层厚度为14nm的N型应变SiGe层，Ge组分为20%，掺杂浓度为1×10¹⁷cm^-3； (5d) Using chemical vapor deposition (CVD), at 700 ° C, a layer of N-type strained SiGe layer with a thickness of 14 nm is selectively grown in the active region of the PMOS device, the Ge composition is 20%, doped The concentration is 1×10 ¹⁷ cm ^-3 ;

（5e）利用化学汽相淀积（CVD）的方法，在700℃，在PMOS器件有源区选择性的生长一层厚度4nm的本征弛豫Si帽层，形成PMOS器件有源区； (5e) using a chemical vapor deposition (CVD) method at 700°C to selectively grow an intrinsically relaxed Si cap layer with a thickness of 4nm in the active region of the PMOS device to form the active region of the PMOS device;

（5f）利用湿法腐蚀，刻蚀掉表面的层SiO₂。 (5f) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，MOS虚栅制备。 Step 6, MOS dummy gate preparation.

（6a）利用化学汽相淀积（CVD）的方法，在700℃，在衬底表面淀积厚度为4nm的SiO₂层，作为NMOS器件和PMOS器件的栅介质层； (6a) Deposit a _SiO2 layer with a thickness of 4nm on the substrate surface at 700°C by chemical vapor deposition (CVD) as the gate dielectric layer of NMOS devices and PMOS devices;

（6b）利用化学汽相淀积（CVD）方法，在700℃，在衬底表面淀积一层厚度为240nm的Poly-Si，刻蚀Poly-Si、SiO₂层，形成NMOS器件虚栅和PMOS器件虚栅； (6b) Deposit a layer of Poly-Si with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD), etch the Poly-Si and _SiO2 layers to form the dummy gate and PMOS device virtual gate;

（6c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，形成 掺杂浓度为3×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）； (6c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and form an N-type lightly doped source-drain structure (N-LDD) with a doping concentration of 3×10 ¹⁸ cm ^-3 ;

（6d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，形成掺杂浓度为3×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）。 (6d) Lithograph the active region of the PMOS device, and perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 3×10 ¹⁸ cm ^-3 .

步骤7，NMOS器件和PMOS器件源漏区制备。 Step 7, preparing the source and drain regions of the NMOS device and the PMOS device.

（7a）利用化学汽相淀积（CVD）的方法，在700℃，在衬底表面上淀积一层厚度为3nm的SiO₂； (7a) Deposit a layer of SiO ₂ with a thickness of 3nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（7b）利用干法刻蚀，刻蚀衬底表面上的SiO₂，保留Ploy-Si侧壁部分，形成NMOS器件栅电极侧墙和PMOS器件栅电极侧墙； (7b) Etching the SiO ₂ on the surface of the substrate by dry etching, retaining the sidewall part of the Poly-Si, and forming the gate electrode sidewall of the NMOS device and the gate electrode sidewall of the PMOS device;

（7c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，自对准生成杂质浓度为8×10¹⁹cm^-3的NMOS器件源区和漏区； (7c) Lithograph the active region of the NMOS device, perform N-type ion implantation on the NMOS device, and self-align to generate the source and drain regions of the NMOS device with an impurity concentration of 8×10 ¹⁹ cm ^-3 ;

（7d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，自对准生成杂质浓度为8×10¹⁹cm^-3的PMOS器件源区和漏区。 (7d) Lithograph the active region of the PMOS device, perform P-type ion implantation on the PMOS device, and self-align to generate the source region and drain region of the PMOS device with an impurity concentration of 8×10 ¹⁹ cm ^-3 .

步骤8，NMOS器件和PMOS器件栅制备。 Step 8, gates of NMOS devices and PMOS devices are prepared.

（8a）利用化学汽相淀积（CVD）的方法，在700℃，在衬底表面淀积一层厚度为450nm的SiO₂层； (8a) Deposit a _SiO2 layer with a thickness of 450nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（8b）利用化学机械抛光（CMP）方法平整表面，再用干法刻蚀工艺刻蚀表面SiO₂至虚栅上表面，露出虚栅； (8b) Use chemical mechanical polishing (CMP) to flatten the surface, and then use a dry etching process to etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate;

（8c）湿法刻蚀虚栅，在栅电极处形成一个凹槽； (8c) Wet etching the dummy gate to form a groove at the gate electrode;

（8d）利用化学汽相淀积（CVD）的方法，在700℃，在衬底表面淀积一层SiON，厚度为3nm； (8d) Deposit a layer of SiON on the surface of the substrate at 700°C with a thickness of 3 nm by chemical vapor deposition (CVD);

（8e）利用物理气相沉积（PVD）的方法，淀积W-TiN复合栅； (8e) Depositing a W-TiN composite gate by physical vapor deposition (PVD);

（8f）利用化学机械抛光（CMP）方法去掉表面的金属，以W-TiN复合栅作为化学机械抛光（CMP）的终止层，从而形成NMOS器件栅极和PMOS器件栅极。 (8f) The metal on the surface is removed by chemical mechanical polishing (CMP), and the W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP), thereby forming the NMOS device gate and the PMOS device gate.

步骤9，构成BiCMOS集成电路。  Step 9, forming a BiCMOS integrated circuit. the

（9a）利用化学汽相淀积（CVD）方法，在700℃，在衬底表面淀积SiO₂层； (9a) Deposit a _SiO2 layer on the substrate surface at 700°C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属，合金，自对准形成金属硅化物； (9b) Lithographic lead window, sputtering a layer of metal, alloy, and self-alignment to form metal silicide on the entire substrate;

（9c）淀积金属，光刻引线，形成NMOS器件漏极、源极和栅极，PMOS器件漏极、源极和栅极，双极晶体管发射极、基极、集电极金属引线，构成导电沟道为30nm的SOI BJT、双应变平面BiCMOS集成器件及电路。 (9c) Deposit metal, lithography leads, form NMOS device drain, source and gate, PMOS device drain, source and gate, bipolar transistor emitter, base, collector metal leads to form conductive SOI BJT with a channel of 30nm, double strained plane BiCMOS integrated devices and circuits.

实施例3：制备导电沟道为22nm的SOI BJT、双应变平面BiCMOS集成器件及电路，具体步骤如下： Embodiment 3: the SOI BJT of 22nm, double-strained plane BiCMOS integrated device and circuit are prepared with a conductive channel, and the specific steps are as follows:

步骤1，外延生长。  Step 1, epitaxial growth. the

（1a）选取SOI衬底片，该衬底下层支撑材料为Si，中间层为SiO₂，厚度为400nm，上层材料为掺杂浓度为1×10¹⁷cm^-3的N型Si，厚度为150nm； (1a) Select the SOI substrate sheet, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 400nm, and the upper layer material is N-type Si with a doping concentration of 1×10 ¹⁷ cm ^-3 with a thickness of 150nm;

（1b）在衬底表面热氧化一层厚度为500nm的SiO₂层。 (1b) Thermally oxidize a _SiO2 layer with a thickness of 500 nm on the substrate surface.

步骤2，隔离区制备。 Step 2, isolation area preparation.

（2a）在SOI衬底上外延生长一层掺杂浓度为1×10¹⁷cm^-3的Si层，厚度为400nm，作为集电区； (2a) Epitaxially grow a Si layer with a doping concentration of 1×10 ¹⁷ cm ^-3 on the SOI substrate, with a thickness of 400 nm, as the collector region;

（2b）在衬底表面热氧化一层厚度为500nm的SiO₂层； (2b) Thermally oxidize a SiO layer with a thickness of 500 nm on the substrate surface _;

（2c）光刻隔离区域，利用干法刻蚀工艺，在深槽隔离区域刻蚀出深度为5μm的深槽； (2c) In the photolithographic isolation area, a deep trench with a depth of 5 μm is etched in the deep trench isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在800℃，在深槽内填充SiO₂； (2d) Filling the deep groove with SiO ₂ at 800°C by chemical vapor deposition (CVD);

（2e）用化学机械抛光（CMP）方法，去除表面多余的氧化层，形成深槽隔离。 (2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

步骤3，双极器件制备。 Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在950℃，退火30min激活杂质，形成掺杂浓度为1×10²⁰cm^-3的重掺杂集电极； (3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 950°C for 30 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ²⁰ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在950℃，退火30min激活杂质，形成掺杂浓度为5×10¹⁸cm^-3的基区； (3b) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photoresist the base area, implant P-type impurities into the base area, and activate the impurities by annealing at 950°C for 30 minutes to form a doping concentration of 5×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在950℃，退火30min激活杂质，成掺杂浓度为5×10²⁰cm^-3的重掺杂发射区，构成双极晶体管； (3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 950°C for 30 minutes to activate the impurities, resulting in a doping concentration of 5×10 ²⁰ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在800℃，淀积一SiO₂层。 (3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 800°C.

步骤4，NMOS器件外延材料制备。 Step 4, preparation of epitaxial materials for NMOS devices.

（4a）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区刻蚀出深度为1.92μm的深槽； (4a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.92 μm in the active area of the NMOS device;

（4a）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性生长厚度为200nm的P型Si缓冲层，掺杂浓度为5×10¹⁵cm^-3； (4a) Selectively grow a P-type Si buffer layer with a thickness of 200nm in the active region of the NMOS device at 750°C by chemical vapor deposition (CVD), with a doping concentration of 5×10 ¹⁵ cm ^-3 ;

（4b）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源 区选择性生长厚度为1.5μm的P型SiGe渐变层，底部Ge组分是0%，顶部Ge组分是25%，掺杂浓度为5×10¹⁵cm^-3； (4b) Using chemical vapor deposition (CVD), at 750 ° C, a P-type SiGe graded layer with a thickness of 1.5 μm is selectively grown in the active region of the NMOS device. The Ge composition at the bottom is 0%, and the Ge composition at the top is 0%. The concentration is 25%, and the doping concentration is 5×10 ¹⁵ cm ^-3 ;

（4c）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性生长厚度为200nm的P型SiGe层，Ge组分为25％，掺杂浓度为5×10¹⁶cm^-3； (4c) Using the chemical vapor deposition (CVD) method, at 750 ° C, a P-type SiGe layer with a thickness of 200 nm is selectively grown in the active region of the NMOS device, the Ge composition is 25%, and the doping concentration is 5× 10 ¹⁶ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在750℃，在NMOS器件有源区选择性生长厚度为15nm的P型应变Si层，掺杂浓度为5×10¹⁶cm^-3作为NMOS器件的沟道。 (4d) Using the chemical vapor deposition (CVD) method, at 750 ° C, a P-type strained Si layer with a thickness of 15 nm was selectively grown in the active region of the NMOS device, and the doping concentration was 5×10 ¹⁶ cm ^-3 as The channel of an NMOS device.

步骤5，PMOS器件有源区制备。 Step 5, preparing the active region of the PMOS device.

（5a）利用化学汽相淀积（CVD）的方法，在800℃，在衬底表面淀积一层SiO₂； (5a) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用干法刻蚀工艺，在PMOS器件有源区刻蚀出深度为1.92μm的深槽； (5b) Photoetching the active area of the PMOS device, using a dry etching process to etch a deep groove with a depth of 1.92 μm in the active area of the PMOS device;

（5c）利用化学汽相淀积（CVD）的方法，在750℃，在PMOS器件有源区选择性的生长一层厚度为1.9μm的N型弛豫Si层，掺杂浓度为5×10¹⁶cm^-3； (5c) Using the chemical vapor deposition (CVD) method, at 750 ° C, a layer of N-type relaxed Si layer with a thickness of 1.9 μm was selectively grown in the active region of the PMOS device, and the doping concentration was 5×10 ¹⁶ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在750℃，在PMOS器件有源区选择性的生长一层厚度为12nm的N型应变SiGe层，Ge组分为25%，掺杂浓度为5×10¹⁶cm^-3； (5d) Using the chemical vapor deposition (CVD) method, at 750 ° C, a layer of N-type strained SiGe layer with a thickness of 12 nm is selectively grown in the active region of the PMOS device, the Ge composition is 25%, and the doped The concentration is 5×10 ¹⁶ cm ^-3 ;

（5e）利用化学汽相淀积（CVD）的方法，在750℃，在PMOS器件有源区选择性的生长一层厚度3nm的本征弛豫Si帽层，形成PMOS器件有源区； (5e) using a chemical vapor deposition (CVD) method at 750°C to selectively grow an intrinsically relaxed Si cap layer with a thickness of 3nm in the active region of the PMOS device to form the active region of the PMOS device;

（5f）利用湿法腐蚀，刻蚀掉表面的层SiO₂。 (5f) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，MOS虚栅制备。 Step 6, MOS dummy gate preparation.

（6a）利用化学汽相淀积（CVD）的方法，在800℃，在衬底表面淀积厚度为3nm的SiO₂层，作为NMOS器件和PMOS器件的栅介质层； (6a) Deposit a _SiO2 layer with a thickness of 3nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD) as the gate dielectric layer of NMOS devices and PMOS devices;

（6b）利用化学汽相淀积（CVD）方法，在800℃，在衬底表面淀积一层厚度为200nm的Poly-Si，刻蚀Poly-Si、SiO₂层，形成NMOS器件虚栅和PMOS器件虚栅； (6b) Deposit a layer of Poly-Si with a thickness of 200nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD), etch the Poly-Si and _SiO2 layers to form the dummy gate and PMOS device virtual gate;

（6c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，形成掺杂浓度为5×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）； (6c) Lithograph the active region of the NMOS device, perform N-type ion implantation on the NMOS device, and form an N-type lightly doped source-drain structure (N-LDD) with a doping concentration of 5×10 ¹⁸ cm ^-3 ;

（6d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，形成掺杂浓度为5×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）。 (6d) Lithograph the active region of the PMOS device, and perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 5×10 ¹⁸ cm ^-3 .

步骤7，NMOS器件和PMOS器件源漏区制备。 Step 7, preparing the source and drain regions of the NMOS device and the PMOS device.

（7a）利用化学汽相淀积（CVD）的方法，在800℃，在衬底表面上淀积一层厚度为3nm的SiO₂； (7a) Deposit a layer of SiO ₂ with a thickness of 3 nm on the surface of the substrate at 800° C. by chemical vapor deposition (CVD);

（7b）利用干法刻蚀，刻蚀衬底表面上的SiO₂，保留Ploy-Si侧壁部分，形成NMOS器件栅电极侧墙和PMOS器件栅电极侧墙； (7b) Etching the SiO ₂ on the surface of the substrate by dry etching, retaining the sidewall part of the Poly-Si, and forming the gate electrode sidewall of the NMOS device and the gate electrode sidewall of the PMOS device;

（7c）光刻NMOS器件有源区，对NMOS器件进行N型离子注入，自对准生成杂质浓度为1×10²⁰cm^-3的NMOS器件源区和漏区； (7c) Lithograph the active area of the NMOS device, perform N-type ion implantation on the NMOS device, and self-align to generate the source and drain regions of the NMOS device with an impurity concentration of 1×10 ²⁰ cm ^-3 ;

（7d）光刻PMOS器件有源区，对PMOS器件进行P型离子注入，自对准生成杂质浓度为1×10²⁰cm^-3的PMOS器件源区和漏区。 (7d) Lithograph the active region of the PMOS device, perform P-type ion implantation on the PMOS device, and self-align to generate the source and drain regions of the PMOS device with an impurity concentration of 1×10 ²⁰ cm ^-3 .

步骤8，CMOS源漏和栅制备。 Step 8, preparation of CMOS source, drain and gate.

（8a）利用化学汽相淀积（CVD）的方法，在800℃，在衬底表面淀积一层厚度为400nm的SiO₂层； (8a) Deposit a _SiO2 layer with a thickness of 400nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

（8b）利用化学机械抛光（CMP）方法平整表面，再用干法刻蚀工艺刻蚀表面SiO₂至虚栅上表面，露出虚栅； (8b) Use chemical mechanical polishing (CMP) to flatten the surface, and then use a dry etching process to etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate;

（8c）湿法刻蚀虚栅，在栅电极处形成一个凹槽； (8c) Wet etching the dummy gate to form a groove at the gate electrode;

（8d）利用化学汽相淀积（CVD）的方法，在800℃，在衬底表面淀积一层SiON，厚度为1.5nm； (8d) Deposit a layer of SiON on the surface of the substrate at 800°C with a thickness of 1.5 nm by chemical vapor deposition (CVD);

（8e）利用物理气相沉积（PVD）的方法，淀积W-TiN复合栅； (8e) Depositing a W-TiN composite gate by physical vapor deposition (PVD);

（8f）利用化学机械抛光（CMP）方法去掉表面的金属，以W-TiN复合栅作为化学机械抛光（CMP）的终止层，从而形成NMOS器件栅极和PMOS器件栅极。 (8f) The metal on the surface is removed by chemical mechanical polishing (CMP), and the W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP), thereby forming the NMOS device gate and the PMOS device gate.

步骤9，构成BiCMOS集成电路。  Step 9, forming a BiCMOS integrated circuit. the

（9a）利用化学汽相淀积（CVD）方法，在800℃，在衬底表面淀积SiO₂层； (9a) Deposit a _SiO2 layer on the substrate surface at 800°C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属，合金，自对准形成金属硅化物； (9b) Lithographic lead window, sputtering a layer of metal, alloy, and self-alignment to form metal silicide on the entire substrate;

（9c）淀积金属，光刻引线，形成NMOS器件漏极、源极和栅极，PMOS器件漏极、源极和栅极，双极晶体管发射极、基极、集电极金属引线，构成导电沟道为22nm的SOI BJT、双应变平面BiCMOS集成器件及电路。 (9c) Deposit metal, lithography leads, form NMOS device drain, source and gate, PMOS device drain, source and gate, bipolar transistor emitter, base, collector metal leads to form conductive SOI BJT with a channel of 22nm, double strained plane BiCMOS integrated devices and circuits.

本发明实施例提供的SOI BJT、双应变平面BiCMOS集成器件及制备方法具有如下优点： The SOI BJT, double strain plane BiCMOS integrated device and preparation method provided by the embodiments of the present invention have the following advantages:

1．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，PMOS器件应用了空穴迁移率比体Si材料高的压应变SiGe材料作为导电沟道，有效地提升PMOS器件的电学性能；而NMOS器件应用了电子迁移率比体Si材料高的 张应变Si材料作为导电沟道，有效地提升NMOS器件的电学性能，因此本发明制备的BiCMOS集成器件及其电路的电学性能较体Si材料制备的BiCMOS集成器件及其电路性能优异； 1. In the SOI BJT prepared by the present invention, in the double-strain plane BiCMOS integrated device, the PMOS device uses the pressure-strained SiGe material with higher hole mobility than the bulk Si material as the conductive channel, which effectively improves the electrical performance of the PMOS device; and the NMOS device The tensile strain Si material with higher electron mobility than the bulk Si material is used as the conductive channel, which effectively improves the electrical performance of the NMOS device. Therefore, the electrical performance of the BiCMOS integrated device and its circuit prepared by the present invention is better than that of the BiCMOS prepared by the bulk Si material. Excellent performance of integrated devices and their circuits;

2．本发明制备的SOI BJT、双应变平面BiCMOS集成器件，采用选择性外延技术，分别在NMOS器件和PMOS器件有源区选择性生长张应变Si和压应变SiGe材料，使NMOS器件和PMOS器件频率性能和电流驱动能力等电学性能能够获得同时提升，从而BiCMOS器件与集成电路性能获得了增强； 2. The SOI BJT prepared by the present invention and the dual-strain plane BiCMOS integrated device adopt selective epitaxy technology to selectively grow tensile strain Si and compressive strain SiGe materials in the active regions of NMOS devices and PMOS devices respectively, so that the frequency performance of NMOS devices and PMOS devices can be improved. Electrical properties such as electrical and current driving capabilities can be simultaneously improved, thereby enhancing the performance of BiCMOS devices and integrated circuits;

3．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，为了有效抑制短沟道效应，引入轻掺杂源漏（LDD）工艺，提高了器件性能； 3. In the SOI BJT and dual strain plane BiCMOS integrated devices prepared by the present invention, in order to effectively suppress the short channel effect, a lightly doped source-drain (LDD) process is introduced to improve device performance;

4．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，PMOS器件为量子阱器件，即应变SiGe层处于Si帽层和体Si层之间，与表面沟道器件相比，降低了沟道载流子输运过程中的界面散射，抑制了迁移率的降低；同时Si帽层与应变SiGe层之间的空穴势垒，抑制了热载流子向栅介质中注入，提高了BiCMOS集成器件和电路的可靠性； 4. In the SOI BJT prepared by the present invention, in the double-strained plane BiCMOS integrated device, the PMOS device is a quantum well device, that is, the strained SiGe layer is between the Si cap layer and the bulk Si layer, and compared with the surface channel device, the channel load is reduced. The interface scattering during carrier transport suppresses the reduction of mobility; at the same time, the hole barrier between the Si cap layer and the strained SiGe layer suppresses the injection of hot carriers into the gate dielectric, improving the performance of BiCMOS integrated devices. and circuit reliability;

5．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，采用高介电常数的SiON代替传统的纯SiO₂做栅介质，增强了MOS器件的栅控能力，提高了器件的可靠性； 5. In the SOI BJT and double-strained plane BiCMOS integrated devices prepared by the present invention, SiON with high dielectric constant is used instead of traditional pure _SiO2 as the gate dielectric, which enhances the gate control capability of MOS devices and improves the reliability of the devices;

6．本发明制备的SOI BJT、双应变平面BiCMOS集成器件过程中，采用了金属栅镶嵌工艺（damascene process）制备栅电极，该栅电极为金属W-TiN复合结构，由于下层的TiN与应变Si和应变SiGe材料功函数差较小，改善了器件的电学特性，上层的W则可以降低栅电极的电阻，实现了栅电极的优化； 6. In the process of the SOI BJT and double-strained planar BiCMOS integrated device prepared by the present invention, a metal gate damascene process (damascene process) is used to prepare the gate electrode. The gate electrode is a metal W-TiN composite structure. The difference in work function of SiGe material is small, which improves the electrical characteristics of the device, and the W on the upper layer can reduce the resistance of the gate electrode, realizing the optimization of the gate electrode;

7．本发明制备的SOI BJT、双应变平面BiCMOS集成器件中，双极器件采用SOI衬底的集电区厚度较传统器件薄，因此，该器件存在集电区横向扩展效应，并能够在集电区形成二维电场，从而提高了该器件的反向击穿电压和Early 电压，在相同的击穿特性下，具有比传统器件更优异的特征频率。 7. In the SOI BJT and double strain plane BiCMOS integrated devices prepared by the present invention, the thickness of the collecting area of the SOI substrate used in the bipolar device is thinner than that of the traditional device. Therefore, the device has the lateral expansion effect of the collecting area, and can A two-dimensional electric field is formed, thereby increasing the reverse breakdown voltage and Early voltage of the device, and has a better characteristic frequency than traditional devices under the same breakdown characteristics.

以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。 The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.