CN102738165A - Mixed crystal plane strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor Transistor) integrated device and manufacturing method thereof - Google Patents

本发明公开了一种混合晶面平面应变BiCMOS集成器件及电路制备方法。其过程为：制备一片SOI衬底，上层的基体材料为（110）晶面，下层的基体材料为（100）晶面；在双极器件区域制造常规的Si双极晶体管；在NMOS器件区域，选择性生长晶面为（100）的应变Si外延层，制备应变Si沟道NMOS器件；在PMOS器件有源区的区域，选择性生长晶面为（110）的应变SiGe外延层，制备沟道的压应变SiGe沟道PMOS器件；光刻引线，构成MOS器件导电沟道为22～45nm的混合晶面平面应变BiCMOS集成器件；本发明充分了利用张应变Si材料电子迁移率高于体Si材料和压应变SiGe材料电子迁移率高于体Si材料以及迁移率各向异性的特点，基于SOI衬底，制备出了性能增强的混合晶面平面应变BiCMOS集成器件及电路。

The invention discloses a mixed crystal plane plane strain BiCMOS integrated device and a circuit preparation method. The process is as follows: prepare a piece of SOI substrate, the base material of the upper layer is (110) crystal plane, and the base material of the lower layer is (100) crystal plane; manufacture conventional Si bipolar transistors in the bipolar device area; in the NMOS device area, Selectively grow a strained Si epitaxial layer with a crystal plane of (100) to prepare a strained Si channel NMOS device; in the active region of a PMOS device, selectively grow a strained SiGe epitaxial layer with a crystal plane of (110) to prepare a channel The compressively strained SiGe channel PMOS device; the lithographic lead, which constitutes the conductive channel of the MOS device is a mixed crystal plane strained BiCMOS integrated device of 22-45nm; the present invention fully utilizes the electron mobility of the tensile strained Si material higher than that of the bulk Si material Based on the characteristics of compressively strained SiGe materials with higher electron mobility than bulk Si materials and mobility anisotropy, performance-enhanced mixed crystal plane strain BiCMOS integrated devices and circuits have been prepared based on SOI substrates.

一种混合晶面平面应变BiCMOS集成器件及制备方法A mixed plane strain BiCMOS integrated device and its preparation method

技术领域 technical field

本发明属于半导体集成电路技术领域，尤其涉及一种混合晶面应变混合晶面平面应变BiCMOS集成器件及制备方法。The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane strain mixed crystal plane strain BiCMOS integrated device and a preparation method.

背景技术 Background technique

在信息技术高度发展的当代，以集成电路为代表的微电子技术是信息技术的关键。集成电路作为人类历史上发展最快、影响最大、应用最广泛的技术，其已成为衡量一个国家科学技术水平、综合国力和国防力量的重要标志。In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength.

对微电子产业发展产生巨大影响的“摩尔定律”指出：集成电路芯片上的晶体管数目，约每18个月增加1倍，性能也提升1倍。40多年来，世界微电子产业始终按照这条定律不断地向前发展，电路规模已由最初的小规模发展到现在的超大规模；Si材料以其优异的性能，在微电子产业中一直占据着重要的地位，而以Si材料为基础的CMOS集成电路以低功耗、低噪声、高输入阻抗、高集成度、可靠性好等优点在集成电路领域中占据着主导地位。"Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the world's microelectronics industry has been developing continuously in accordance with this law, and the circuit scale has grown from the initial small scale to the current ultra-large scale; Si material has always occupied the leading position in the microelectronics industry due to its excellent performance. CMOS integrated circuits based on Si materials occupy a dominant position in the field of integrated circuits due to their low power consumption, low noise, high input impedance, high integration, and good reliability.

随着器件特征尺寸的逐步减小，尤其是进入纳米尺度以后，微电子技术的发展越来越逼近材料、技术、器件的极限，面临着巨大的挑战。当器件特征尺寸缩小到65纳米以后，MOS器件中的短沟效应、强场效应、量子效应、寄生参量的影响、工艺参数涨落等问题对器件泄漏电流、亚阈特性、开态/关态电流等性能的影响越来越突出；而且随着无线移动通信的飞速发展，对器件和集成电路的性能，如频率特性、噪声特性、封装面积、功耗和成本等提出了更高的要求，传统硅基工艺制备的器件和集成电路越来越无法满足新型、高速电子系统的需求。With the gradual reduction of device feature size, especially after entering the nanometer scale, the development of microelectronics technology is getting closer and closer to the limit of materials, technologies and devices, and is facing huge challenges. When the feature size of the device is reduced to 65 nanometers, the short channel effect, strong field effect, quantum effect, parasitic parameter influence, process parameter fluctuation and other issues in the MOS device will affect the device leakage current, sub-threshold characteristics, on/off state, etc. The impact of current and other performance is becoming more and more prominent; and with the rapid development of wireless mobile communication, higher requirements are put forward for the performance of devices and integrated circuits, such as frequency characteristics, noise characteristics, packaging area, power consumption and cost. Devices and integrated circuits prepared by traditional silicon-based processes are increasingly unable to meet the needs of new, high-speed electronic systems.

CMOS集成电路的一个重要性能指标，是NMOS和PMOS器件的驱动能力，而电子和空穴的迁移率分别是决定其驱动能力的关键因素之一；为了提高NMOS器件和PMOS器件的性能进而提高CMOS集成电路的性能，两种载流子的迁移率都应当尽可能地高。An important performance index of CMOS integrated circuits is the driving capability of NMOS and PMOS devices, and the mobility of electrons and holes is one of the key factors determining their driving capabilities; in order to improve the performance of NMOS devices and PMOS devices and then improve CMOS For integrated circuit performance, the mobility of both carriers should be as high as possible.

早在上世纪五十年代，就已经研究发现在硅材料上施加应力，会改变电子和空穴的迁移率，从而改变半导体材料上所制备的NMOS和PMOS器件的性能；但电子和空穴并不总是对同种应力做出相同的反应；同时，在相同的晶面上制备NMOS器件和PMOS器件，它们的迁移率并不能同时达到最优。As early as the 1950s, it has been found that applying stress on silicon materials will change the mobility of electrons and holes, thereby changing the performance of NMOS and PMOS devices prepared on semiconductor materials; but electrons and holes do not The same response to the same stress is not always made; at the same time, the mobility of NMOS devices and PMOS devices cannot be optimized at the same time when they are prepared on the same crystal plane.

由于Si材料载流子材料迁移率较低，所以采用Si BiCMOS技术制造的集成电路性能，尤其是频率性能，受到了极大的限制。Due to the low mobility of Si materials, the performance of integrated circuits manufactured by Si BiCMOS technology, especially the frequency performance, is greatly limited.

为此，要在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率，本专利提出一种应变技术制备CMOS，即应变混合晶面平面应变BiCMOS集成器件及电路的制备。To this end, in order to increase the carrier mobility of another type of device without reducing the carrier mobility of one type of device, this patent proposes a straining technology to prepare CMOS, that is, strained mixed crystal Fabrication of Plane Strain BiCMOS Integrated Devices and Circuits.

发明内容 Contents of the invention

本发明的目的在于提供一种混合晶面平面应变BiCMOS集成器件及制备方法，以实现在不改变现有设备和增加成本的条件下，导电沟道为22～45nm的混合晶面平面应变BiCMOS集成器件及电路。The purpose of the present invention is to provide a mixed crystal plane strain BiCMOS integrated device and its preparation method, so as to realize the mixed crystal plane strain BiCMOS integration with a conductive channel of 22-45nm without changing the existing equipment and increasing the cost devices and circuits.

本发明的目的在于提供一种混合晶面平面应变BiCMOS集成器件及电路，NMOS器件为应变Si平面沟道，PMOS器件为应变SiGe平面沟道，双极器件为Si SOI BJT。The purpose of the present invention is to provide a mixed crystal plane strained BiCMOS integrated device and circuit, the NMOS device is a strained Si planar channel, the PMOS device is a strained SiGe planar channel, and the bipolar device is a Si SOI BJT.

进一步、NMOS器件的导电沟道是张应变Si材料，NMOS器件的导电沟道为平面沟道。Further, the conductive channel of the NMOS device is a tensile strained Si material, and the conductive channel of the NMOS device is a planar channel.

进一步、PMOS器件的导电沟道是压应变SiGe材料，PMOS器件的导电沟道为平面沟道。Further, the conductive channel of the PMOS device is a compressively strained SiGe material, and the conductive channel of the PMOS device is a planar channel.

进一步、NMOS器件和PMOS器件的晶面不同，其中NMOS器件的晶面为（100），PMOS器件的晶面为（110）。Further, the crystal planes of the NMOS device and the PMOS device are different, wherein the crystal plane of the NMOS device is (100), and the crystal plane of the PMOS device is (110).

进一步、PMOS器件采用量子阱结构。Further, the PMOS device adopts a quantum well structure.

进一步、双极器件衬底为SOI材料。Further, the bipolar device substrate is made of SOI material.

本发明的另一目的在于提供一种混合晶面平面应变BiCMOS集成器件的制备方法，包括如下步骤：Another object of the present invention is to provide a method for preparing a mixed plane strain BiCMOS integrated device, comprising the following steps:

第一步、选取两片Si片，一块是N型掺杂浓度为1～5×10¹⁵cm^-3的Si（110）衬底片，作为上层有源层的基体材料，另一块是P型掺杂浓度为1～5×10¹⁵cm^-3的Si（100）衬底片，作为下层有源层的基体材料；对两片Si片表面进行氧化，氧化层厚度为0.5~1μm，采用化学机械抛光（CMP）工艺对两个氧化层表面进行抛光；The first step is to select two pieces of Si, one is a Si (110) substrate with an N-type doping concentration of 1-5×10 ¹⁵ cm ^-3 as the base material of the upper active layer, and the other is a P-type doped A Si (100) substrate with a dopant concentration of 1 to 5×10 ¹⁵ cm ^-3 is used as the base material of the lower active layer; the surface of the two Si wafers is oxidized, and the thickness of the oxide layer is 0.5 to 1 μm, and chemical mechanical polishing is used (CMP) process to polish the surface of the two oxide layers;

第二步、对上层有源层基体材料中注入氢，并将两片Si片氧化层相对置于超高真空环境中在350～480℃的温度下实现键合；将键合后的Si片温度升高100～200℃，使上层基体材料在注入的氢处断裂，对上层基体材料多余的部分进行剥离，保留100~200nm的Si材料，并在其断裂表面进行化学机械抛光（CMP），形成SOI衬底；The second step is to inject hydrogen into the base material of the upper active layer, and place the oxide layers of the two Si sheets facing each other in an ultra-high vacuum environment to achieve bonding at a temperature of 350-480°C; the bonded Si sheets The temperature rises by 100-200°C to break the upper matrix material at the injected hydrogen, peel off the excess part of the upper matrix material, retain the 100-200nm Si material, and perform chemical mechanical polishing (CMP) on the fractured surface. Forming an SOI substrate;

第三步、光刻双极器件有源区，外延生长一层掺杂浓度为1×10¹⁶～1×10¹⁷cm^-3的Si层，厚度为100～200nm，作为集电区；The third step is to lithography the active region of the bipolar device, and epitaxially grow a Si layer with a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁷ cm ^-3 , with a thickness of 100 to 200 nm, as the collector region;

第四步、利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积一层SiO₂，光刻隔离区，利用干法刻蚀工艺，在隔离区刻蚀出深度为2.5～3.5μm的深槽，利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积一层SiO₂和一层SiN，将深槽内表面全部覆盖，最后淀积SiO₂将深槽内填满，形成深槽隔离；Step 4: Deposit a layer of SiO ₂ on the surface of the substrate at 600-800°C by chemical vapor deposition (CVD), photolithographically isolate the area, and use dry etching to etch a layer of SiO 2 in the isolation area For deep grooves with a depth of 2.5-3.5 μm, a layer of SiO ₂ and a layer of SiN are deposited on the surface of the substrate by chemical vapor deposition (CVD) at 600-800 °C to completely cover the inner surface of the deep groove. Finally, deposit SiO ₂ to fill the deep trench to form deep trench isolation;

第五步、光刻集电区接触区，对集电区进行N型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为1×10¹⁹～1×10²⁰cm-3的重掺杂集电极；Step 5: Lithograph the contact area of the collector region, implant N-type impurities into the collector region, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 1×10 ¹⁹ to 1×10 ²⁰ cm-3 heavily doped collector;

第六步、在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为1×10¹⁸～5×10¹⁸cm^-3的基区；The sixth step is to thermally oxidize a _SiO2 layer on the surface of the substrate, photoresist the base area, implant P-type impurities into the base area, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 1 Base area of ×10 ¹⁸ ～5×10 ¹⁸ cm ^-3 ;

第七步、在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800～950℃，退火30～90min激活杂质，形成掺杂浓度为5×10¹⁹～5×10²⁰cm^-3的重掺杂发射区，在衬底表面利用化学汽相淀积（CVD）的方法，在600～800℃，淀积一SiO₂层；The seventh step is to thermally oxidize a _SiO2 layer on the surface of the substrate, photolithography the emission area, implant N-type impurities into the substrate, and activate the impurities by annealing at 800-950°C for 30-90 minutes to form a doping concentration of 5 For the heavily doped emitter region of ×10 ¹⁹ to 5×10 ²⁰ cm ^-3 , a SiO ₂ layer is deposited on the surface of the substrate by chemical vapor deposition (CVD) at 600-800°C;

第八步、利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积一层SiO₂，光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区，刻蚀出深度为1.7～2.9μm的深槽，将中间的氧化层刻透；利用化学汽相淀积（CVD）方法，在600～750℃，在（100）晶面衬底的NMOS器件有源区上选择性外延生长四层材料：第一层是厚度为200～400nm的P型Si缓冲层，掺杂浓度为1～5×10¹⁵cm^-3；第二层是厚度为1.3～2.1nm的P型SiGe渐变层，该层底部Ge组分是0％，顶部Ge组分是15～25％，掺杂浓度为1～5×10¹⁵cm^-3；第三层是Ge组分为15～25％，厚度为200～400nm的P型SiGe层，掺杂浓度为0.5～5×10¹⁷cm^-3；第四层是厚度为8～20nm的P型应变Si层，掺杂浓度为0.5～5×10¹⁷cm^-3，作为NMOS器件的沟道；利用湿法腐蚀，刻蚀掉表面的层SiO₂；Step 8: Deposit a layer of SiO ₂ on the surface of the substrate at 600-800°C by chemical vapor deposition (CVD), and photolithographically etch the active area of the NMOS device. In the active area, a deep groove with a depth of 1.7-2.9 μm is etched to penetrate the oxide layer in the middle; using chemical vapor deposition (CVD) method, at 600-750 ° C, on the (100) crystal plane substrate Selective epitaxial growth of four layers of materials on the active region of the NMOS device: the first layer is a P-type Si buffer layer with a thickness of 200-400 nm, and the doping concentration is 1-5×10 ¹⁵ cm ^-3 ; the second layer is a thick It is a P-type SiGe graded layer of 1.3-2.1nm, the Ge composition at the bottom of the layer is 0%, the Ge composition at the top is 15-25%, and the doping concentration is 1-5×10 ¹⁵ cm ^-3 ; the third layer is A P-type SiGe layer with a Ge composition of 15-25%, a thickness of 200-400nm, and a doping concentration of 0.5-5×10 ¹⁷ cm ^-3 ; the fourth layer is a P-type strained Si layer with a thickness of 8-20nm. The doping concentration is 0.5-5×10 ¹⁷ cm ^-3 , which is used as the channel of the NMOS device; the SiO ₂ layer on the surface is etched away by wet etching;

第九步、利用化学汽相淀积（CVD）方法，在600～800℃，在衬底表面淀积一层SiO₂，光刻PMOS器件有源区，利用化学汽相淀积（CVD）方法，在600～750℃，在PMOS器件有源区上选择性外延生长三层材料：第一层是厚度为100～200nm的N型Si缓冲层，掺杂浓度为0.5～5×10¹⁷cm^-3，第二层是厚度为8～20nm的N型SiGe应变层，Ge组分是15～25%，掺杂浓度为0.5～5×10¹⁷cm^-3，作为PMOS器件的沟道，第三层是厚度为3～5nm的本征弛豫Si帽层，形成PMOS器件有源区；利用湿法腐蚀，刻蚀掉表面的层SiO₂；Step 9: Deposit a layer of SiO ₂ on the surface of the substrate at 600-800°C by chemical vapor deposition (CVD) method, and photolithography the active area of the PMOS device by chemical vapor deposition (CVD) method , at 600-750°C, selectively epitaxially grow three layers of materials on the active region of the PMOS device: the first layer is an N-type Si buffer layer with a thickness of 100-200nm, and the doping concentration is 0.5-5×10 ¹⁷ cm ^{- 3.} The second layer is an N-type SiGe strained layer with a thickness of 8-20nm, the Ge composition is 15-25%, and the doping concentration is 0.5-5×10 ¹⁷ cm ^-3 , which is used as the channel of the PMOS device. The third The layer is an intrinsically relaxed Si cap layer with a thickness of 3-5nm, forming the active area of the PMOS device; using wet etching to etch away the SiO ₂ layer on the surface;

第十步、光刻场氧区，利用干法刻蚀工艺，在场氧区刻蚀出深度为0.3～0.5μm的浅槽；再利用化学汽相淀积（CVD）方法，在600～800℃，在浅槽内填充SiO₂；最后，用化学机械抛光（CMP）方法，除去多余的氧化层，形成浅槽隔离；The tenth step, photolithography field oxygen area, using dry etching process, etch a shallow groove with a depth of 0.3 ~ 0.5 μm in the field oxygen area; then use chemical vapor deposition (CVD) method, at 600 ~ 800 ° C , fill the shallow groove with SiO ₂ ; finally, use chemical mechanical polishing (CMP) to remove the excess oxide layer to form shallow groove isolation;

第十一步、在300～400℃，在有源区上用原子层化学汽相淀积（ALCVD）的方法淀积HfO₂层，厚度为6～10nm，作为NMOS器件和PMOS器件的栅介质，再利用化学汽相淀积（CVD）方法，在600～750℃，在栅介质层上淀积一层厚度为100～500nm的本征Poly-SiGe作为栅电极，Ge组分为10～30%；光刻NMOS和PMOS器件栅介质与栅多晶，形成栅极；The eleventh step, at 300-400°C, deposit an HfO ₂ layer on the active region by atomic layer chemical vapor deposition (ALCVD), with a thickness of 6-10nm, as the gate dielectric of NMOS devices and PMOS devices , and then use the chemical vapor deposition (CVD) method to deposit a layer of intrinsic Poly-SiGe with a thickness of 100-500 nm on the gate dielectric layer at 600-750 ° C as the gate electrode, and the Ge composition is 10-30 %; Photolithography of NMOS and PMOS device gate dielectric and gate polysilicon to form the gate;

第十二步、光刻NMOS器件有源区，对NMOS器件有源区进行N型离子注入，形成掺杂浓度为1～5×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）区域；光刻PMOS器件有源区，对PMOS器件有源区进行P型离子注入，形成掺杂浓度为1～5×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）区域；The twelfth step, photoetching the active area of the NMOS device, performing N-type ion implantation on the active area of the NMOS device, forming an N ^- type ^lightly doped source-drain structure (N -LDD) region; photolithography of the active region of the PMOS device, and performing P-type ion implantation on the active region of the PMOS device to form a P ^- type ^lightly doped source-drain structure (P -LDD) area;

第十三步、利用化学汽相淀积（CVD）方法，在600～800℃，在整个衬底上淀积一厚度为3～5nm的SiO₂层，用干法刻蚀掉这层SiO₂，形成NMOS器件和PMOS器件栅极侧墙；Step 13: Deposit a SiO ₂ layer with a thickness of 3-5nm on the entire substrate at 600-800°C by chemical vapor deposition (CVD), and etch this layer of SiO ₂ by dry method , forming gate sidewalls of NMOS devices and PMOS devices;

第十四步、光刻NMOS器件有源区，在NMOS器件有源区进行N型离子注入，自对准生成NMOS器件的源区、漏区和栅极；光刻PMOS器件有源区，在PMOS器件有源区进行N型离子注入，自对准生成PMOS器件的源区、漏区和栅极；The fourteenth step, photoetching the active area of the NMOS device, performing N-type ion implantation in the active area of the NMOS device, and self-aligning to generate the source area, drain area and gate of the NMOS device; photoetching the active area of the PMOS device, N-type ion implantation is performed on the active area of the PMOS device, and the source, drain and gate of the PMOS device are self-aligned;

第十五步、在整个衬底上用化学汽相淀积（CVD）方法，在600～800℃，淀积300～500nm厚的SiO₂层；光刻出引线窗口，在整个衬底上溅射一层金属钛（Ti），合金，自对准形成金属硅化物，清洗表面多余的金属，形成金属电极，构成MOS器件导电沟道为22～45nm的混合晶面平面应变BiCMOS集成器件。Step 15: Deposit a 300-500nm thick _SiO2 layer on the entire substrate by chemical vapor deposition (CVD) at 600-800°C; photoetch the lead window and sputter on the entire substrate Inject a layer of metal titanium (Ti), alloy, form metal silicide by self-alignment, clean the excess metal on the surface, form metal electrodes, and form a MOS device with a mixed crystal planar strain BiCMOS integrated device with a conductive channel of 22-45nm.

进一步、沟道长度取22～45nm。Further, the channel length is 22-45 nm.

进一步、该制备方法中所涉及的最高温度根据化学汽相淀积（CVD）工艺温度决定，最高温度小于等于800℃。Further, the maximum temperature involved in the preparation method is determined according to the chemical vapor deposition (CVD) process temperature, and the maximum temperature is less than or equal to 800°C.

本发明的另一目的在于提供一种混合晶面平面应变BiCMOS集成电路的制备方法，包括如下步骤：Another object of the present invention is to provide a method for preparing a mixed plane strain BiCMOS integrated circuit, comprising the following steps:

步骤1，SOI衬底材料制备的实现方法为：Step 1, the implementation method of SOI substrate material preparation is:

（1a）选取N型掺杂浓度为1×10¹⁵cm^-3的Si片，晶面为（110），对其表面进行氧化，氧化层厚度为0.5μm，作为上层的基体材料，并在该基体材料中注入氢；(1a) Select a Si sheet with an N-type doping concentration of 1×10 ¹⁵ cm ^{-3 and} a crystal plane of (110), oxidize its surface, and the thickness of the oxide layer is 0.5 μm, as the base material of the upper layer, and in the Hydrogen is injected into the matrix material;

（1b）选取P型掺杂浓度为1×10¹⁵cm^-3的Si片，晶面为（100），对其表面进行氧化，氧化层厚度为0.5μm，作为下层的基体材料；(1b) Select a Si sheet with a P-type doping concentration of 1×10 ¹⁵ cm ^{-3 and} a crystal plane of (100), oxidize its surface, and the thickness of the oxide layer is 0.5 μm, as the base material of the lower layer;

（1c）采用化学机械抛光（CMP）工艺，分别对下层和注入氢后的上层基体材料表面进行抛光处理；(1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

（1d）将抛光处理后的下层和上层基体材料表面SiO₂相对紧贴，置于超高真空环境中在350℃温度下实现键合；(1d) Put the SiO ₂ on the surface of the polished lower layer and the upper layer of the substrate relatively close to each other, and place them in an ultra-high vacuum environment to achieve bonding at a temperature of 350 °C;

（1e）将键合后的基片温度升高200℃，使上层基体材料在注入的氢处断裂，对上层基体材料多余的部分进行剥离，保留100nm的Si材料，并在该断裂表面进行化学机械抛光（CMP），形成SOI结构；(1e) Raise the temperature of the bonded substrate by 200°C to break the upper matrix material at the injected hydrogen, peel off the excess part of the upper matrix material, retain 100nm of Si material, and perform a chemical process on the fractured surface Mechanical polishing (CMP) to form SOI structure;

步骤2，隔离制备的实现方法为：Step 2, the implementation method of isolation preparation is:

（2a）光刻双极器件有源区，外延生长一层掺杂浓度为1×10¹⁶cm^-3的Si层，厚度为100nm，作为集电区；(2a) In the active region of the photolithographic bipolar device, a Si layer with a doping concentration of 1×10 ¹⁶ cm ^-3 is grown epitaxially, with a thickness of 100 nm, as the collector region;

（2b）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(2b) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（2c）光刻隔离区，利用干法刻蚀工艺，在隔离区刻蚀出深度为2.5μm的深槽；(2c) In the photolithography isolation area, a deep groove with a depth of 2.5 μm is etched in the isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在600℃，在深槽内表面淀积SiO₂层，将深槽内表面全部覆盖；(2d) Using the chemical vapor deposition (CVD) method, at 600 ° C, deposit a SiO ₂ layer on the inner surface of the deep groove to completely cover the inner surface of the deep groove;

（2e）利用化学汽相淀积（CVD）方法，在600℃，在深槽内SiO₂层上再淀积一层SiN层，将深槽内表面全部覆盖；(2e) Using the chemical vapor deposition (CVD) method, at 600 ° C, deposit a layer of SiN layer on the SiO ₂ layer in the deep groove to completely cover the inner surface of the deep groove;

（2f）利用化学汽相淀积（CVD）方法，在600℃，在深槽内填充SiO₂，利用化学机械抛光（CMP）方法，除去多余的氧化层，形成深槽隔离；(2f) Using the chemical vapor deposition (CVD) method, at 600°C, fill the deep groove with SiO ₂ , and use the chemical mechanical polishing (CMP) method to remove the redundant oxide layer to form a deep groove isolation;

步骤3，双极器件制备的实现方法为：Step 3, the implementation method of bipolar device preparation is:

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁹cm^-3的重掺杂集电极；(3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 800°C for 90 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁸cm^-3的基区；(3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 800°C for 90 minutes to form a doping concentration of 1×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800℃，退火90min激活杂质，成掺杂浓度为5×10¹⁹cm^-3的重掺杂发射区，构成双极晶体管；(3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 800°C for 90 minutes to activate the impurities, resulting in a doping concentration of 5×10 ¹⁹ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在600℃，淀积一SiO₂层；(3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 600°C;

步骤4，NMOS器件区制备的实现方法为：Step 4, the implementation method of NMOS device area preparation is:

（4a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(4a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（4b）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区，刻蚀出深度为1.7μm的深槽，将氧化层刻透；(4b) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.7 μm in the active area of the NMOS device, and etching the oxide layer through;

（4c）利用化学汽相淀积（CVD）的方法，在600℃，在深槽内沿（100）晶面生长一层厚度为200nm的P型Si缓冲层，掺杂浓度为1×10¹⁵cm^-3；(4c) Using chemical vapor deposition (CVD), grow a P-type Si buffer layer with a thickness of 200nm along the (100) crystal plane in the deep trench at 600°C, with a doping concentration of 1×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在600℃，P型缓冲层上生长一层厚度为1.3μm的P型Ge组分梯形分布的SiGe，底部Ge组分为0%，顶部为15%，掺杂浓度为1×10¹⁵cm^-3；(4d) Using chemical vapor deposition (CVD), grow a layer of SiGe with a thickness of 1.3 μm on the P-type buffer layer at 600 °C, with a trapezoidal distribution of P-type Ge composition, and the Ge composition at the bottom is 0%, The top is 15%, and the doping concentration is 1×10 ¹⁵ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在600℃，在Ge组分梯形分布的SiGe层上生长一层厚度为200nm的P型SiGe层，Ge组分为15％，掺杂浓度为5×10¹⁶cm^-3；(4e) Using chemical vapor deposition (CVD), at 600°C, grow a P-type SiGe layer with a thickness of 200nm on the SiGe layer with a trapezoidal distribution of Ge composition, the Ge composition is 15%, doped The concentration is 5×10 ¹⁶ cm ^-3 ;

（4f）利用化学汽相淀积（CVD）方法，在600℃，在SiGe层上生长一层厚度为20nm的应变Si层，掺杂浓度为5×10¹⁶cm^-3，作为NMOS器件的沟道；(4f) Using the chemical vapor deposition (CVD) method, at 600°C, grow a strained Si layer with a thickness of 20nm on the SiGe layer, with a doping concentration of 5×10 ¹⁶ cm ^-3 , as the trench of the NMOS device road;

（4g）利用湿法腐蚀，刻蚀掉表面的层SiO₂；(4g) using wet etching to etch away the SiO ₂ layer on the surface;

步骤5，PMOS器件区制备的实现方法为：Step 5, the implementation method of PMOS device area preparation is:

（5a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(5a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区沿（110）晶面生长一层厚度为200nm的N型Si缓冲层，掺杂浓度为5×10¹⁶cm^-3；(5b) Lithograph the active area of the PMOS device, using the chemical vapor deposition (CVD) method, at 600 ° C, grow a layer of N-type Si buffer with a thickness of 200 nm along the (110) crystal plane in the active area of the PMOS device layer with a doping concentration of 5×10 ¹⁶ cm ^-3 ;

（5c）利用化学汽相淀积（CVD）的方法，在600℃，在Si缓冲层上生长一层厚度为20nm的P型SiGe层，Ge组分为15%，掺杂浓度为5×10¹⁶cm^-3；(5c) Using chemical vapor deposition (CVD), grow a P-type SiGe layer with a thickness of 20 nm on the Si buffer layer at 600 °C, with a Ge composition of 15% and a doping concentration of 5×10 ¹⁶ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在600℃，在应变SiGe层上生长一层厚度为5nm的本征弛豫Si帽层，形成PMOS器件有源区；(5d) growing an intrinsically relaxed Si cap layer with a thickness of 5 nm on the strained SiGe layer at 600°C by chemical vapor deposition (CVD) to form the active region of the PMOS device;

（5e）利用湿法腐蚀，刻蚀掉表面的层SiO₂；(5e) using wet etching to etch away the SiO ₂ layer on the surface;

步骤6，浅槽隔离制备的实现方法为：Step 6, the implementation method of shallow groove isolation preparation is:

（6a）光刻场氧区，利用干法刻蚀工艺，在隔离区刻蚀出深度为0.3μm的浅槽；(6a) In the oxygen area of the photolithography field, a shallow groove with a depth of 0.3 μm is etched in the isolation area by using a dry etching process;

（6b）利用化学汽相淀积（CVD）方法，在600℃，在浅槽内填充SiO₂；(6b) Using chemical vapor deposition (CVD) method, at 600°C, fill the shallow groove with SiO ₂ ;

（6c）用化学机械抛光（CMP）方法，除去多余的氧化层，形成浅槽隔离；(6c) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation;

步骤7，MOS器件栅极与轻掺杂源漏（LDD）制备的实现方法为：Step 7, the implementation method of MOS device gate and lightly doped source and drain (LDD) preparation is as follows:

（7a）在300℃，在有源区上用原子层化学汽相淀积（ALCVD）的方法淀积HfO₂层，厚度为6nm，作为NMOS器件和PMOS器件的栅介质；(7a) At 300°C, deposit _an HfO2 layer with a thickness of 6nm on the active region by atomic layer chemical vapor deposition (ALCVD), as the gate dielectric of NMOS devices and PMOS devices;

（7b）利用化学汽相淀积（CVD）方法，在600℃，在栅介质层上淀积一层本征的Poly-SiGe，厚度为100nm，Ge组分为10%；(7b) Deposit a layer of intrinsic Poly-SiGe with a thickness of 100nm and a Ge composition of 10% on the gate dielectric layer at 600°C by chemical vapor deposition (CVD);

（7c）光刻NMOS和PMOS器件栅介质与栅多晶，形成栅极；(7c) Photolithography of NMOS and PMOS device gate dielectrics and gate polysilicon to form gates;

（7d）光刻NMOS器件有源区，对NMOS器件有源区进行N型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）区域；(7d) Lithographically etches the active region of the NMOS device, and performs N-type ion implantation on the active region of the NMOS device to form an N-type lightly doped source-drain structure (N-LDD) region with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

（7e）光刻PMOS器件有源区，对PMOS器件有源区进行P型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）区域；(7e) Lithograph the active region of the PMOS device, perform P-type ion implantation on the active region of the PMOS device, and form a P-type lightly doped source-drain structure (P-LDD) region with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

步骤8，MOS器件形成的实现方法为：Step 8, the implementation method of MOS device formation is:

（8a）利用化学汽相淀积（CVD）方法，在600℃，在整个衬底上淀积一厚度为3nm的SiO₂层；(8a) Deposit a _SiO2 layer with a thickness of 3 nm on the entire substrate at 600 °C by chemical vapor deposition (CVD);

（8b）利用干法刻蚀工艺，蚀掉这层SiO₂，保留NMOS器件和PMOS器件栅极侧墙；(8b) using a dry etching process to etch away this layer of SiO ₂ , and retain the NMOS device and the gate sidewall of the PMOS device;

（8c）光刻NMOS器件有源区，在NMOS器件有源区进行N型离子注入，自对准生成NMOS器件的源、漏区和栅极；(8c) Lithograph the active area of the NMOS device, perform N-type ion implantation in the active area of the NMOS device, and self-align to generate the source, drain and gate of the NMOS device;

（8d）光刻PMOS器件有源区，在PMOS器件有源区进行N型离子注入，自对准生成PMOS器件的源、漏区和栅极；(8d) Lithograph the active area of the PMOS device, perform N-type ion implantation in the active area of the PMOS device, and self-align to generate the source, drain and gate of the PMOS device;

步骤9，构成BiCMOS集成电路的实现方法为：Step 9, the implementation method of forming a BiCMOS integrated circuit is:

（9a）用化学汽相淀积（CVD）方法，在600℃，在整个衬底上淀积300nm厚的SiO₂层；(9a) Deposit a 300 nm thick _SiO2 layer on the entire substrate at 600 °C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属钛（Ti），合金，自对准形成金属硅化物，清洗表面多余的金属，形成金属接触；(9b) Photoetching the lead window, sputtering a layer of metal titanium (Ti) and alloy on the entire substrate, self-aligning to form a metal silicide, cleaning the excess metal on the surface, and forming a metal contact;

（9c）溅射金属，光刻引线，分别形成NMOS器件的源电极、栅电极、漏电极和PMOS器件的漏电极、源电极、栅电极，以及双极晶体管发射极、基极金属引、集电极金属引线，最终MOS器件构成导电沟道为22nm的混合晶面平面应变BiCMOS集成器件及电路。(9c) Sputtering metal, photolithography leads, respectively forming the source electrode, gate electrode, drain electrode of NMOS devices and the drain electrode, source electrode, gate electrode of PMOS devices, as well as bipolar transistor emitter, base metal lead, collector Electrode metal leads, the final MOS device constitutes a mixed crystal plane strain BiCMOS integrated device and circuit with a conductive channel of 22nm.

本发明具有如下优点：The present invention has the following advantages:

1．本发明制备的混合晶面平面应变BiCMOS集成器件及电路中采用了SOI衬底，降低了器件与电路的功耗，提高了器件与电路的可靠性；1. The mixed crystal planar strain BiCMOS integrated device and the circuit prepared by the present invention adopt the SOI substrate, which reduces the power consumption of the device and the circuit, and improves the reliability of the device and the circuit;

2．本发明制备的混合晶面平面应变BiCMOS集成器件及电路采用了混合晶面衬底技术，即在同一个衬底片上分布有（100）和（110）这两种晶面，在（100）晶面上电子迁移率最高，而对于空穴，（110）晶面上最高，为（100）晶面上的2.5倍，本发明结合了载流子迁移率同时达到最高的两种晶面，能在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率；2. The mixed crystal plane strain BiCMOS integrated device and circuit prepared by the present invention adopt the mixed crystal plane substrate technology, that is, two crystal planes (100) and (110) are distributed on the same substrate, and the (100) crystal plane The highest electron mobility on the plane, and for holes, the (110) crystal plane is the highest, which is 2.5 times that of the (100) crystal plane. The present invention combines the two crystal planes with the highest carrier mobility at the same time, and can Improving the carrier mobility of one type of device without reducing the carrier mobility of another type of device;

3．本发明制备的混合晶面平面应变BiCMOS集成器件及电路，采用选择性外延技术，分别在NMOS器件和PMOS器件有源区选择性生长张应变Si和压应变SiGe材料，使NMOS器件和PMOS器件频率性能和电流驱动能力等电学性能能够获得同时提升，从而CMOS器件与集成电路性能获得了增强；3. The mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention adopt selective epitaxy technology to selectively grow tensile strain Si and compressive strain SiGe materials in the active regions of NMOS devices and PMOS devices respectively, so that the frequency of NMOS devices and PMOS devices Electrical properties such as performance and current drive capability can be improved simultaneously, thereby enhancing the performance of CMOS devices and integrated circuits;

4．本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中MOS器件采用了高K值的HfO₂作为栅介质，提高了MOS器件的栅控能力，增强了NMOS和PMOS器件的电学性能；4. The mixed crystal planar strain BiCMOS integrated device and the circuit structure prepared by the present invention adopt _HfO2 with a high K value as the gate dielectric, which improves the gate control ability of the MOS device and enhances the electrical performance of the NMOS and PMOS devices;

5．本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中PMOS器件为量子阱器件，即应变SiGe沟道层处于Si帽层和体Si层之间，与表面沟道器件相比，该器件能有效地降低沟道界面散射，提高了器件电学特性；同时，量子阱可以使热电子注入栅介质中的问题得到改善，增加了器件和电路的可靠性；5. The PMOS device in the mixed plane strain BiCMOS integrated device and circuit structure prepared by the present invention is a quantum well device, that is, the strained SiGe channel layer is between the Si cap layer and the bulk Si layer. Compared with the surface channel device, the device has It can effectively reduce channel interface scattering and improve the electrical characteristics of the device; at the same time, quantum wells can improve the problem of hot electron injection into the gate dielectric, increasing the reliability of devices and circuits;

6．本发明制备混合晶面平面应变BiCMOS集成器件及电路工艺中，采用Poly-SiGe材料作为栅电极，其功函数随Ge组分的变化而变化，通过调节Poly-SiGe中Ge组分，实现CMOS阈值电压可连续调整，减少了工艺步骤，降低了工艺难度；6. In the preparation of the mixed crystal planar strain BiCMOS integrated device and the circuit technology of the present invention, the Poly-SiGe material is used as the gate electrode, and its work function changes with the change of the Ge composition, and the CMOS threshold is realized by adjusting the Ge composition in the Poly-SiGe The voltage can be adjusted continuously, which reduces the process steps and process difficulty;

7．本发明制备的混合晶面平面应变BiCMOS集成器件及电路过程中涉及的最高温度为800℃，低于引起应变Si沟道应力弛豫的工艺温度，因此该制备方法能有效地保持应变Si沟道应力，提高集成电路的性能；7. The highest temperature involved in the process of the mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention is 800°C, which is lower than the process temperature that causes stress relaxation of the strained Si channel, so the preparation method can effectively maintain the strained Si channel Stress, improve the performance of integrated circuits;

8.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中，双极器件采用SOI衬底的集电区厚度较传统器件薄，因此，该器件存在集电区横向扩展效应，并能够在集电区形成二维电场，从而提高了该器件的反向击穿电压和Early电压，在相同的击穿特性下，具有比传统器件更优异的特征频率。8. In the mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention, the thickness of the collector region of the SOI substrate used in the bipolar device is thinner than that of the traditional device. Therefore, the device has a collector region lateral extension effect, and can be used in The collector area forms a two-dimensional electric field, thereby improving the reverse breakdown voltage and early voltage of the device, and has a better characteristic frequency than traditional devices under the same breakdown characteristics.

附图说明 Description of drawings

图1是本发明提供的混合晶面平面应变BiCMOS集成器件制备的工艺流程图。Fig. 1 is a flow chart of the preparation process of the mixed plane strain BiCMOS integrated device provided by the present invention.

具体实施方式 Detailed ways

为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

本发明实施例提供了一种混合晶面平面应变BiCMOS集成器件及电路，NMOS器件为应变Si平面沟道，PMOS器件为应变SiGe平面沟道，双极器件为Si SOI BJT。The embodiment of the present invention provides a mixed plane strain BiCMOS integrated device and circuit, the NMOS device is a strained Si planar channel, the PMOS device is a strained SiGe planar channel, and the bipolar device is a Si SOI BJT.

作为本发明实施例的一优化方案，NMOS器件的导电沟道是张应变Si材料，NMOS器件的导电沟道为平面沟道。As an optimized solution of the embodiment of the present invention, the conductive channel of the NMOS device is a tensile strained Si material, and the conductive channel of the NMOS device is a planar channel.

作为本发明实施例的一优化方案，PMOS器件的导电沟道是压应变SiGe材料，PMOS器件的导电沟道为平面沟道。As an optimized solution of the embodiment of the present invention, the conduction channel of the PMOS device is a compressively strained SiGe material, and the conduction channel of the PMOS device is a planar channel.

作为本发明实施例的一优化方案，PMOS器件的导电沟道是压应变SiGe材料，PMOS器件的导电沟道为平面沟道。As an optimized solution of the embodiment of the present invention, the conduction channel of the PMOS device is a compressively strained SiGe material, and the conduction channel of the PMOS device is a planar channel.

作为本发明实施例的一优化方案，PMOS器件采用量子阱结构。As an optimization scheme of the embodiment of the present invention, the PMOS device adopts a quantum well structure.

作为本发明实施例的一优化方案，双极器件衬底为SOI材料。As an optimized solution of the embodiment of the present invention, the bipolar device substrate is made of SOI material.

以下参照附图1，对本发明混合晶面平面应变BiCMOS集成器件及电路的制备方法工艺流程作进一步详细描述。Referring to the accompanying drawing 1, the process flow of the preparation method of the mixed plane strain BiCMOS integrated device and circuit of the present invention will be further described in detail.

实施例1：制备22nm混合晶面平面应变BiCMOS集成器件及电路，具体步骤如下：Embodiment 1: Prepare 22nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

步骤1，SOI衬底材料制备。Step 1, SOI substrate material preparation.

（1a）选取N型掺杂浓度为1×10¹⁵cm^-3的Si片，晶面为（110），对其表面进行氧化，氧化层厚度为0.5μm，作为上层的基体材料，并在该基体材料中注入氢；(1a) Select a Si sheet with an N-type doping concentration of 1×10 ¹⁵ cm ^{-3 and} a crystal plane of (110), oxidize its surface, and the thickness of the oxide layer is 0.5 μm, as the base material of the upper layer, and in the Hydrogen is injected into the matrix material;

（1b）选取P型掺杂浓度为1×10¹⁵cm^-3的Si片，晶面为（100），对其表面进行氧化，氧化层厚度为0.5μm，作为下层的基体材料；(1b) Select a Si sheet with a P-type doping concentration of 1×10 ¹⁵ cm ^{-3 and} a crystal plane of (100), oxidize its surface, and the thickness of the oxide layer is 0.5 μm, as the base material of the lower layer;

（1c）采用化学机械抛光（CMP）工艺，分别对下层和注入氢后的上层基体材料表面进行抛光处理；(1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

（1d）将抛光处理后的下层和上层基体材料表面SiO₂相对紧贴，置于超高真空环境中在350℃温度下实现键合；(1d) Put the SiO ₂ on the surface of the polished lower layer and the upper layer of the substrate relatively close to each other, and place them in an ultra-high vacuum environment to achieve bonding at a temperature of 350 °C;

（1e）将键合后的基片温度升高200℃，使上层基体材料在注入的氢处断裂，对上层基体材料多余的部分进行剥离，保留100nm的Si材料，并在该断裂表面进行化学机械抛光（CMP），形成SOI结构。(1e) Raise the temperature of the bonded substrate by 200°C to break the upper matrix material at the injected hydrogen, peel off the excess part of the upper matrix material, retain 100nm of Si material, and perform a chemical process on the fractured surface Mechanical polishing (CMP) to form the SOI structure.

步骤2，隔离制备。Step 2, isolation preparation.

（2a）光刻双极器件有源区，外延生长一层掺杂浓度为1×10¹⁶cm^-3的Si层，厚度为100nm，作为集电区；(2a) In the active region of the photolithographic bipolar device, a Si layer with a doping concentration of 1×10 ¹⁶ cm ^-3 is grown epitaxially, with a thickness of 100 nm, as the collector region;

（2b）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(2b) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（2c）光刻隔离区，利用干法刻蚀工艺，在隔离区刻蚀出深度为2.5μm的深槽；(2c) In the photolithography isolation area, a deep groove with a depth of 2.5 μm is etched in the isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在600℃，在深槽内表面淀积SiO₂层，将深槽内表面全部覆盖；(2d) Using the chemical vapor deposition (CVD) method, at 600 ° C, deposit a SiO ₂ layer on the inner surface of the deep groove to completely cover the inner surface of the deep groove;

（2e）利用化学汽相淀积（CVD）方法，在600℃，在深槽内SiO₂层上再淀积一层SiN层，将深槽内表面全部覆盖；(2e) Using the chemical vapor deposition (CVD) method, at 600 ° C, deposit a layer of SiN layer on the SiO ₂ layer in the deep groove to completely cover the inner surface of the deep groove;

（2f）利用化学汽相淀积（CVD）方法，在600℃，在深槽内填充SiO₂，利用化学机械抛光（CMP）方法，除去多余的氧化层，形成深槽隔离。(2f) Using the chemical vapor deposition (CVD) method, at 600°C, fill the deep groove with SiO ₂ , and use the chemical mechanical polishing (CMP) method to remove the redundant oxide layer to form the deep groove isolation.

步骤3，双极器件制备。Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁹cm^-3的重掺杂集电极；(3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 800°C for 90 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在800℃，退火90min激活杂质，形成掺杂浓度为1×10¹⁸cm^-3的基区；(3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 800°C for 90 minutes to form a doping concentration of 1×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在800℃，退火90min激活杂质，成掺杂浓度为5×10¹⁹cm^-3的重掺杂发射区，构成双极晶体管；(3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 800°C for 90 minutes to activate the impurities, resulting in a doping concentration of 5×10 ¹⁹ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在600℃，淀积一SiO₂层。(3d) Deposit a SiO ₂ layer on the substrate surface by chemical vapor deposition (CVD) at 600°C.

步骤4，NMOS器件区制备。Step 4, preparation of the NMOS device area.

（4a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(4a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（4b）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区，刻蚀出深度为1.7μm的深槽，将氧化层刻透；(4b) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.7 μm in the active area of the NMOS device, and etching the oxide layer through;

（4c）利用化学汽相淀积（CVD）的方法，在600℃，在深槽内沿（100）晶面生长一层厚度为200nm的P型Si缓冲层，掺杂浓度为1×10¹⁵cm^-3；(4c) Using chemical vapor deposition (CVD), grow a P-type Si buffer layer with a thickness of 200nm along the (100) crystal plane in the deep trench at 600°C, with a doping concentration of 1×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在600℃，P型缓冲层上生长一层厚度为1.3μm的P型Ge组分梯形分布的SiGe，底部Ge组分为0%，顶部为15%，掺杂浓度为1×10¹⁵cm^-3；(4d) Using chemical vapor deposition (CVD), grow a layer of SiGe with a thickness of 1.3 μm on the P-type buffer layer at 600 °C, with a trapezoidal distribution of P-type Ge composition, and the Ge composition at the bottom is 0%, The top is 15%, and the doping concentration is 1×10 ¹⁵ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在600℃，在Ge组分梯形分布的SiGe层上生长一层厚度为200nm的P型SiGe层，Ge组分为15％，掺杂浓度为5×10¹⁶cm^-3；(4e) Using chemical vapor deposition (CVD), at 600°C, grow a P-type SiGe layer with a thickness of 200nm on the SiGe layer with a trapezoidal distribution of Ge composition, the Ge composition is 15%, doped The concentration is 5×10 ¹⁶ cm ^-3 ;

（4f）利用化学汽相淀积（CVD）方法，在600℃，在SiGe层上生长一层厚度为20nm的应变Si层，掺杂浓度为5×10¹⁶cm^-3，作为NMOS器件的沟道；(4f) Using the chemical vapor deposition (CVD) method, at 600°C, grow a strained Si layer with a thickness of 20nm on the SiGe layer, with a doping concentration of 5×10 ¹⁶ cm ^-3 , as the trench of the NMOS device road;

（4g）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(4g) Etch away the SiO ₂ layer on the surface by wet etching.

步骤5，PMOS器件区制备。Step 5, preparing the PMOS device area.

（5a）利用化学汽相淀积（CVD）方法，在600℃，在衬底表面淀积一层SiO₂；(5a) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用化学汽相淀积（CVD）的方法，在600℃，在PMOS器件有源区沿（110）晶面生长一层厚度为200nm的N型Si缓冲层，掺杂浓度为5×10¹⁶cm^-3；(5b) Lithograph the active area of the PMOS device, using the chemical vapor deposition (CVD) method, at 600 ° C, grow a layer of N-type Si buffer with a thickness of 200 nm along the (110) crystal plane in the active area of the PMOS device layer with a doping concentration of 5×10 ¹⁶ cm ^-3 ;

（5c）利用化学汽相淀积（CVD）的方法，在600℃，在Si缓冲层上生长一层厚度为20nm的P型SiGe层，Ge组分为15%，掺杂浓度为5×10¹⁶cm^-3；(5c) Using chemical vapor deposition (CVD), grow a P-type SiGe layer with a thickness of 20 nm on the Si buffer layer at 600 °C, with a Ge composition of 15% and a doping concentration of 5×10 ¹⁶ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在600℃，在应变SiGe层上生长一层厚度为5nm的本征弛豫Si帽层，形成PMOS器件有源区；(5d) growing an intrinsically relaxed Si cap layer with a thickness of 5 nm on the strained SiGe layer at 600°C by chemical vapor deposition (CVD) to form the active region of the PMOS device;

（5e）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(5e) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，浅槽隔离制备。Step 6, shallow trench isolation preparation.

（6a）光刻场氧区，利用干法刻蚀工艺，在隔离区刻蚀出深度为0.3μm的浅槽；(6a) In the oxygen area of the photolithography field, a shallow groove with a depth of 0.3 μm is etched in the isolation area by using a dry etching process;

（6b）利用化学汽相淀积（CVD）方法，在600℃，在浅槽内填充SiO₂；(6b) Using chemical vapor deposition (CVD) method, at 600°C, fill the shallow groove with SiO ₂ ;

（6c）用化学机械抛光（CMP）方法，除去多余的氧化层，形成浅槽隔离。(6c) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

步骤7，MOS器件栅极与轻掺杂源漏（LDD）制备。Step 7, the gate and lightly doped source and drain (LDD) of the MOS device are prepared.

（7a）在300℃，在有源区上用原子层化学汽相淀积（ALCVD）的方法淀积HfO₂层，厚度为6nm，作为NMOS器件和PMOS器件的栅介质；(7a) At 300°C, deposit _an HfO2 layer with a thickness of 6nm on the active region by atomic layer chemical vapor deposition (ALCVD), as the gate dielectric of NMOS devices and PMOS devices;

（7b）利用化学汽相淀积（CVD）方法，在600℃，在栅介质层上淀积一层本征的Poly-SiGe，厚度为100nm，Ge组分为10%；(7b) Deposit a layer of intrinsic Poly-SiGe with a thickness of 100nm and a Ge composition of 10% on the gate dielectric layer at 600°C by chemical vapor deposition (CVD);

（7c）光刻MOS器件栅介质与栅多晶，形成栅极；(7c) Lithographic MOS device gate dielectric and gate polysilicon to form the gate;

（7d）光刻NMOS器件有源区，对NMOS器件有源区进行N型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）区域；(7d) Lithographically etches the active region of the NMOS device, and performs N-type ion implantation on the active region of the NMOS device to form an N-type lightly doped source-drain structure (N-LDD) region with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

（7e）光刻PMOS器件有源区，对PMOS器件有源区进行P型离子注入，形成掺杂浓度为1×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）区域。(7e) Lithograph the active region of the PMOS device, perform P-type ion implantation on the active region of the PMOS device, and form a P-type lightly doped source-drain structure (P-LDD) region with a doping concentration of 1×10 ¹⁸ cm ^-3 .

步骤8，MOS器件形成。Step 8, MOS devices are formed.

（8a）利用化学汽相淀积（CVD）方法，在600℃，在整个衬底上淀积一厚度为3nm的SiO₂层；(8a) Deposit a _SiO2 layer with a thickness of 3 nm on the entire substrate at 600 °C by chemical vapor deposition (CVD);

（8b）利用干法刻蚀工艺，蚀掉这层SiO₂，保留NMOS器件和PMOS器件栅极侧墙；(8b) using a dry etching process to etch away this layer of SiO ₂ , and retain the NMOS device and the gate sidewall of the PMOS device;

（8c）光刻NMOS器件有源区，在NMOS器件有源区进行N型离子注入，自对准生成NMOS器件的源、漏区和栅极；(8c) Lithograph the active area of the NMOS device, perform N-type ion implantation in the active area of the NMOS device, and self-align to generate the source, drain and gate of the NMOS device;

（8d）光刻PMOS器件有源区，在PMOS器件有源区进行N型离子注入，自对准生成PMOS器件的源、漏区和栅极。(8d) Lithograph the active region of the PMOS device, perform N-type ion implantation in the active region of the PMOS device, and self-align to generate the source, drain and gate of the PMOS device.

步骤9，构成BiCMOS集成电路。Step 9, forming a BiCMOS integrated circuit.

（9a）用化学汽相淀积（CVD）方法，在600℃，在整个衬底上淀积300nm厚的SiO₂层；(9a) Deposit a 300 nm thick _SiO2 layer on the entire substrate at 600 °C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属钛（Ti），合金，自对准形成金属硅化物，清洗表面多余的金属，形成金属接触；(9b) Photoetching the lead window, sputtering a layer of metal titanium (Ti) and alloy on the entire substrate, self-aligning to form a metal silicide, cleaning the excess metal on the surface, and forming a metal contact;

（9c）溅射金属，光刻引线，分别形成NMOS器件的源电极、栅电极、漏电极和PMOS器件的漏电极、源电极、栅电极，以及双极晶体管发射极、基极金属引、集电极金属引线，最终MOS器件构成导电沟道为22nm的混合晶面平面应变BiCMOS集成器件及电路。(9c) Sputtering metal, photolithography leads, respectively forming the source electrode, gate electrode, drain electrode of NMOS devices and the drain electrode, source electrode, gate electrode of PMOS devices, as well as bipolar transistor emitter, base metal lead, collector Electrode metal leads, the final MOS device constitutes a mixed crystal plane strain BiCMOS integrated device and circuit with a conductive channel of 22nm.

实施例2：制备30nm混合晶面平面应变BiCMOS集成器件及电路，具体步骤如下：Embodiment 2: Prepare 30nm mixed crystal plane plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

步骤1，SOI衬底材料制备。Step 1, SOI substrate material preparation.

（1a）选取N型掺杂浓度为3×10¹⁵cm^-3的Si片，晶面为（110），对其表面进行氧化，氧化层厚度为0.75μm，作为上层的基体材料，并在该基体材料中注入氢；(1a) Select a Si sheet with an N-type doping concentration of 3×10 ¹⁵ cm ^{-3 and} a crystal plane of (110), oxidize its surface, and the thickness of the oxide layer is 0.75 μm, as the base material of the upper layer, and in the Hydrogen is injected into the matrix material;

（1b）选取P型掺杂浓度为3×10¹⁵cm^-3的Si片，晶面为（100），对其表面进行氧化，氧化层厚度为0.75μm，作为下层的基体材料；(1b) Select a Si sheet with a P-type doping concentration of 3×10 ¹⁵ cm ^{-3 and} a crystal plane of (100), oxidize its surface, and the thickness of the oxide layer is 0.75 μm, as the base material of the lower layer;

（1c）采用化学机械抛光（CMP）工艺，分别对下层和注入氢后的上层有源层基体材料表面进行抛光处理；(1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

（1d）将抛光处理后的下层和上层基体材料表面SiO₂相对紧贴，置于超高真空环境中在400℃温度下实现键合；(1d) Put the SiO ₂ on the surface of the polished lower layer and the upper layer of the substrate relatively close to each other, and place them in an ultra-high vacuum environment to achieve bonding at a temperature of 400 °C;

（1e）将键合后的基片温度升高150℃，使上层基体材料在注入的氢处断裂，对上层基体材料多余的部分进行剥离，保留150nm的Si材料，并在该断裂表面进行化学机械抛光（CMP），形成SOI结构。(1e) Raise the temperature of the bonded substrate by 150°C to break the upper matrix material at the injected hydrogen, peel off the excess part of the upper matrix material, retain 150nm of Si material, and perform chemical treatment on the fractured surface Mechanical polishing (CMP) to form the SOI structure.

步骤2，隔离制备。Step 2, isolation preparation.

（2a）光刻双极器件有源区，外延生长一层掺杂浓度为5×10¹⁶cm^-3的Si层，厚度为150nm，作为集电区；(2a) In the active region of the photolithographic bipolar device, a Si layer with a doping concentration of 5×10 ¹⁶ cm ^-3 is grown epitaxially, with a thickness of 150 nm, as the collector region;

（2b）利用化学汽相淀积（CVD）方法，在700℃，在衬底表面淀积一层SiO₂；(2b) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（2c）光刻隔离区，利用干法刻蚀工艺，在隔离区刻蚀出深度为3μm的深槽；(2c) In the photolithography isolation area, a deep groove with a depth of 3 μm is etched in the isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在700℃，在深槽内表面淀积SiO₂层，将深槽内表面全部覆盖；(2d) Using the chemical vapor deposition (CVD) method, at 700 ° C, deposit a SiO ₂ layer on the inner surface of the deep groove to completely cover the inner surface of the deep groove;

（2e）利用化学汽相淀积（CVD）方法，在700℃，在深槽内SiO₂层上再淀积一层SiN层，将深槽内表面全部覆盖；(2e) Using the chemical vapor deposition (CVD) method, at 700 ° C, deposit a layer of SiN on the SiO ₂ layer in the deep groove to completely cover the inner surface of the deep groove;

（2f）利用化学汽相淀积（CVD）方法，在700℃，在深槽内填充SiO₂，利用化学机械抛光（CMP）方法，除去多余的氧化层，形成深槽隔离。(2f) Using the chemical vapor deposition (CVD) method, at 700°C, fill the deep groove with SiO ₂ , and use the chemical mechanical polishing (CMP) method to remove the redundant oxide layer to form the deep groove isolation.

步骤3，双极器件制备。Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在900℃，退火45min激活杂质，形成掺杂浓度为5×10¹⁹cm^-3的重掺杂集电极；(3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 900°C for 45 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 5×10 ¹⁹ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在900℃，退火45min激活杂质，形成掺杂浓度为3×10¹⁸cm^-3的基区；(3b) Thermally oxidize a SiO ₂ layer on the substrate surface, photolithographically etch the base region, implant P-type impurities into the base region, and activate the impurities by annealing at 900°C for 45 minutes to form a doping concentration of 3×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在900℃，退火45min激活杂质，成掺杂浓度为1×10²⁰cm^-3的重掺杂发射区，构成双极晶体管；(3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 900°C for 45min to activate the impurities, resulting in a doping concentration of 1×10 ²⁰ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在700℃，淀积一SiO₂层。(3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 700°C.

步骤4，NMOS器件区制备。Step 4, preparation of the NMOS device area.

（4a）利用化学汽相淀积（CVD）方法，在700℃，在衬底表面淀积一层SiO₂；(4a) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（4b）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区，刻蚀出深度为2.3μm的深槽，将氧化层刻透；(4b) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 2.3 μm in the active area of the NMOS device, and etching the oxide layer through;

（4c）利用化学汽相淀积（CVD）的方法，在700℃，在深槽内沿（100）晶面生长一层厚度为300nm的P型Si缓冲层，掺杂浓度为3×10¹⁵cm^-3；(4c) Using chemical vapor deposition (CVD), grow a P-type Si buffer layer with a thickness of 300nm along the (100) crystal plane in the deep trench at 700°C, with a doping concentration of 3×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在700℃，P型缓冲层上生长一层厚度为1.7μm的P型Ge组分梯形分布的SiGe，底部Ge组分为0%，顶部为20%，掺杂浓度为3×10¹⁵cm^-3；(4d) Using chemical vapor deposition (CVD), grow a layer of SiGe with a thickness of 1.7 μm on the P-type buffer layer at 700 °C, with a trapezoidal distribution of P-type Ge components, and the Ge component at the bottom is 0%, The top is 20%, and the doping concentration is 3×10 ¹⁵ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在700℃，在Ge组分梯形分布的SiGe层上生长一层厚度为300nm的P型SiGe层，Ge组分为20％，掺杂浓度为1×10¹⁷cm^-3；(4e) Using chemical vapor deposition (CVD), at 700°C, grow a P-type SiGe layer with a thickness of 300nm on the SiGe layer with a trapezoidal distribution of Ge composition, the Ge composition is 20%, doped The concentration is 1×10 ¹⁷ cm ^-3 ;

（4f）利用化学汽相淀积（CVD）方法，在700℃，在SiGe层上生长一层厚度为15nm的应变Si层，掺杂浓度为1×10¹⁷cm^-3，作为NMOS器件的沟道；(4f) A strained Si layer with a thickness of 15nm was grown on the SiGe layer at 700°C by chemical vapor deposition (CVD) with a doping concentration of 1×10 ¹⁷ cm ^-3 as the trench of the NMOS device. road;

（4g）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(4g) Etch away the SiO ₂ layer on the surface by wet etching.

步骤5，PMOS器件区制备。Step 5, preparing the PMOS device area.

（5a）利用化学汽相淀积（CVD）方法，在700℃，在衬底表面淀积一层SiO₂；(5a) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用化学汽相淀积（CVD）的方法，在700℃，在PMOS器件有源区沿（110）晶面生长一层厚度为300nm的N型Si缓冲层，掺杂浓度为1×10¹⁷cm^-3；(5b) Lithograph the active area of the PMOS device, using the chemical vapor deposition (CVD) method, at 700 ° C, grow a layer of N-type Si buffer with a thickness of 300 nm along the (110) crystal plane in the active area of the PMOS device layer with a doping concentration of 1×10 ¹⁷ cm ^-3 ;

（5c）利用化学汽相淀积（CVD）的方法，在700℃，在Si缓冲层上生长一层厚度为15nm的P型SiGe层，Ge组分为20%，掺杂浓度为1×10¹⁷cm^-3；(5c) Using chemical vapor deposition (CVD), grow a P-type SiGe layer with a thickness of 15 nm on the Si buffer layer at 700 °C, with a Ge composition of 20% and a doping concentration of 1×10 ¹⁷ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在700℃，在应变SiGe层上生长一层厚度为4nm的本征弛豫Si帽层，形成PMOS器件有源区；(5d) Using chemical vapor deposition (CVD), at 700°C, grow an intrinsically relaxed Si cap layer with a thickness of 4 nm on the strained SiGe layer to form the active region of the PMOS device;

（5e）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(5e) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，浅槽隔离制备。Step 6, shallow trench isolation preparation.

（6a）光刻场氧区，利用干法刻蚀工艺，在隔离区刻蚀出深度为0.4μm的浅槽；(6a) In the oxygen area of the photolithography field, a shallow groove with a depth of 0.4 μm is etched in the isolation area by using a dry etching process;

（6b）利用化学汽相淀积（CVD）方法，在700℃，在浅槽内填充SiO₂；(6b) Fill the shallow groove with SiO ₂ at 700°C by chemical vapor deposition (CVD);

（6c）用化学机械抛光（CMP）方法，除去多余的氧化层，形成浅槽隔离。(6c) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

步骤7，MOS器件栅极与轻掺杂源漏（LDD）制备。Step 7, the gate and lightly doped source and drain (LDD) of the MOS device are prepared.

（7a）在350℃，在有源区上用原子层化学汽相淀积（ALCVD）的方法淀积HfO₂层，厚度为8nm，作为NMOS器件和PMOS器件的栅介质；(7a) At 350°C, a layer of HfO ₂ was deposited on the active region by atomic layer chemical vapor deposition (ALCVD), with a thickness of 8nm, as the gate dielectric of NMOS devices and PMOS devices;

（7b）利用化学汽相淀积（CVD）方法，在700℃，在栅介质层上淀积一层本征的Poly-SiGe，厚度为300nm，Ge组分为20%；(7b) Deposit a layer of intrinsic Poly-SiGe with a thickness of 300nm and a Ge composition of 20% on the gate dielectric layer at 700°C by chemical vapor deposition (CVD);

（7c）光刻MOS器件栅介质与栅多晶，形成栅极；(7c) Lithographic MOS device gate dielectric and gate polysilicon to form the gate;

（7d）光刻NMOS器件有源区，对NMOS器件有源区进行N型离子注入，形成掺杂浓度为3×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）区域；(7d) Lithographically etches the active area of the NMOS device, and performs N-type ion implantation on the active area of the NMOS device to form an N-type lightly doped source-drain structure (N-LDD) region with a doping concentration of 3×10 ¹⁸ cm ^-3 ;

（7e）光刻PMOS器件有源区，对PMOS器件有源区进行P型离子注入，形成掺杂浓度为3×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）区域。(7e) Lithograph the active region of the PMOS device, perform P-type ion implantation on the active region of the PMOS device, and form a P-type lightly doped source-drain structure (P-LDD) region with a doping concentration of 3×10 ¹⁸ cm ^-3 .

步骤8，MOS器件形成。Step 8, MOS devices are formed.

（8a）利用化学汽相淀积（CVD）方法，在700℃，在整个衬底上淀积一厚度为4nm的SiO₂层；(8a) Deposit a _SiO2 layer with a thickness of 4 nm on the entire substrate at 700 °C by chemical vapor deposition (CVD);

（8b）利用干法刻蚀工艺，蚀掉这层SiO₂，保留NMOS器件和PMOS器件栅极侧墙；(8b) using a dry etching process to etch away this layer of SiO ₂ , and retain the NMOS device and the gate sidewall of the PMOS device;

（8c）光刻NMOS器件有源区，在NMOS器件有源区进行N型离子注入，自对准生成NMOS器件的源、漏区和栅极；(8c) Lithograph the active area of the NMOS device, perform N-type ion implantation in the active area of the NMOS device, and self-align to generate the source, drain and gate of the NMOS device;

（8d）光刻PMOS器件有源区，在PMOS器件有源区进行N型离子注入，自对准生成PMOS器件的源、漏区和栅极。(8d) Lithograph the active region of the PMOS device, perform N-type ion implantation in the active region of the PMOS device, and self-align to generate the source, drain and gate of the PMOS device.

步骤9，构成BiCMOS集成电路。Step 9, forming a BiCMOS integrated circuit.

（9a）用化学汽相淀积（CVD）方法，在700℃，在整个衬底上淀积400nm厚的SiO₂层；(9a) Deposit a 400 nm thick _SiO2 layer on the entire substrate at 700 °C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属钛（Ti），合金，自对准形成金属硅化物，清洗表面多余的金属，形成金属接触；(9b) Photoetching the lead window, sputtering a layer of metal titanium (Ti) and alloy on the entire substrate, self-aligning to form a metal silicide, cleaning the excess metal on the surface, and forming a metal contact;

（9c）溅射金属，光刻引线，分别形成NMOS器件的源电极、栅电极、漏电极和PMOS器件的漏电极、源电极、栅电极，以及双极晶体管发射极、基极、集电极金属引线，最终MOS器件构成导电沟道为30nm的混合晶面平面应变BiCMOS集成器件及电路。(9c) Sputtering metal, photolithographic leads, respectively forming the source electrode, gate electrode, drain electrode of NMOS devices and the drain electrode, source electrode, gate electrode of PMOS devices, and the emitter, base, and collector metals of bipolar transistors Leads, the final MOS device constitutes a mixed crystal plane strain BiCMOS integrated device and circuit with a conductive channel of 30nm.

实施例3：制备45nm混合晶面平面应变BiCMOS集成器件及电路，具体步骤如下：Embodiment 3: Prepare 45nm mixed plane strain BiCMOS integrated device and circuit, the specific steps are as follows:

步骤1，SOI衬底材料制备。Step 1, SOI substrate material preparation.

（1a）选取N型掺杂浓度为5×10¹⁵cm^-3的Si片，晶面为（110），对其表面进行氧化，氧化层厚度为1μm，作为上层的基体材料，并在该基体材料中注入氢；(1a) Select a Si sheet with an N-type doping concentration of 5×10 ¹⁵ cm ^{-3 and} a crystal plane of (110), oxidize its surface, and the thickness of the oxide layer is 1 μm, as the upper substrate material, and in the substrate Hydrogen is injected into the material;

（1b）选取P型掺杂浓度为5×10¹⁵cm^-3的Si片，晶面为（100），对其表面进行氧化，氧化层厚度为1μm，作为下层的基体材料；(1b) Select a Si sheet with a P-type doping concentration of 5×10 ¹⁵ cm ^{-3 and} a crystal plane of (100), oxidize its surface, and the thickness of the oxide layer is 1 μm, as the base material of the lower layer;

（1c）采用化学机械抛光（CMP）工艺，分别对下层层和注入氢后的上层基体材料表面进行抛光处理；(1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

（1d）将抛光处理后的下层和上层基体材料表面SiO₂相对紧贴，置于超高真空环境中在480℃温度下实现键合；(1d) Put the SiO ₂ on the surface of the polished lower layer and the upper layer of the substrate relatively close to each other, and place them in an ultra-high vacuum environment to achieve bonding at a temperature of 480 °C;

（1e）将键合后的基片温度升高100℃，使上层基体材料在注入的氢处断裂，对上层基体材料多余的部分进行剥离，保留200nm的Si材料，并在该断裂表面进行化学机械抛光（CMP），形成SOI结构。(1e) Raise the temperature of the bonded substrate by 100°C to break the upper matrix material at the injected hydrogen, peel off the excess part of the upper matrix material, retain 200nm of Si material, and perform chemical treatment on the fractured surface Mechanical polishing (CMP) to form the SOI structure.

步骤2，隔离制备。Step 2, isolation preparation.

（2a）光刻双极器件有源区，外延生长一层掺杂浓度为1×10¹⁷cm^-3的Si层，厚度为200nm，作为集电区；(2a) In the active region of the photolithographic bipolar device, a Si layer with a doping concentration of 1×10 ¹⁷ cm ^-3 is grown epitaxially, with a thickness of 200 nm, as the collector region;

（2b）利用化学汽相淀积（CVD）方法，在800℃，在衬底表面淀积一层SiO₂；(2b) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

（2c）光刻隔离区，利用干法刻蚀工艺，在隔离区刻蚀出深度为3.5μm的深槽；(2c) In the photolithography isolation area, a deep groove with a depth of 3.5 μm is etched in the isolation area by using a dry etching process;

（2d）利用化学汽相淀积（CVD）方法，在800℃，在深槽内表面淀积SiO₂层，将深槽内表面全部覆盖；(2d) Using the chemical vapor deposition (CVD) method, at 800 ° C, deposit a SiO ₂ layer on the inner surface of the deep groove to completely cover the inner surface of the deep groove;

（2e）利用化学汽相淀积（CVD）方法，在800℃，在深槽内SiO₂层上再淀积一层SiN层，将深槽内表面全部覆盖；(2e) Using the chemical vapor deposition (CVD) method, at 800 ° C, deposit a layer of SiN layer on the SiO ₂ layer in the deep groove to completely cover the inner surface of the deep groove;

（2f）利用化学汽相淀积（CVD）方法，在800℃，在深槽内填充SiO₂，利用化学机械抛光（CMP）方法，除去多余的氧化层，形成深槽隔离。(2f) Using the chemical vapor deposition (CVD) method, at 800°C, fill the deep groove with SiO ₂ , and use the chemical mechanical polishing (CMP) method to remove the redundant oxide layer to form the deep groove isolation.

步骤3，双极器件制备。Step 3, bipolar device preparation.

（3a）光刻集电区接触区，对集电区进行N型杂质的注入，并在950℃，退火30min激活杂质，形成掺杂浓度为1×10²⁰cm^-3的重掺杂集电极；(3a) Photoetching the contact area of the collector region, implanting N-type impurities into the collector region, and annealing at 950°C for 30 minutes to activate the impurities to form a heavily doped collector with a doping concentration of 1×10 ²⁰ cm ^-3 ;

（3b）在衬底表面热氧化一SiO₂层，光刻基区，对基区进行P型杂质的注入，并在950℃，退火30min激活杂质，形成掺杂浓度为5×10¹⁸cm^-3的基区；(3b) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photoresist the base area, implant P-type impurities into the base area, and activate the impurities by annealing at 950°C for 30 minutes to form a doping concentration of 5×10 ¹⁸ cm ^{- 3} base regions;

（3c）在衬底表面热氧化一SiO₂层，光刻发射区，对衬底进行N型杂质的注入，并在950℃，退火30min激活杂质，成掺杂浓度为5×10²⁰cm^-3的重掺杂发射区，构成双极晶体管；(3c) Thermally oxidize a SiO ₂ layer on the surface of the substrate, photolithography the emitter region, implant N-type impurities into the substrate, and anneal at 950°C for 30 minutes to activate the impurities, resulting in a doping concentration of 5×10 ²⁰ cm ^{- 3} 's heavily doped emitter region, forming a bipolar transistor;

（3d）在衬底表面利用化学汽相淀积（CVD）的方法，在800℃，淀积一SiO₂层。(3d) Deposit a SiO ₂ layer on the surface of the substrate by chemical vapor deposition (CVD) at 800°C.

步骤4，NMOS器件区制备。Step 4, preparation of the NMOS device area.

（4a）利用化学汽相淀积（CVD）方法，在800℃，在衬底表面淀积一层SiO₂；(4a) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

（4b）光刻NMOS器件有源区，利用干法刻蚀工艺，在NMOS器件有源区，刻蚀出深度为2.9μm的深槽，将氧化层刻透；(4b) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 2.9 μm in the active area of the NMOS device, and etching the oxide layer through;

（4c）利用化学汽相淀积（CVD）的方法，在750℃，在深槽内沿（100）晶面生长一层厚度为400nm的P型Si缓冲层，掺杂浓度为5×10¹⁵cm^-3；(4c) Using chemical vapor deposition (CVD), grow a P-type Si buffer layer with a thickness of 400nm along the (100) crystal plane in the deep trench at 750°C, with a doping concentration of 5×10 ¹⁵ cm ^-3 ;

（4d）利用化学汽相淀积（CVD）的方法，在750℃，P型缓冲层上生长一层厚度为2.1μm的P型Ge组分梯形分布的SiGe，底部Ge组分为0%，顶部为25%，掺杂浓度为5×10¹⁵cm^-3；(4d) Using chemical vapor deposition (CVD), grow a layer of SiGe with a thickness of 2.1 μm on the P-type buffer layer at 750 °C, with a trapezoidal distribution of P-type Ge composition, and the Ge composition at the bottom is 0%, The top is 25%, and the doping concentration is 5×10 ¹⁵ cm ^-3 ;

（4e）利用化学汽相淀积（CVD）的方法，在750℃，在Ge组分梯形分布的SiGe层上生长一层厚度为400nm的P型SiGe层，Ge组分为25％，掺杂浓度为5×10¹⁷cm^-3；(4e) Using chemical vapor deposition (CVD), grow a P-type SiGe layer with a thickness of 400nm on the SiGe layer with a trapezoidal distribution of Ge composition at 750°C. The Ge composition is 25%, doped The concentration is 5×10 ¹⁷ cm ^-3 ;

（4f）利用化学汽相淀积（CVD）方法，在750℃，在SiGe层上生长一层厚度为8nm的应变Si层，掺杂浓度为5×10¹⁷cm^-3，作为NMOS器件的沟道；(4f) Using the chemical vapor deposition (CVD) method, at 750 ° C, grow a layer of strained Si layer with a thickness of 8 nm on the SiGe layer, with a doping concentration of 5×10 ¹⁷ cm ^-3 , as the channel of the NMOS device road;

（4g）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(4g) Etch away the SiO ₂ layer on the surface by wet etching.

步骤5，PMOS器件区制备。Step 5, preparing the PMOS device area.

（5a）利用化学汽相淀积化学汽相淀积（CVD）方法，在800℃，在衬底表面淀积一层SiO₂；(5a) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition chemical vapor deposition (CVD);

（5b）光刻PMOS器件有源区，利用化学汽相淀积（CVD）的方法，在750℃，在PMOS器件有源区沿（110）晶面生长一层厚度为400nm的N型Si缓冲层，掺杂浓度为5×1017cm^-3；(5b) Lithograph the active area of the PMOS device, using the chemical vapor deposition (CVD) method, at 750 ° C, grow a layer of N-type Si buffer with a thickness of 400 nm along the (110) crystal plane in the active area of the PMOS device layer, the doping concentration is 5×1017cm ^-3 ;

（5c）利用化学汽相淀积（CVD）的方法，在750℃，在Si缓冲层上生长一层厚度为8nm的P型SiGe层，Ge组分为25％，掺杂浓度为5×10¹⁷cm^-3；(5c) Using chemical vapor deposition (CVD), grow a P-type SiGe layer with a thickness of 8 nm on the Si buffer layer at 750 °C, with a Ge composition of 25% and a doping concentration of 5×10 ¹⁷ cm ^-3 ;

（5d）利用化学汽相淀积（CVD）的方法，在750℃，在应变SiGe层上生长一层厚度为3nm的本征弛豫Si帽层，形成PMOS器件有源区；(5d) growing an intrinsically relaxed Si cap layer with a thickness of 3nm on the strained SiGe layer at 750°C by chemical vapor deposition (CVD) to form the active region of the PMOS device;

（5e）利用湿法腐蚀，刻蚀掉表面的层SiO₂。(5e) using wet etching to etch away the SiO ₂ layer on the surface.

步骤6，浅槽隔离制备。Step 6, shallow trench isolation preparation.

（6a）光刻场氧区，利用干法刻蚀工艺，在隔离区刻蚀出深度为0.5μm的浅槽；(6a) In the oxygen area of the photolithography field, a shallow groove with a depth of 0.5 μm is etched in the isolation area by using a dry etching process;

（6b）利用化学汽相淀积（CVD）方法，在800℃，在浅槽内填充SiO₂；(6b) Fill the shallow groove with SiO ₂ at 800°C by chemical vapor deposition (CVD);

（6c）用化学机械抛光（CMP）方法，除去多余的氧化层，形成浅槽隔离。(6c) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

步骤7，MOS器件栅极与轻掺杂源漏（LDD）制备。Step 7, the gate and lightly doped source and drain (LDD) of the MOS device are prepared.

（7a）在400℃，在有源区上用原子层化学汽相淀积（ALCVD）的方法淀积HfO₂层，厚度为10nm，作为NMOS器件和PMOS器件的栅介质；(7a) At 400°C, deposit _an HfO2 layer with a thickness of 10nm on the active region by atomic layer chemical vapor deposition (ALCVD), as the gate dielectric of NMOS devices and PMOS devices;

（7b）利用化学汽相淀积（CVD）方法，在750℃，在栅介质层上淀积一层本征的Poly-SiGe，厚度为500nm，Ge组分为30%；(7b) Deposit a layer of intrinsic Poly-SiGe with a thickness of 500nm and a Ge composition of 30% on the gate dielectric layer at 750°C by chemical vapor deposition (CVD);

（7c）光刻MOS器件栅介质与栅多晶，形成栅极；(7c) Lithographic MOS device gate dielectric and gate polysilicon to form the gate;

（7d）光刻NMOS器件有源区，对NMOS器件有源区进行N型离子注入，形成掺杂浓度为5×10¹⁸cm^-3的N型轻掺杂源漏结构（N-LDD）区域；(7d) Lithographically etches the active region of the NMOS device, and performs N-type ion implantation on the active region of the NMOS device to form an N-type lightly doped source-drain structure (N-LDD) region with a doping concentration of 5×10 ¹⁸ cm ^-3 ;

（7e）光刻PMOS器件有源区，对PMOS器件有源区进行P型离子注入，形成掺杂浓度为5×10¹⁸cm^-3的P型轻掺杂源漏结构（P-LDD）区域。(7e) Lithograph the active region of the PMOS device, perform P-type ion implantation on the active region of the PMOS device, and form a P-type lightly doped source-drain structure (P-LDD) region with a doping concentration of 5×10 ¹⁸ cm ^-3 .

步骤8，MOS器件形成。Step 8, MOS devices are formed.

（8a）利用化学汽相淀积（CVD）方法，在800℃，在整个衬底上淀积一厚度为5nm的SiO₂层；(8a) Deposit a _SiO2 layer with a thickness of 5 nm on the entire substrate at 800 °C by chemical vapor deposition (CVD);

（8b）利用干法刻蚀工艺，蚀掉这层SiO₂，保留NMOS器件和PMOS器件栅极侧墙；(8b) using a dry etching process to etch away this layer of SiO ₂ , and retain the NMOS device and the gate sidewall of the PMOS device;

（8c）光刻NMOS器件有源区，在NMOS器件有源区进行N型离子注入，自对准生成NMOS器件的源、漏区和栅极；(8c) Lithograph the active area of the NMOS device, perform N-type ion implantation in the active area of the NMOS device, and self-align to generate the source, drain and gate of the NMOS device;

（8d）光刻PMOS器件有源区，在PMOS器件有源区进行N型离子注入，自对准生成PMOS器件的源、漏区和栅极。(8d) Lithograph the active region of the PMOS device, perform N-type ion implantation in the active region of the PMOS device, and self-align to generate the source, drain and gate of the PMOS device.

步骤9，构成BiCMOS集成电路。Step 9, forming a BiCMOS integrated circuit.

（9a）用化学汽相淀积（CVD）方法，在800℃，在整个衬底上淀积500nm厚的SiO₂层；(9a) Deposit a 500 nm thick _SiO2 layer on the entire substrate at 800 °C by chemical vapor deposition (CVD);

（9b）光刻引线窗口，在整个衬底上溅射一层金属钛（Ti），合金，自对准形成金属硅化物，清洗表面多余的金属，形成金属接触；(9b) Photoetching the lead window, sputtering a layer of metal titanium (Ti) and alloy on the entire substrate, self-aligning to form a metal silicide, cleaning the excess metal on the surface, and forming a metal contact;

（9c）溅射金属，光刻引线，分别形成NMOS器件的源电极、栅电极、漏电极和PMOS器件的漏电极、源电极、栅电极，以及双极晶体管发射极、基极、集电极金属引线，最终MOS器件构成导电沟道为45nm的混合晶面平面应变BiCMOS集成器件及电路。(9c) Sputtering metal, photolithographic leads, respectively forming the source electrode, gate electrode, drain electrode of NMOS devices and the drain electrode, source electrode, gate electrode of PMOS devices, and the emitter, base, and collector metals of bipolar transistors Leads, the final MOS device constitutes a mixed crystal plane strain BiCMOS integrated device and circuit with a conductive channel of 45nm.

本发明实施例提供的混合晶面应变混合晶面平面应变BiCMOS集成器件及制备方法具有如下优点：The mixed crystal plane strain mixed crystal plane strain BiCMOS integrated device and the preparation method provided by the embodiment of the present invention have the following advantages:

1．本发明制备的混合晶面平面应变BiCMOS集成器件及电路中采用了SOI衬底，降低了器件与电路的功耗，提高了器件与电路的可靠性；1. The mixed crystal planar strain BiCMOS integrated device and the circuit prepared by the present invention adopt the SOI substrate, which reduces the power consumption of the device and the circuit, and improves the reliability of the device and the circuit;

2．本发明制备的混合晶面平面应变BiCMOS集成器件及电路采用了混合晶面衬底技术，即在同一个衬底片上分布有（100）和（110）这两种晶面，在（100）晶面上电子迁移率最高，而对于空穴，（110）晶面上最高，为（100）晶面上的2.5倍，本发明结合了载流子迁移率同时达到最高的两种晶面，能在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率；2. The mixed crystal plane strain BiCMOS integrated device and circuit prepared by the present invention adopt the mixed crystal plane substrate technology, that is, two crystal planes (100) and (110) are distributed on the same substrate, and the (100) crystal plane The highest electron mobility on the plane, and for holes, the (110) crystal plane is the highest, which is 2.5 times that of the (100) crystal plane. The present invention combines the two crystal planes with the highest carrier mobility at the same time, and can Improving the carrier mobility of one type of device without reducing the carrier mobility of another type of device;

3．本发明制备的混合晶面平面应变BiCMOS集成器件及电路，采用选择性外延技术，分别在NMOS器件和PMOS器件有源区选择性生长张应变Si和压应变SiGe材料，使NMOS器件和PMOS器件频率性能和电流驱动能力等电学性能能够获得同时提升，从而CMOS器件与集成电路性能获得了增强；3. The mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention adopt selective epitaxy technology to selectively grow tensile strain Si and compressive strain SiGe materials in the active regions of NMOS devices and PMOS devices respectively, so that the frequency of NMOS devices and PMOS devices Electrical properties such as performance and current drive capability can be improved simultaneously, thereby enhancing the performance of CMOS devices and integrated circuits;

4．本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中MOS器件采用了高K值的HfO₂作为栅介质，提高了MOS器件的栅控能力，增强了NMOS和PMOS器件的电学性能；4. The mixed crystal planar strain BiCMOS integrated device and the circuit structure prepared by the present invention adopt _HfO2 with a high K value as the gate dielectric, which improves the gate control ability of the MOS device and enhances the electrical performance of the NMOS and PMOS devices;

5．本发明制备的混合晶面平面应变BiCMOS集成器件及电路结构中PMOS器件为量子阱器件，即应变SiGe沟道层处于Si帽层和体Si层之间，与表面沟道器件相比，该器件能有效地降低沟道界面散射，提高了器件电学特性；同时，量子阱可以使热电子注入栅介质中的问题得到改善，增加了器件和电路的可靠性；5. The PMOS device in the mixed plane strain BiCMOS integrated device and circuit structure prepared by the present invention is a quantum well device, that is, the strained SiGe channel layer is between the Si cap layer and the bulk Si layer. Compared with the surface channel device, the device has It can effectively reduce channel interface scattering and improve the electrical characteristics of the device; at the same time, quantum wells can improve the problem of hot electron injection into the gate dielectric, increasing the reliability of devices and circuits;

6．本发明制备混合晶面平面应变BiCMOS集成器件及电路工艺中，采用Poly-SiGe材料作为栅电极，其功函数随Ge组分的变化而变化，通过调节Poly-SiGe中Ge组分，实现CMOS阈值电压可连续调整，减少了工艺步骤，降低了工艺难度；6. In the preparation of the mixed crystal planar strain BiCMOS integrated device and the circuit technology of the present invention, the Poly-SiGe material is used as the gate electrode, and its work function changes with the change of the Ge composition, and the CMOS threshold is realized by adjusting the Ge composition in the Poly-SiGe The voltage can be adjusted continuously, which reduces the process steps and process difficulty;

7．本发明制备的混合晶面平面应变BiCMOS集成器件及电路过程中涉及的最高温度为800℃，低于引起应变Si沟道应力弛豫的工艺温度，因此该制备方法能有效地保持应变Si沟道应力，提高集成电路的性能；7. The highest temperature involved in the process of the mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention is 800°C, which is lower than the process temperature that causes stress relaxation of the strained Si channel, so the preparation method can effectively maintain the strained Si channel Stress, improve the performance of integrated circuits;

8.本发明制备的混合晶面平面应变BiCMOS集成器件及电路中，双极器件采用SOI衬底的集电区厚度较传统器件薄，因此，该器件存在集电区横向扩展效应，并能够在集电区形成二维电场，从而提高了该器件的反向击穿电压和Early电压，在相同的击穿特性下，具有比传统器件更优异的特征频率。以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。8. In the mixed crystal planar strain BiCMOS integrated device and circuit prepared by the present invention, the thickness of the collector region of the SOI substrate used in the bipolar device is thinner than that of the traditional device. Therefore, the device has a collector region lateral extension effect, and can be used in The collector area forms a two-dimensional electric field, thereby improving the reverse breakdown voltage and early voltage of the device, and has a better characteristic frequency than traditional devices under the same breakdown characteristics. The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.