CN103035290A - EEPROM (Electrically Erasable Programmable Read-Only Memory) circuit, data readout method and nonvolatile memory - Google Patents
- ️Wed Apr 10 2013
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- CN103035290A CN103035290A CN2012105110189A CN201210511018A CN103035290A CN 103035290 A CN103035290 A CN 103035290A CN 2012105110189 A CN2012105110189 A CN 2012105110189A CN 201210511018 A CN201210511018 A CN 201210511018A CN 103035290 A CN103035290 A CN 103035290A Authority
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- 238000002679 ablation Methods 0.000 description 1
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Abstract
The invention provides an EEPROM (Electrically Erasable Programmable Read-Only Memory) circuit. The EEPROM circuit comprises a memory unit array, an erasing circuit and a readout circuit, wherein the readout circuit comprises a reference unit readout circuit and a data unit readout circuit; a reference unit is controlled by the erasing circuit to write the preset data, and the readout current of a data unit and the output current of the reference unit readout circuit are compared, so that the data memorized in the data unit is obtained. By adopting the EEPROM circuit provided by the invention, the influences on the power voltage caused by external environments such as parasitic parameters and process variation can be effectively removed, and thus the problems of the fluctuation of the readout time change and the phenomenon of error readout can be avoided.
Description
Technical field
The present invention relates to memory area, in particular, relate to a kind of eeprom circuit, method for reading data and nonvolatile memory.
Background technology
Along with the development of science and technology, storer is widely used.The kind of storer is a lot, and wherein, nonvolatile semiconductor memory relies on the characteristic of its data storage, is widely used.
See also Fig. 1, be the structural drawing of minimum memory unit in the nonvolatile semiconductor memory, this
storage unit10 comprises selects
transistor11 and floating boom tunnel oxidation layer transistor 12.Wherein, select the grid
connective word line21 of
transistor11, drain electrode or source electrode connect
bit line23; The transistorized control gate of floating boom tunnel oxidation layer connects
erasable end23.
Eeprom circuit comprises
memory cell array20,
column decode circuitry31,
column selection transistor32,
column decoder33 and
reading circuit34 as shown in Figure 3 in the prior art.Wherein,
memory cell array20 by m capable * rectangular array that the
storage unit10 of n row forms.
Column decode circuitry31 is connected with each
word line21 of
memory cell array20, for the row at
storage unit10 places of selecting to read.In like manner,
array decoding circuit33 is specially
column selection transistor32 conductings with these row, so that the
column selection transistor32 added operating voltage VDD of these row are delivered to all
storage unit10 of these row for the row at
storage unit10 places of selecting to read.Therefore,
column decode circuitry31 and
array decoding circuit33 have determined
storage unit10 positions that need to read jointly.
Reading circuit34 need to be compared the reading current of the storage unit that detects with a preset reference electric current, usually, this preset reference current value is set to half of reading current value of storage unit.
The inventor finds, in the prior art, reference current is fixed value, but because there is the difference of circuit structure and layout in storage unit, and the impact of the external environment such as the parasitic parameter on the line, process deviation, the value that causes the reference current set is not half of actual read current value of storage unit, can not meet design requirement, tend to cause change fluctuation greatly readout time, even phenomenon occurs misreading out.
Summary of the invention
In view of this, the invention provides a kind of eeprom circuit and nonvolatile memory, solved the problem that variation was fluctuateed greatly, misread out readout time in the prior art.
For achieving the above object, the invention provides following technical scheme:
A kind of eeprom circuit comprises: memory cell array, erasable circuit and reading circuit, and the comprising of described memory cell array: set of reference cells and data sheet tuple,
Described set of reference cells comprises the first reference unit and the second reference unit, and described data sheet tuple comprises at least one data cell;
Each described data cell all is connected to predetermined word line or bit line with described set of reference cells;
Described erasable circuit links to each other with every row in the described memory cell array, is used for synchronously controlling described the first reference unit and writing the first preset data when erasable in that the data unit is carried out, and controls described the second reference unit and writes the second preset data;
Described reading circuit comprises reference unit reading circuit and data cell reading circuit, wherein, described reference unit reading circuit gathers the first reading current of described the first reference unit and the second reading current of described the second reference unit, and export one and become the output current of preset ratio with described the second reading current with described the first reading current, described data cell reading circuit is used for gathering the reading current of the described data cell of every row, and the output current of the reading current of the described data cell of more every row and described reference unit reading circuit, obtain the data of the storage of described data cell.
Preferably, described reference current reading circuit comprises the first switching tube, second switch pipe and current mirror,
The grid of described the first switching tube links to each other with the grid of described second switch pipe, and public connecting end links to each other with external sense wire;
The source electrode of described the first switching tube links to each other with the transistorized drain electrode of selection in described the first reference unit, and the source electrode of described second switch pipe links to each other with the transistorized drain electrode of selection in described the second reference unit;
The input end of described current mirror links to each other with the drain electrode of described the first switching tube and the drain electrode of described second switch pipe respectively, and output terminal links to each other with described data cell reading circuit.
Preferably, described data cell reading circuit comprises: the 7th switching tube and impact damper;
The grid of described the 7th switching tube links to each other, drains with the grid of described second switch pipe and links to each other with the output terminal of described reference unit reading circuit and the input end of impact damper respectively, and the output terminal of described impact damper is as the output terminal of described data cell reading circuit.
Preferably, the output current of described current mirror is 1/2nd of input current.
Preferably, described the first switching tube, described second switch pipe and described the 7th switching tube are the N-type metal-oxide-semiconductor.
Preferably, described the first preset data is the anti-data of described the second preset data, and when described the first preset data was 0, described the second preset data was 1; When described the first preset data was 1, described the second preset data was 0.
Preferably, when the reading current of described data cell during greater than the output current of described reference unit reading circuit, the data of described data cell storage are 0;
When the reading current of described data cell during less than the output current of described reference unit reading circuit, the data of described data cell storage are 1.
A kind of method for reading data is applied to eeprom circuit, comprising:
Synchronously control the first reference unit and write the first preset data when erasable in that the data unit is carried out, control the second reference unit and write the second preset data;
Gather the first reading current of described the first reference unit and the second reading current of described the second reference unit, and export one and become the output current of preset ratio with described the second reading current with described the first reading current;
The reading current of more described data cell and described output current obtain the data of the storage of described data cell.
Preferably, described output current is 1/2nd of described the first reading current and described the second reading current sum.
A kind of nonvolatile memory comprises the described eeprom circuit of above-mentioned any one.
Via above-mentioned technical scheme as can be known, compared with prior art, the invention provides a kind of eeprom circuit, comprise: memory cell array, erasable circuit and reading circuit, this reading circuit comprises reference unit reading circuit and data cell reading circuit, write preset data by erasable circuit control reference unit, and the size of the output current of the reading current of the data cell by more every row and reference unit reading circuit, obtain the data of the storage of described data cell.Adopt eeprom circuit provided by the invention, can effectively eliminate the external environments such as parasitic parameter, process deviation to the impact of supply voltage, and then avoided the fluctuation that changes readout time and misread out the problem such as phenomenon.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is embodiments of the invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to the accompanying drawing that provides other accompanying drawing.
Fig. 1 is the synoptic diagram of storage unit in the eeprom circuit;
Fig. 2 is the structural representation of eeprom circuit in the prior art;
Fig. 3 is the transistorized structural representation of floating boom tunnel oxidation layer in the storage unit in the eeprom circuit;
Fig. 4 is the structural representation of a kind of eeprom circuit provided by the invention;
The specific implementation circuit diagram of a kind of eeprom circuit that Fig. 5 provides for the embodiment of the invention one;
The process flow diagram of a kind of method for reading data that Fig. 6 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The invention provides a kind of eeprom circuit, comprise: memory cell array, erasable circuit and reading circuit, this reading circuit comprises reference unit reading circuit and data cell reading circuit, write preset data by erasable circuit control reference unit, and the size of the output current of the reading current by the comparing data unit and reference unit reading circuit, obtain the data of the storage of described data cell.Adopt eeprom circuit provided by the invention, can effectively eliminate the external environments such as parasitic parameter, process deviation to the impact of supply voltage, and then avoided the fluctuation that changes readout time and misread out the problem such as phenomenon.
Embodiment one
See also accompanying drawing 3, structure and the principle of work of storage unit in the eeprom circuit briefly introduced, wherein, floating boom tunnel
oxidation layer transistor12 comprises
polysilicon gate123a, the 123b of
source electrode121,
drain electrode122 and two superimposed.Wherein, lower-layer gate is floating
boom123a very, with external insulation, is used for stored charge.The upper strata grid is
control gate123b, has extension line and connects erasable end 23.Between floating
boom123a and
drain electrode122, be provided with the thin tunnel oxide of one
deck124.
According to the electric charge situation on the floating
boom123a, can define the type of described storage unit stores data, as: without electric charge, the data that then define this cell stores are " 0 " in floating boom
123a.In floating boom123a, there is electric charge then to represent to store data and is " 1 ".Need to prove that the storage unit of different EEPROM may be just the opposite to the definition of storage data, as: without electric charge, the data that then define this cell stores are " 1 " in floating boom 123a.In floating
boom123a, there is electric charge then to represent to store data and is " 0 ", at this, do not do too much restriction.
Action type and the principle of described storage unit are as follows:
(for example+16V), because the effect of electric field force,
electronics122 passes
tunnel oxide124 and arrives floating
boom123a and charge from draining, and is erase operation when
control gate123b adds positive high voltage with respect to
drain electrode122.
(for example+16V), then electronics passes
tunnel oxide124 from floating
boom123a and arrives
drain electrode122, makes floating
boom123a discharge, is programming operation when
drain electrode122 adds positive high voltage with respect to
control gate123b.
When
control gate123b with respect to
drain electrode122 add positive low-voltage (for example+2V) time, if store electric charge among the
floating boom123a,
source electrode121 and drain between 122 can't conducting then, drain 122 end no currents or electric current are very little, expression storage data " 1 "; If stored charge not among the
floating boom123a, then
source electrode121 and the conducting between 122 that drains, 122 ends that drain have larger electric current, and expression storage data " 0 " are read operation.The electric current of
drain electrode122 is called reading current during read operation.
Now in conjunction with Fig. 4, structural drawing for a kind of eeprom circuit provided by the invention, comprise: memory cell array, erasable circuit 103 and reading circuit 104, wherein, memory cell array comprises: set of reference cells 102 and data sheet tuple 101, wherein, data sheet tuple 101 comprises at least one
data cell10, and described set of reference cells 102 comprises the first reference unit 10a and the second reference unit 10b.
Here need to prove, in eeprom circuit provided by the invention, set of reference cells can be arranged in every delegation of memory cell array, it is the corresponding set of reference cells of delegation, also can be for a set of reference cells only be set in the whole memory cell array, namely multirow shares a set of reference cells, can also be for a plurality of set of reference cells are set in whole memory cell array, be the corresponding set of reference cells of part multirow, the corresponding set of reference cells of part delegation.
Now the every delegation in the memory cell array is provided with a set of reference cells as example, and annexation and the function of each ingredient in the eeprom circuit provided by the invention is introduced:
Each
data cell10 all is connected to predetermined word line or bit line with set of reference cells 102.
What need here to explain is: the grid of selector switch pipe links to each other with grid with selector switch pipe in the reference unit of delegation in each data cell, and receives same word line WL, such as the annexation among Fig. 5.Here, select transistor T 3 and floating boom tunnel oxidation layer transistor T 5 to consist of the first reference unit, select transistor T 4 and floating boom tunnel oxidation layer transistor T 6 to consist of the second reference unit, select transistor T 8 and floating boom tunnel oxidation layer transistor T 9 composition data unit.
Erasable circuit 103 links to each other with every row in the memory cell array, be used for being controlled at the data unit is carried out when erasable, synchronously control described the first reference unit and write the first preset data, control described the second reference unit and write the second preset data, wherein, described the first preset data and described the second preset data are complementary data, as, when the first preset data was " 0 ", then the second preset data is " 1 ", and was like that.Specific implementation step concrete operations of described ablation process that can vide infra, but be not limited to this step, any can realize the operation of reference unit data writing all passable.
Described reading circuit links to each other with every row in the described memory cell array, comprise reference
unit reading circuit1041 and data
cell reading circuit1042, wherein, described reference
unit reading circuit1041 gathers the first reading current Icell_0 of described the
first reference unit1051 and the second reading current Icell_1 of described the
second reference unit1052, and export one and become the output current I_mirror of preset ratio with described the second reading current Icell_1 with described the first reading current Icell_0, described data
cell reading circuit1042 is used for gathering the reading current I_cell_data of described data cell, by the reading current of more described data
cell reading circuit1042 and the output current of described reference
unit reading circuit1041, obtain the data of the storage of described data cell.
The invention provides a kind of preferred embodiment, as shown in Figure 5, wherein, transistor T 5, T6 and T9 are the floating boom transistors of N-type, are used for the storage data, and
transistor T1, T2, T3, T4, T7 and T8 are the N-type field effect transistor, play the effect of switch, those skilled in the art play the transistor of on-off action as can be known, can also be the field effect transistor of other types.Reference unit reading circuit among Fig. 4 comprises the first
switch transistor T1, second switch pipe T2 and current mirror (being made of
switch transistor T10 and T11).Data
cell reading circuit1042 comprises the 7th switching tube T7 and output buffer BUF.
Wherein, the concrete annexation of this reference unit reading circuit is:
The grid of the first
switch transistor T1 links to each other with the grid of second switch pipe T2, and public connecting end links to each other with external sense wire READ.
The source electrode of described the first
switch transistor T1 links to each other with the drain electrode of selection transistor T 3 in described the first reference unit, and the source electrode of described second switch pipe T2 links to each other with the drain electrode of selection transistor T 4 in described the second reference unit.
The input end of described current mirror (drain electrode of transistor T 10) links to each other with the drain electrode of described the first
switch transistor T1 and the drain electrode of described second switch pipe T2 respectively, and output terminal (drain electrode of transistor T 11) links to each other with the input end of data
cell reading circuit1042.
The concrete annexation of notebook data unit reading circuit is:
The grid of described the 7th switching tube T7 links to each other with the grid of described second switch pipe T2, and the drain electrode of described the 7th switching tube T7 links to each other with the output terminal of reference
unit reading circuit1041 and the input end of output buffer BUF respectively.The output terminal of described output buffer BUF is as the output terminal of described data
cell reading circuit1042.
In the present embodiment, selecting current mirror is that output current is the current mirror of input current 1/2nd, and namely the raceway groove length breadth ratio of the field effect transistor of input end is the twice of raceway groove length breadth ratio of the field effect transistor of output terminal in the current mirror.
By reference to the accompanying drawings 5, the principle of work of the eeprom circuit that present embodiment is provided describes.Wherein, every row comprises a set of reference cells and at least one data cell in this circuit, each set of reference cells comprises two reference units, in order to draw conveniently, in Fig. 5, only drawn a data unit 106(by selecting transistor T 8 and floating boom tunnel oxidation layer transistor T 9 to consist of), wherein, select transistor T 3 and floating boom tunnel oxidation layer transistor T 5 to consist of the
first reference unit1051, select transistor T 4 and floating boom tunnel oxidation layer transistor T 6 to consist of the
second reference unit1052.
In the present embodiment, the reference arm that the reference arm that
transistor T1, transistor T 3 and transistor T 5 form and number form take transistor T 2, T4 and T6 is as two complementary branch roads, wherein, can define the reference arm record data " 1 " that
transistor T1, transistor T 3 and transistor T 5 form, with the reference arm record data " 0 " of transistor T 2, T4 and T6 composition.Also can be the reference arm record data " 0 " of
transistor T1, transistor T 3 and transistor T 5 compositions, with the reference arm record data " 1 " that transistor T 2, T4 and T6 form, namely need only two branch roads and form complementary.In the present embodiment, in the mode of the first record data mode as example, the principle of work of the eeprom circuit that by reference to the accompanying drawings present embodiment is provided is introduced.Wherein, the branch road of transistor T 7, T8 and T9 composition is used for the record True Data.
Because in the present embodiment, the channel width-over-length ratio of setting
transistor T11 in the current mirror is half of T10, then is half of electric current sum of two reference arm, i.e. I_mirror=(I_cell_0+I_cell_1 from the image current of T11 output)/2.
Apparently, because floating boom transistor T 9 all is connected to identical gate control lines CG in the floating boom transistor T 6 in the first reference unit in floating boom transistor T 5 and the second reference unit and the data cell, and bit line BL is separate, then the eeprom circuit that provides of present embodiment is when carrying out data writing to storage array, can only carry out first erase operation, carry out again programming operation.The principle of work of the eeprom circuit of present embodiment is as follows:
The principle of work that the below introduces is divided into data and writes (claiming again " erasable ") procedure division and data read process part, and wherein, data were write procedure division and are specially two processes of " wiping "+" programming ".
Carry out at first, first erasing move:
1, T2 and T7 are read in the control cut-off, send into the 0V low level toward sense wire READ; Send into the 0V low level at the bit line of each storage element, that is: BL_ref_0=0V, BL_ref_1=0V, BL_data=0V.
WL applies the 16V high pressure at the word line.Here need to prove that in fact, the high pressure that applies 5V at word line WL just can be chosen each storage unit, but the inventor considers drain voltage with field effect transistor T5, the T6 of storage unit and the T9 bit-line voltage that furthers, so apply the 16V high pressure.
Apply the 15.5V high pressure at gate control lines CG.And the source electrode of each storage unit is connected to low level, i.e. source signal line GNDF=0V.Apparently; these storage unit can be directly connected to ground signalling; or respectively by being connected to source signal line GNDF behind some switching transistors; those skilled in the art are in foundation thought of the present invention; all will change in specific embodiments and applications, but all within protection scope of the present invention.
Erase process continues about 1ms, and the read current of all storage unit T5, T6 and T9 is I_cell_1 after having wiped.
Then, the action of programming:
Send into the 0V low level at sense wire READ, word line WL sends into the 16V high pressure.Apply 0V low pressure on the gate control lines CG, the source signal line GNDF that storage unit connects is set to high-impedance state (highimpedance, hi-z).
Because reference unit T6 wants data writing " 0 ", then apply the 15.5V high-voltage pulse at bit line BL_ref_0, and reference unit T5 wants data writing " 1 ", does not then need to change the state after wiping, and applies 0V low pressure or is arranged to high-impedance state at bit line BL_ref_0.
Data cell applies different voltage according to the difference of data writing at bit line, when needs data writing " 0 ", then apply the 15.5V high-voltage pulse at bit line BL_data, when needs data writing " 1 ", the state of keeping after wiping gets final product, and applies 0V low pressure or is arranged to high-impedance state at bit line BL_data.
Programming process continues about 1ms, and the read current of reference unit T6 is I_cell_0 after having programmed, and the read current of reference unit T5 is I_cell_1.The electric current of data cell T9 is then according to the difference of data writing and difference, and when data writing was " 0 ", the electric current of T9 was I_cell_0, and when data writing was " 1 ", the electric current of T9 was I_cell_1.
The principle of work of reading out data is as follows, and concrete steps are:
At first turn-on transistor T1, T2 and T7 send into for example 5V of operating voltage VDD(at sense wire READ); Owing to do not need to wipe and programming operation, bit line all is set to high-impedance state, i.e. BL_ref_0=Hi-z, BL_ref_1=Hi-z, BL_data=Hi-z.
Then, this row that gating will read is also sent into operating voltage VDD toward word line WL.The control grid CG of storage unit only need to send into the voltage of 1.5V, and source signal end GNDF links ground connection, GNDF=0V
Apparently, the electric current of the T6 that flows through this moment is larger, and the electric current of the T5 that flows through is less, and I_cell_0 is arranged〉I_cell_1.
So, because mirror image effect and the size thereof of T10 and T11 are different, I_mirror=(I_cell_0+I_cell_1 is arranged)/2, when the data among the data cell T9 are " 0 ", flow through transistor T 9 electric current with the storage data " 0 " reference unit identical, be I_cell_data=I_cell_0, so at node P place, the electric current △ I that flows to output signal end DOUT is:
△I=I_mirror-I_cell_data
=（I_cell_0+I_cell_1）/2-I_cell_0
=（I_cell_1-I_cell_0）/2<0，
As seen the direction of electric current △ I is that input end A from output buffer BUF flows to data cell T9, among Fig. 5, in the dotted line frame, drawn an equivalent parasitic capacitances C, because the effect of discharge, the voltage of stray capacitance C is dragged down, and input end A can be to output signal end DOUT output low level;
On the contrary, when the data among the data cell T9 were " 1 ", the electric current of the transistor T 9 of flowing through was identical with the reference unit of storage data " 1 ", i.e. I_cell_data=I_cell_1, and so at node P place, the electric current △ I that flows to output signal end DOUT is:
△I=I_mirror-I_cell_data
=（I_cell_0+I_cell_1）/2-I_cell_1
=（I_cell_0-I_cell_1）/2>0,
As seen sense of current is the input end A that flows to output buffer BUF from
transistor T11, because the effect of charging, the voltage of stray capacitance C is elevated, and input end A can be to output signal end DOUT output high level.
As seen, because during the data in the reading out data unit, reference current is to be produced by a pair of reference unit identical and synchronously erasable with the structure of data cell, this reference current is with respect to the read current real-time update of data cell, can follow the tracks of operating voltage and electric current environmental change, threshold drift after simultaneously also can the tracking data unit repeating to wipe/write, adopt eeprom circuit provided by the invention, can effectively eliminate parasitic parameter, the external environments such as process deviation are on the impact of supply voltage, and then have avoided the fluctuation that changes readout time and misread out the problem such as phenomenon.
Describe circuit in detail among the embodiment that the invention described above provides, can adopt the method for various ways to realize for circuit of the present invention, so the present invention also provides a kind of method for reading data, the below provides specific embodiment and is elaborated.
See also Fig. 6, be a kind of method for reading data provided by the invention, it is applied to eeprom circuit, comprises step:
S101: synchronously control the first reference unit and write the first preset data when erasable in that the data unit is carried out, control the second reference unit and write the second preset data;
S102: gather the first reading current of described the first reference unit and the second reading current of described the second reference unit, and export one and become the output current of preset ratio with described the second reading current with described the first reading current;
S103: the reading current of more described data cell and described output current obtain the data of the storage of described data cell.
Except this, the present invention also provides a kind of nonvolatile memory on the basis that a kind of EPROM circuit is provided, be packaged with the circuit described in above-described embodiment one.
In sum: the invention provides a kind of EPROM circuit, because complementary two reference units and data cell co-localization are in memory array cell, eliminate parasitic parameter and since the deviation band of manufacture craft the impact on supply voltage, again since reference unit and data cell wipe synchronously and data writing, therefore, reference unit can be good at the tracking data unit owing to repeat threshold voltage shift erasable or that the data maintenance causes, thereby improves stability, reliability and the permanance of chip performance.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the device that embodiment provides, because it is corresponding with the method that embodiment provides, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
Above-mentioned explanation to the embodiment that provides makes this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but principle and the features of novelty the widest consistent scope that provides with this paper will be provided.
Claims (10)
1. an eeprom circuit is characterized in that, comprising: memory cell array, erasable circuit and reading circuit, and described memory cell array comprises: set of reference cells and data sheet tuple,
Described set of reference cells comprises the first reference unit and the second reference unit, and described data sheet tuple comprises at least one data cell;
Each described data cell all is connected to predetermined word line or bit line with described set of reference cells;
Described erasable circuit links to each other with every row in the described memory cell array, is used for synchronously controlling described the first reference unit and writing the first preset data when erasable in that the data unit is carried out, and controls described the second reference unit and writes the second preset data;
Described reading circuit comprises reference unit reading circuit and data cell reading circuit, wherein, described reference unit reading circuit gathers the first reading current of described the first reference unit and the second reading current of described the second reference unit, and export one and become the output current of preset ratio with described the second reading current with described the first reading current, described data cell reading circuit is used for gathering the reading current of the described data cell of every row, and the output current of the reading current of the described data cell of more every row and described reference unit reading circuit, obtain the data of the storage of described data cell.
2. eeprom circuit according to claim 1 is characterized in that, described reference unit reading circuit comprises the first switching tube, second switch pipe and current mirror,
The grid of described the first switching tube links to each other with the grid of described second switch pipe, and public connecting end links to each other with external sense wire;
The source electrode of described the first switching tube links to each other with the transistorized drain electrode of selection in described the first reference unit, and the source electrode of described second switch pipe links to each other with the transistorized drain electrode of selection in described the second reference unit;
The input end of described current mirror links to each other with the drain electrode of described the first switching tube and the drain electrode of described second switch pipe respectively, and output terminal links to each other with described data cell reading circuit.
3. eeprom circuit according to claim 2 is characterized in that, described data cell reading circuit comprises: the 7th switching tube and impact damper;
The grid of described the 7th switching tube links to each other with the grid of described second switch pipe, the drain electrode of described the 7th switching tube links to each other with the output terminal of described reference unit reading circuit and the input end of impact damper respectively, and the output terminal of described impact damper is as the output terminal of described data cell reading circuit.
4. eeprom circuit according to claim 2 is characterized in that, the output current of described current mirror is 1/2nd of input current.
5. eeprom circuit according to claim 2 is characterized in that, described the first switching tube, described second switch pipe and described the 7th switching tube are the N-type metal-oxide-semiconductor.
6. eeprom circuit according to claim 1 is characterized in that, described the first preset data is the anti-data of described the second preset data, and when described the first preset data was 0, described the second preset data was 1; When described the first preset data was 1, described the second preset data was 0.
7. eeprom circuit according to claim 1 is characterized in that:
When the reading current of described data cell during greater than the output current of described reference unit reading circuit, the data of described data cell storage are 0;
When the reading current of described data cell during less than the output current of described reference unit reading circuit, the data of described data cell storage are 1.
8. a method for reading data is applied to eeprom circuit, it is characterized in that, comprising:
Synchronously control the first reference unit and write the first preset data when erasable in that the data unit is carried out, control the second reference unit and write the second preset data;
Gather the first reading current of described the first reference unit and the second reading current of described the second reference unit, and export one and become the output current of preset ratio with described the second reading current with described the first reading current;
The reading current of more described data cell and described output current obtain the data of the storage of described data cell.
9. method for reading data according to claim 8 is characterized in that, described output current is 1/2nd of described the first reading current and described the second reading current sum.
10. a nonvolatile memory is characterized in that, comprises such as eeprom circuit as described in any one among the claim 1-7.
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