CN103106148B - Block management method, memory controller and memory storage device - Google Patents

A block management method, a memory controller and a memory storage device are provided. The method is used for managing a plurality of entity blocks of the rewritable nonvolatile memory module in the memory storage device. The method includes maintaining an error information mapping table to record error correctable physical blocks in the physical blocks and error bits corresponding to the error correctable physical blocks. The method further comprises selecting the physical block for writing data according to the error correctable physical block in the error information corresponding table and the corresponding error bit number. Therefore, the data stability of the memory storage device can be improved.

区块管理方法、存储器控制器与存储器存储装置Block management method, memory controller and memory storage device

技术领域 technical field

本发明涉及一种区块管理方法，尤其涉及一种管理可复写式非易失性存储器模组的实体区块的方法，以及使用此方法的存储器控制器与存储器存储装置。The present invention relates to a block management method, in particular to a method for managing physical blocks of a rewritable non-volatile memory module, and a memory controller and a memory storage device using the method.

背景技术 Background technique

可复写式非易失性存储器(rewritable non-volatile memory)具有数据非易失性、省电、体积小与无机械结构等特性，故被广泛地应用于各种电子装置。可复写式非易失性存储器具有多个实体区块(physicalblock)，且每一实体区块具有多个实体页面(physical page)。其中，实体区块为数据抹除的最小单位，而实体页面则是数据写入的最小单位。Rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size and no mechanical structure, so it is widely used in various electronic devices. The rewritable non-volatile memory has a plurality of physical blocks, and each physical block has a plurality of physical pages. Wherein, the physical block is the smallest unit of data erasing, and the physical page is the smallest unit of data writing.

当使用可复写式非易失性存储器的存储装置(以下称为存储器存储装置)被制造完成而进行第一次格式化(亦称为开卡)时，存储器存储装置的存储器控制器会对可复写式非易失性存储器的所有实体区块进行磁盘扫瞄以识别出正常及损毁的实体区块。存储器控制器会将正常的实体区块优先分组至数据区与闲置区并且将剩余的实体区块分组至取代区。其中，数据区的实体区块是用以存储来自主机系统的数据，闲置区的实体区块是用以轮替数据区中的实体区块，而取代区的实体区块则是用以在存储器存储装置运作过程中取代发生损坏的实体区块。When a storage device using a rewritable non-volatile memory (hereinafter referred to as a memory storage device) is manufactured and is formatted for the first time (also called card opening), the memory controller of the memory storage device will All physical blocks of the rewritable non-volatile memory are scanned to identify normal and damaged physical blocks. The memory controller will preferentially group the normal physical blocks into the data area and the spare area and group the remaining physical blocks into the replacement area. Among them, the physical blocks in the data area are used to store data from the host system, the physical blocks in the idle area are used to replace the physical blocks in the data area, and the physical blocks in the replacement area are used to store data in the memory. The damaged physical block is replaced during the operation of the storage device.

一般来说，正常的实体区块亦会有不同的使用寿命，因此在使用存储器存储装置的过程中，倘若实体区块之间的使用寿命差距过大，则容易造成数据不稳定的情况。Generally speaking, normal physical blocks also have different service lives. Therefore, in the process of using the memory storage device, if the service life gap between physical blocks is too large, it is easy to cause data instability.

发明内容 Contents of the invention

有鉴于此，本发明提供一种区块管理方法、存储器控制器与存储器存储装置，能减少因可复写式非易失性存储器模组中实体区块的寿命差距过大而造成数据不稳定的现象。In view of this, the present invention provides a block management method, a memory controller and a memory storage device, which can reduce the data instability caused by the excessive life gap of the physical blocks in the rewritable non-volatile memory module. Phenomenon.

本发明提出一种区块管理方法，用以管理可复写式非易失性存储器模组中的多个实体区块。此方法包括维护错误信息对应表以记录上述实体区块中至少一错误可修正实体区块以及错误可修正实体区块所对应的错误位元数。此方法还包括依据错误信息对应表中的错误可修正实体区块以及错误可修正实体区块所对应的错误位元数来选择用以写入数据的实体区块。The invention proposes a block management method for managing multiple physical blocks in a rewritable non-volatile memory module. The method includes maintaining an error information correspondence table to record at least one error-correctable physical block among the physical blocks and the number of error bits corresponding to the error-correctable physical block. The method further includes selecting a physical block for writing data according to the error correctable physical block in the error information correspondence table and the number of error bits corresponding to the error correctable physical block.

从另一观点来看，本发明提出一种存储器控制器，用于管理存储器存储装置中的可复写式非易失性存储器模组。此存储器控制器包括主机系统介面、存储器介面，以及存储器管理电路。主机系统介面用以耦接至主机系统。存储器介面用以耦接可复写式非易失性存储器模组，此可复写式非易失性存储器模组包括多个实体区块。存储器管理电路耦接至主机系统介面与存储器介面，存储器管理电路用以维护错误信息对应表以记录上述实体区块中至少一错误可修正实体区块以及错误可修正实体区块所对应的错误位元数，并且依据错误信息对应表中的错误可修正实体区块以及错误可修正实体区块所对应的错误位元数来选择用以写入数据的实体区块。From another point of view, the present invention provides a memory controller for managing a rewritable non-volatile memory module in a memory storage device. The memory controller includes a host system interface, a memory interface, and a memory management circuit. The host system interface is used for coupling to the host system. The memory interface is used for coupling the rewritable non-volatile memory module, and the rewritable non-volatile memory module includes a plurality of physical blocks. The memory management circuit is coupled to the host system interface and the memory interface, and the memory management circuit is used to maintain an error information correspondence table to record at least one error-correctable physical block in the above-mentioned physical blocks and the error bits corresponding to the error-correctable physical blocks and select a physical block for writing data according to the error correctable physical block in the error information correspondence table and the number of error bits corresponding to the error correctable physical block.

从又一观点来看，本发明提出一种存储器存储装置，包括可复写式非易失性存储器模组、连接器以及存储器控制器。可复写式非易失性存储器模组包括多个实体区块。连接器用以耦接主机系统。存储器控制器耦接至可复写式非易失性存储器模组与连接器，存储器控制器用以维护错误信息对应表以记录上述实体区块中至少一错误可修正实体区块以及错误可修正实体区块所对应的错误位元数，并且依据错误信息对应表中的错误可修正实体区块以及错误可修正实体区块所对应的错误位元数来选择用以写入数据的实体区块。From another point of view, the present invention provides a memory storage device, including a rewritable non-volatile memory module, a connector, and a memory controller. The rewritable non-volatile memory module includes multiple physical blocks. The connector is used to couple with the host system. The memory controller is coupled to the rewritable non-volatile memory module and the connector, and the memory controller is used to maintain the error information correspondence table to record at least one error-correctable physical block and the error-correctable physical area among the above-mentioned physical blocks The number of error bits corresponding to the block, and the physical block for writing data is selected according to the error correctable physical block in the error information correspondence table and the error bit number corresponding to the error correctable physical block.

基于上述，本发明是依据各实体区块是否通过写入测试与抹除测试以及其错误位元数来对实体区块进行管理。进一步来说，本发明是依照实体区块的错误位元数来决定是否使用该实体区块来写入数据。据此，能让可复写式非易失性存储器模组中的实体区块使用寿命更为平均，从而增加数据稳定性。Based on the above, the present invention manages the physical blocks according to whether each physical block passes the writing test and the erasing test and the number of error bits. Further, the present invention determines whether to use the physical block to write data according to the number of error bits in the physical block. Accordingly, the service life of the physical blocks in the rewritable non-volatile memory module can be more even, thereby increasing data stability.

为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

附图说明 Description of drawings

图1A是根据本发明一范例实施例显示的使用存储器存储装置的主机系统的示意图。FIG. 1A is a schematic diagram of a host system using a memory storage device according to an exemplary embodiment of the present invention.

图1B是根据本发明范例实施例所显示的电脑、输入/输出装置与存储器存储装置的示意图。FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment of the present invention.

图1C是根据本发明另一范例实施例所显示的主机系统与存储器存储装置的示意图。FIG. 1C is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

图2是显示图1A所示的存储器存储装置的概要方块图。FIG. 2 is a schematic block diagram showing the memory storage device shown in FIG. 1A.

图3是根据本发明一范例实施例显示的存储器控制器的概要方块图。FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

图4是根据本发明的一范例实施例所显示的管理实体区块的示意图。FIG. 4 is a schematic diagram of a management physical block displayed according to an exemplary embodiment of the present invention.

图5A、5B是根据本发明的一范例实施例所显示的错误信息对应表的示意图。5A and 5B are schematic diagrams of error information correspondence tables displayed according to an exemplary embodiment of the present invention.

图6是根据本发明的一范例实施例所显示的区块管理方法的流程图。FIG. 6 is a flowchart of a block management method according to an exemplary embodiment of the present invention.

图7是根据本发明的另一范例实施例所显示的区块管理方法的流程图。FIG. 7 is a flow chart showing a block management method according to another exemplary embodiment of the present invention.

主要元件符号说明：Description of main component symbols:

1000：主机系统1000: host system

1100：电脑1100: computer

1102：微处理器1102: Microprocessor

1104：随机存取存储器1104: random access memory

1106：输入/输出装置1106: Input/Output Device

1108：系统汇流排1108: System bus

1110：数据传输介面1110: data transmission interface

1202：鼠标1202: Mouse

1204：键盘1204: keyboard

1206：显示器1206: display

1208：印表机1208: Printer

1212：移动盘1212: Move Disk

1214：记忆卡1214: memory card

1216：固态硬盘1216: SSD

1310：数码相机1310: Digital camera

1312：SD卡1312: SD card

1314：MMC卡1314: MMC card

1316：记忆棒1316: memory stick

1318：CF卡1318: CF card

1320：嵌入式存储装置1320: Embedded storage device

100：存储器存储装置100: memory storage device

102：连接器102: Connector

104：存储器控制器104: memory controller

106：可复写式非易失性存储器模组106: Rewritable non-volatile memory module

1041：主机系统介面1041: host system interface

1043：存储器管理电路1043: memory management circuit

1045：存储器介面1045: memory interface

3002：错误检查与校正电路3002: Error checking and correction circuit

3004：缓冲存储器3004: buffer memory

3006：电源管理电路3006: Power management circuit

410(0)～410(N)：实体区块410(0)～410(N): physical block

502：数据区502: data area

504：闲置区504: idle area

506：系统区506: System area

508：取代区508: Replacement area

610(0)～610(L)：逻辑区块610(0)～610(L): logical block

700、800：错误信息对应表700, 800: error message correspondence table

PBA(i)、PBA(j)、PBA(k)、PBA(1)、PBA(m)、PBA(n)、PBA(a)、PBA(b)、PBA(c)、PBA(d)：实体区块位址PBA(i), PBA(j), PBA(k), PBA(1), PBA(m), PBA(n), PBA(a), PBA(b), PBA(c), PBA(d): Physical block address

800-0、800-1、800-2、800-(N-1)、800-N：分表800-0, 800-1, 800-2, 800-(N-1), 800-N: sub-table

S610～S640：本发明的一实施例所述的区块管理方法的各步骤S610-S640: each step of the block management method described in an embodiment of the present invention

S710～S740：本发明的另一实施例所述的区块管理方法的各步骤S710-S740: each step of the block management method described in another embodiment of the present invention

具体实施方式 Detailed ways

一般而言，存储器存储装置(亦称，存储器存储系统)包括可复写式非易失性存储器模组与控制器(亦称，控制电路)。通常存储器存储装置会与主机系统一起使用，以使主机系统可将数据写入至存储器存储装置或从存储器存储装置中读取数据。另外，亦有存储器存储装置是包括嵌入式存储器与可执行于主机系统上以实质地作为此嵌入式存储器的控制器的软件。一般来说在存储器存储装置出厂时，可复写式非易失性存储器模组便包括正常的实体区块与损坏的实体区块(亦称，坏实体区块)，而各正常实体区块随着其读取数据错误率的不同会有相异的使用寿命。本发明便是基于上述观点而提出的一种区块管理方法、存储器控制器与存储器存储装置，藉由平均实体区块的使用寿命来增加数据的正确性。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically a memory storage device is used with a host system such that the host system can write data to or read data from the memory storage device. In addition, there is also a memory storage device that includes an embedded memory and software executable on a host system that essentially serves as a controller for the embedded memory. Generally speaking, when the memory storage device leaves the factory, the rewritable non-volatile memory module includes normal physical blocks and damaged physical blocks (also known as bad physical blocks), and each normal physical block is Depending on the error rate of the read data, the service life will be different. The present invention proposes a block management method, a memory controller, and a memory storage device based on the above point of view, and increases the accuracy of data by averaging the service life of physical blocks.

图1A是根据本发明一范例实施例所显示的使用存储器存储装置的主机系统的示意图。FIG. 1A is a schematic diagram of a host system using a memory storage device according to an exemplary embodiment of the present invention.

主机系统1000包括电脑1100与输入/输出(Input/Output，I/O)装置1106。电脑1100包括微处理器1102、随机存取存储器(Random AccessMemory，RAM)1104、系统汇流排1108以及数据传输介面1110。输入/输出装置1106包括如图1B所示的鼠标1202、键盘1204、显示器1206与印表机1208。必须了解的是，图1B所示的装置非限制输入/输出装置1106，输入/输出装置1106可还包括其他装置。The host system 1000 includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (Random Access Memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

在本发明范例实施例中，存储器存储装置100是通过数据传输介面1110与主机系统1000的其他元件耦接。藉由微处理器1102、随机存取存储器1104以及输入/输出装置1106的运作，主机系统1000可将数据写入至存储器存储装置100，或从存储器存储装置100中读取数据。例如，存储器存储装置100可以是如图1B所示的记忆卡1214、移动盘1212、或固态硬盘(Solid State Drive，SSD)1216。In an exemplary embodiment of the present invention, the memory storage device 100 is coupled with other components of the host system 1000 through the data transmission interface 1110 . Through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 , the host system 1000 can write data into the memory storage device 100 or read data from the memory storage device 100 . For example, the memory storage device 100 may be a memory card 1214, a removable disk 1212, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

一般而言，主机系统1000为可存储数据的任意系统。虽然在本范例实施例中主机系统1000是以电脑系统来作说明，然而，在本发明另一范例实施例中，主机系统1000亦可以是手机、数码相机、摄影机、通讯装置、音讯播放器或视讯播放器等系统。例如，在主机系统为数码相机1310时，存储器存储装置则为其所使用的安全数位(Secure Digital，SD)卡1312、多媒体记忆(Multimedia Card，MMC)卡1314、记忆棒(Memory Stick)1316、小型快闪(Compact Flash，CF)卡1318或嵌入式存储装置1320(如图1C所示)。嵌入式存储装置1320包括嵌入式多媒体卡(Embedded MMC，eMMC)。值得一提的是，嵌入式多媒体卡是直接耦接于主机系统的基板上。In general, host system 1000 is any system that can store data. Although the host system 1000 is described as a computer system in this exemplary embodiment, in another exemplary embodiment of the present invention, the host system 1000 may also be a mobile phone, a digital camera, a video camera, a communication device, an audio player or systems such as video players. For example, when the host system is a digital camera 1310, the memory storage device is a secure digital (Secure Digital, SD) card 1312, a multimedia memory (Multimedia Card, MMC) card 1314, a memory stick (Memory Stick) 1316, A compact flash (Compact Flash, CF) card 1318 or an embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.

图2是显示图1A所示的存储器存储装置100的方块图。请参照图2，存储器存储装置100包括连接器102、存储器控制器104与可复写式非易失性存储器模组106。FIG. 2 is a block diagram showing the memory storage device 100 shown in FIG. 1A. Referring to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

连接器102耦接至存储器控制器104，并且用以耦接主机系统1000。在本范例实施例中，连接器102所支援的传输介面种类为序列先进附件(Serial Advanced Technology Attachment，SATA)介面。然而在其他范例实施例中，连接器102的传输介面种类也可以是通用序列汇流排(Universal Serial Bus，USB)介面、多媒体存储卡(Multimedia Card，MMC)介面、平行先进附件(Parallel Advanced Technology Attachment，PATA)介面、电气和电子工程师协会(Institute of Electrical and ElectronicEngineers，IEEE)1394介面、高速周边零件连接介面(PeripheralComponent Interconnect Express，PCI Express)介面、安全数位(SecureDigital，SD)介面、记忆棒(Memory Stick，MS)介面、小型快闪(CompactFlash，CF)介面，或整合驱动电子(Integrated Drive Electronics，IDE)介面等任何适用的介面，在此并不加以限制。The connector 102 is coupled to the memory controller 104 for coupling to the host system 1000 . In this exemplary embodiment, the type of transmission interface supported by the connector 102 is a Serial Advanced Technology Attachment (SATA) interface. However, in other exemplary embodiments, the transmission interface type of the connector 102 may also be a Universal Serial Bus (Universal Serial Bus, USB) interface, a Multimedia Card (Multimedia Card, MMC) interface, a Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment) , PATA) interface, Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 interface, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) interface, secure digital (SecureDigital, SD) interface, memory stick (Memory Any applicable interface such as Stick (MS) interface, CompactFlash (CF) interface, or Integrated Drive Electronics (IDE) interface is not limited herein.

存储器控制器104会执行以硬件型式或韧体型式实作的多个逻辑闸或控制指令，并根据主机系统1000的指令在可复写式非易失性存储器模组106中进行数据的写入、读取与抹除等运作。其中，存储器控制器104还特别用以根据本范例实施例的区块管理方法而依照错误位元数来对可复写式非易失性存储器模组106中的实体区块进行使用与否的管理。本范例实施例的区块管理方法将于后配合图示再作说明。The memory controller 104 executes a plurality of logic gates or control instructions implemented in hardware or firmware, and writes data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000, Operations such as reading and erasing. Wherein, the memory controller 104 is also specially used for managing the use or non-use of the physical blocks in the rewritable non-volatile memory module 106 according to the number of error bits according to the block management method of this exemplary embodiment. . The block management method of this exemplary embodiment will be described later with the illustrations.

可复写式非易失性存储器模组106耦接至存储器控制器104。可复写式非易失性存储器模组106包括多个实体区块，且每一实体区块包括多个实体页面。举例来说，可复写式非易失性存储器模组106为多阶记忆胞(Multi Level Cell，MLC)NAND快闪存储器模组，但本发明不限于此，可复写式非易失性存储器模组106也可以是单阶记忆胞(SingleLevel Cell，SLC)NAND快闪存储器模组、其他快闪存储器模组或任何具有相同特性的存储器模组。The rewritable non-volatile memory module 106 is coupled to the memory controller 104 . The rewritable non-volatile memory module 106 includes a plurality of physical blocks, and each physical block includes a plurality of physical pages. For example, the rewritable nonvolatile memory module 106 is a multi-level memory cell (Multi Level Cell, MLC) NAND flash memory module, but the present invention is not limited thereto, the rewritable nonvolatile memory module The group 106 can also be a single-level memory cell (Single Level Cell, SLC) NAND flash memory module, other flash memory modules or any memory module with the same characteristics.

图3是根据本发明一范例实施例所显示的存储器控制器的概要方块图。请参照图3，存储器控制器104包括主机系统介面1041、存储器管理电路1043，以及存储器介面1045。FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention. Referring to FIG. 3 , the memory controller 104 includes a host system interface 1041 , a memory management circuit 1043 , and a memory interface 1045 .

主机系统介面1041耦接至存储器管理电路1043，并通过连接器102以耦接主机系统1000。主机系统介面1041是用以接收与识别主机系统1000所传送的指令与数据。据此，主机系统1000所传送的指令与数据会通过主机系统介面1041而传送至存储器管理电路1043。在本范例实施例中，主机系统介面1041对应连接器102而为SATA介面，而在其他范例实施例中，主机系统介面1041也可以是USB介面、MMC介面、PATA介面、IEEE 1394介面、PCI Express介面、SD介面、MS介面、CF介面、IDE介面或符合其他介面标准的介面。The host system interface 1041 is coupled to the memory management circuit 1043 and is coupled to the host system 1000 through the connector 102 . The host system interface 1041 is used for receiving and identifying commands and data sent by the host system 1000 . Accordingly, the commands and data sent by the host system 1000 are sent to the memory management circuit 1043 through the host system interface 1041 . In this exemplary embodiment, the host system interface 1041 corresponds to the connector 102 and is a SATA interface, and in other exemplary embodiments, the host system interface 1041 can also be a USB interface, an MMC interface, a PATA interface, an IEEE 1394 interface, or a PCI Express interface. interface, SD interface, MS interface, CF interface, IDE interface or interfaces that meet other interface standards.

存储器管理电路1043是用以控制存储器控制器104的整体运作。具体来说，存储器管理电路1043具有多个控制指令，在存储器存储装置100运作时，上述控制指令会被执行以实现本范例实施例的区块管理方法。The memory management circuit 1043 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 1043 has a plurality of control instructions, which are executed when the memory storage device 100 is operating to implement the block management method of this exemplary embodiment.

在一范例实施例中，存储器管理电路1043的控制指令是以韧体型式来实作。例如，存储器管理电路1043具有微处理器单元(未显示)与只读存储器(未显示)，且上述控制指令是被烧录在只读存储器中。当存储器存储装置100运作时，上述控制指令会由微处理器单元来执行以完成本范例实施例的区块管理方法。In an exemplary embodiment, the control commands of the memory management circuit 1043 are implemented in the form of firmware. For example, the memory management circuit 1043 has a microprocessor unit (not shown) and a read-only memory (not shown), and the above-mentioned control instructions are burned in the read-only memory. When the memory storage device 100 is in operation, the above control instructions will be executed by the microprocessor unit to complete the block management method of this exemplary embodiment.

在本发明另一范例实施例中，存储器管理电路1043的控制指令亦可以程式码型式存储于可复写式非易失性存储器模组106的特定区域(例如，可复写式非易失性存储器模组106中专用于存放系统数据的系统区)中。此外，存储器管理电路1043具有微处理器单元(未显示)、只读存储器(未显示)及随机存取存储器(未显示)。其中，只读存储器具有驱动码段，并且当存储器控制器104被致能时，微处理器单元会先执行此驱动码段来将存储于可复写式非易失性存储器模组106中的控制指令载入至存储器管理电路1043的随机存取存储器中。之后，微处理器单元会运转上述控制指令以执行本范例实施例的区块管理方法。此外，在本发明另一范例实施例中，存储器管理电路1043的控制指令亦可以一硬件型式来实作。In another exemplary embodiment of the present invention, the control command of the memory management circuit 1043 can also be stored in a specific area of the rewritable non-volatile memory module 106 (for example, the rewritable non-volatile memory module Group 106 is dedicated to storing system data in the system area). In addition, the memory management circuit 1043 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). Wherein, the read-only memory has a driving code segment, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driving code segment to store the control code stored in the rewritable non-volatile memory module 106 The instructions are loaded into the random access memory of the memory management circuit 1043 . Afterwards, the microprocessor unit executes the above control instructions to execute the block management method of this exemplary embodiment. In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 1043 can also be implemented in a hardware form.

存储器介面1045耦接至存储器管理电路1043，以使存储器控制器104与可复写式非易失性存储器模组106相耦接。据此，存储器控制器104可对可复写式非易失性存储器模组106进行相关运作。也就是说，欲写入至可复写式非易失性存储器模组106的数据会经由存储器介面1045转换为可复写式非易失性存储器模组106所能接受的格式。The memory interface 1045 is coupled to the memory management circuit 1043 to couple the memory controller 104 with the rewritable non-volatile memory module 106 . Accordingly, the memory controller 104 can perform related operations on the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable non-volatile memory module 106 will be converted into a format acceptable to the rewritable non-volatile memory module 106 through the memory interface 1045 .

在本发明的另一范例实施例中，存储器控制器104还包括错误检查与校正电路3002。错误检查与校正电路3002耦接至存储器管理电路1043，用以执行错误检查与校正程序以确保数据的正确性。具体而言，当存储器管理电路1043接收到来自主机系统1000的写入指令时，错误检查与校正电路3002会为对应此写入指令的数据产生对应的错误检查与校正码(Error Checking and Correcting Code，ECC Code)，且存储器管理电路1043会将对应此写入指令的数据与对应的错误检查与校正码写入至可复写式非易失性存储器模组106。之后当存储器管理电路1043从可复写式非易失性存储器模组106中读取数据时，会同时读取此数据对应的错误检查与校正码，且错误检查与校正电路3002会依据此错误检查与校正码对所读取的数据执行错误检查与校正程序，以识别该笔数据是否存在错误位元。In another exemplary embodiment of the present invention, the memory controller 104 further includes an error checking and correction circuit 3002 . The error checking and correction circuit 3002 is coupled to the memory management circuit 1043 for executing error checking and correction procedures to ensure the correctness of data. Specifically, when the memory management circuit 1043 receives a write command from the host system 1000, the error checking and correcting circuit 3002 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command , ECC Code), and the memory management circuit 1043 will write the data corresponding to the write command and the corresponding error checking and correction code into the rewritable non-volatile memory module 106. Afterwards, when the memory management circuit 1043 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 3002 will check the error according to the The error checking and correction program is executed on the read data with the correction code to identify whether there is an error bit in the data.

在本发明的另一范例实施例中，存储器控制器104还包括缓冲存储器3004。缓冲存储器3004可以是静态随机存取存储器(Static RandomAccess Memory，SRAM)、或动态随机存取存储器(Dynamic RandomAccess Memory，DRAM)等，本发明并不加以限制。缓冲存储器3004耦接至存储器管理电路1043，用以暂存来自于主机系统1000的数据，或暂存来自于可复写式非易失性存储器模组106的数据。In another exemplary embodiment of the present invention, the memory controller 104 further includes a buffer memory 3004 . The buffer memory 3004 may be a static random access memory (Static Random Access Memory, SRAM), or a dynamic random access memory (Dynamic Random Access Memory, DRAM), etc., and the present invention is not limited thereto. The buffer memory 3004 is coupled to the memory management circuit 1043 for temporarily storing data from the host system 1000 or temporarily storing data from the rewritable non-volatile memory module 106 .

在本发明又一范例实施例中，存储器控制器104还包括电源管理电路3006。电源管理电路3006耦接至存储器管理电路1043，用以控制存储器存储装置100的电源。In yet another exemplary embodiment of the present invention, the memory controller 104 further includes a power management circuit 3006 . The power management circuit 3006 is coupled to the memory management circuit 1043 for controlling the power of the memory storage device 100 .

图4是根据本发明的一范例实施例所显示的管理可复写式非易失性存储器模组的实体区块的示意图。FIG. 4 is a schematic diagram of managing physical blocks of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

请参照图4，本范例实施例的可复写式非易失性存储器模组106包括实体区块410(0)～410(N)，且每一实体区块包括数个实体页面。存储器控制器104中的存储器管理电路1043会将实体区块410(0)～410(N)逻辑地分组为数据区502、闲置区504、系统区506与取代区508。其中，图4所标示的F、S、R与N为正整数，代表各区配置的实体区块数量，其可由存储器存储装置100的制造商依据所使用的可复写式非易失性存储器模组106的容量来设定。Referring to FIG. 4 , the rewritable non-volatile memory module 106 of this exemplary embodiment includes physical blocks 410 ( 0 )˜410 (N), and each physical block includes several physical pages. The memory management circuit 1043 in the memory controller 104 logically groups the physical blocks 410 ( 0 )˜ 410 (N) into a data area 502 , an idle area 504 , a system area 506 and a replacement area 508 . Wherein, F, S, R, and N marked in FIG. 4 are positive integers, representing the number of physical blocks configured in each area, which can be determined by the manufacturer of the memory storage device 100 according to the rewritable non-volatile memory module used. 106 capacity to set.

逻辑上属于数据区502与闲置区504的实体区块是用以存储来自于主机系统1000的数据。具体来说，数据区502的实体区块是被视为已存储数据的实体区块，而闲置区504的实体区块是用以写入新数据的实体区块。换句话说，闲置区504的实体区块为空或可使用的实体区块(无记录数据或标记为已没用的无效数据)。当从主机系统1000接收到写入指令与欲写入的数据时，存储器管理电路1043会从闲置区504中提取实体区块，并且将数据写入至所提取的实体区块中，以替换数据区502的实体区块。或者，当需要对一逻辑区块执行数据合并程序时，存储器管理电路1043会从闲置区504提取实体区块并将数据写入其中，以替换原先映射此逻辑区块的实体区块。The physical blocks logically belonging to the data area 502 and the free area 504 are used to store data from the host system 1000 . Specifically, the physical blocks in the data area 502 are physical blocks that are regarded as stored data, and the physical blocks in the spare area 504 are physical blocks for writing new data. In other words, the physical blocks of the spare area 504 are empty or usable physical blocks (no recorded data or invalid data marked as useless). When receiving a write command and data to be written from the host system 1000, the memory management circuit 1043 will extract a physical block from the spare area 504, and write data into the extracted physical block to replace the data Physical block of region 502. Alternatively, when a data merging procedure needs to be performed on a logical block, the memory management circuit 1043 will extract the physical block from the spare area 504 and write data therein to replace the physical block originally mapped to the logical block.

逻辑上属于系统区506的实体区块是用以记录系统数据。举例来说，系统数据包括关于可复写式非易失性存储器模组106的制造商与型号、可复写式非易失性存储器模组106的实体区块数、每一实体区块的实体页面数等等。The physical blocks logically belonging to the system area 506 are used to record system data. For example, the system data includes the manufacturer and model of the rewritable non-volatile memory module 106, the number of physical blocks of the rewritable non-volatile memory module 106, and the physical pages of each physical block Count and so on.

逻辑上属于取代区508的实体区块是用以在数据区502、闲置区504或系统区506中的实体区块损毁时，取代损坏的实体区块。具体而言，在存储器存储装置100运作期间，倘若取代区508中仍存有正常的实体区块且数据区502的实体区块损坏时，存储器管理电路1043会从取代区508中提取正常的实体区块来更换数据区502中损坏的实体区块。也因此，在存储器存储装置100的运作过程中，数据区502、闲置区504、系统区506与取代区508的实体区块会动态地变动。例如，用以轮替存储数据的实体区块会变动地属于数据区502或闲置区504。The physical blocks logically belonging to the replacement area 508 are used to replace the damaged physical blocks when the physical blocks in the data area 502 , spare area 504 or system area 506 are damaged. Specifically, during the operation of the memory storage device 100, if there are still normal physical blocks in the replacement area 508 and the physical blocks in the data area 502 are damaged, the memory management circuit 1043 will extract the normal physical blocks from the replacement area 508. block to replace the damaged physical block in the data area 502. Therefore, during the operation of the memory storage device 100 , the physical blocks of the data area 502 , the spare area 504 , the system area 506 and the replacement area 508 will change dynamically. For example, the physical blocks used to alternately store data may belong to the data area 502 or the free area 504 .

为了让主机系统1000能对可复写式非易失性存储器模组106进行存取，存储器管理电路1043会配置数个逻辑区块610(0)～610(L)以映射数据区502中的实体区块410(0)～410(F-1)。其中每一逻辑区块包括多个逻辑页面，而逻辑区块610(0)～610(L)中的逻辑页面会依序映射实体区块410(0)～410(F-1)中的实体页面。In order for the host system 1000 to access the rewritable non-volatile memory module 106, the memory management circuit 1043 will configure several logical blocks 610(0)-610(L) to map the entities in the data area 502 Blocks 410(0)-410(F-1). Each logical block includes a plurality of logical pages, and the logical pages in the logical blocks 610(0)-610(L) will sequentially map the entities in the physical blocks 410(0)-410(F-1) page.

详言之，存储器管理电路1043将所配置的逻辑区块610(0)～610(L)提供给主机系统1000，并维护逻辑区块-实体区块映射表(logicalblock-physical block mapping table)以记录逻辑区块610(0)～610(L)与实体区块410(0)～410(F-1)的映射关系。因此，当主机系统1000欲存取一逻辑存取位址时，存储器管理电路1043会将此逻辑存取位址转换为对应的逻辑区块的逻辑页面，再透过逻辑区块-实体区块映射表找到其所映射的实体页面来进行存取。Specifically, the memory management circuit 1043 provides the configured logical blocks 610(0)˜610(L) to the host system 1000, and maintains a logical block-physical block mapping table for The mapping relationship between the logical blocks 610(0)-610(L) and the physical blocks 410(0)-410(F-1) is recorded. Therefore, when the host system 1000 intends to access a logical access address, the memory management circuit 1043 will convert the logical access address into a logical page of the corresponding logical block, and then pass the logical block-physical block The mapping table finds its mapped entity page for access.

在本范例实施例中，当存储器存储装置100被制造完成而进行第一次格式化(亦称为开卡)时，存储器控制器104中的存储器管理电路1043会对可复写式非易失性存储器模组106的所有实体区块进行写入测试、抹除测试，以及读取测试。针对所有通过写入测试与抹除测试的实体区块，倘若其经过读取测试而产生的错误位元数小于或等于错误位元数门槛值，则该些实体区块将被存储器管理电路1043识别为错误可修正实体区块(亦即，其中的错误位元可被错误检查与校正电路3002校正)。一般来说，存储器管理电路1043在开卡程序中会优先将错误可修正实体区块分组至数据区502与闲置区504。错误位元数门槛值的大小与可复写式非易失性存储器模组106的规格有关。举例而言，倘若错误位元数门槛值为48，表示错误检查与校正电路3002具有检查与校正48个错误位元的能力。亦即，一旦所读取的数据有超过48个错误位元，该笔数据便无法被错误检查与校正电路3002校正。然而必须了解的是，本发明并不对错误位元数门槛值的大小加以限制。In this exemplary embodiment, when the memory storage device 100 is manufactured and formatted for the first time (also called card opening), the memory management circuit 1043 in the memory controller 104 will All physical blocks of the memory module 106 are subjected to write test, erase test, and read test. For all physical blocks that pass the write test and the erase test, if the number of error bits generated by the read test is less than or equal to the threshold value of the number of error bits, these physical blocks will be processed by the memory management circuit 1043 Identifies as an error correctable physical block (ie, the erroneous bits therein can be corrected by the ECC circuit 3002). Generally speaking, the memory management circuit 1043 will preferentially group the error correctable physical blocks into the data area 502 and the spare area 504 during the card opening procedure. The size of the error bit threshold is related to the specifications of the rewritable non-volatile memory module 106 . For example, if the threshold value of the number of error bits is 48, it means that the error checking and correction circuit 3002 has the capability of checking and correcting 48 error bits. That is, once the read data has more than 48 error bits, the data cannot be corrected by the error checking and correcting circuit 3002 . However, it must be understood that the present invention does not limit the threshold value of the number of error bits.

除此之外，存储器管理电路1043会将有通过写入测试与抹除测试，但在经过读取测试所产生的错误位元数大于错误位元数门槛值的实体区块，以及未通过写入测试及/或抹除测试的实体区块都识别为错误不可修正实体区块。In addition, the memory management circuit 1043 will have physical blocks that pass the writing test and erasing test, but the number of error bits generated after the read test is greater than the threshold value of the number of error bits, and the physical blocks that fail to pass the write test The physical blocks of the entry test and/or the erasure test are all identified as error uncorrectable physical blocks.

在本范例实施例中，存储器管理电路1043会将各错误可修正实体区块与其错误位元数的对应关系记录于一错误信息对应表。In this exemplary embodiment, the memory management circuit 1043 records the corresponding relationship between each error correctable physical block and its error bit number in an error information correspondence table.

在另一范例实施例中，存储器管理电路1043可仅对可复写式非易失性存储器模组106的所有实体区块进行写入测试及读取测试来取得错误位元数，并据以建立错误信息对应表。In another exemplary embodiment, the memory management circuit 1043 can only perform a write test and a read test on all physical blocks of the rewritable non-volatile memory module 106 to obtain the number of error bits, and establish Error message correspondence table.

在又一范例实施例中，存储器管理电路1043也可在存储器存储装置100的运行中藉由数据写入及读取来建立错误信息对应表。In yet another exemplary embodiment, the memory management circuit 1043 can also create an error information correspondence table by writing and reading data during the operation of the memory storage device 100 .

图5A是根据本发明的一范例实施例所显示的错误信息对应表的示意图。如图5A的错误信息对应表700所示，假设错误位元数门槛值为48，存储器管理电路1043将以0至48个错误位元为键值建立49个栏位，以分别记录所对应的错误位元数以及符合该栏位的键值的错误可修正实体区块的实体区块位址。此外，存储器管理电路1043会在错误信息对应表700建立一不可用实体区块栏位，以记录所有错误不可修正实体区块的实体区块位址。举例来说，参照错误信息对应表700可得知实体区块位址为PBA(k)以及PBA(1)的错误可修正实体区块具有1个错误位元、实体区块位址为PBA(a)以及PBA(b)的错误可修正实体区块具有48个错误位元，且实体区块位址为PBA(c)以及PBA(d)的实体区块则属于错误不可修正实体区块。FIG. 5A is a schematic diagram of an error message correspondence table displayed according to an exemplary embodiment of the present invention. As shown in the error information correspondence table 700 of FIG. 5A , assuming that the error bit number threshold value is 48, the memory management circuit 1043 will use 0 to 48 error bits as key values to create 49 fields to record the corresponding The wrong number of bits and the error matching the key value of this field can correct the physical block address of the physical block. In addition, the memory management circuit 1043 will create an unavailable physical block field in the error information corresponding table 700 to record the physical block addresses of all error uncorrectable physical blocks. For example, referring to the error information correspondence table 700, it can be known that the error-correctable physical block whose physical block address is PBA(k) and PBA(1) has 1 error bit, and the physical block address is PBA( The error correctable physical blocks of a) and PBA(b) have 48 error bits, and the physical blocks whose physical block addresses are PBA(c) and PBA(d) are error uncorrectable physical blocks.

图5B是根据本发明的另一范例实施例所显示的错误信息对应表的示意图。假设错误位元数门槛值为48，图5B的错误信息对应表800包括50个分表(例如，分表800-0、800-1、800-2、800-(N-1)、800-N)以分别记录所对应的错误位元数为0至48的错误可修正实体区块的实体区块位址以及错误不可修正实体区块的实体区块位址。在本范例实施例中，分表800-0是用以记录所有具有0个错误位元的错误可修正实体区块的实体区块位址(例如，实体区块位址PBA(i)、PBA(i))、分表800-1是用以记录所有具有1个错误位元的错误可修正实体区块的实体区块位址(例如，实体区块位址PBA(k)、PBA(1))，而分表800-N则是用以记录所有错误不可修正实体区块的实体区块位址(例如，实体区块位址PBA(c)、PBA(d))。FIG. 5B is a schematic diagram of an error information correspondence table displayed according to another exemplary embodiment of the present invention. Assuming that the threshold value of the number of error bits is 48, the error information corresponding table 800 of FIG. N) to respectively record the physical block address of the error correctable physical block and the physical block address of the error uncorrectable physical block corresponding to the number of error bits ranging from 0 to 48. In this exemplary embodiment, the sub-table 800-0 is used to record the physical block addresses of all error-correctable physical blocks with 0 error bits (for example, physical block addresses PBA(i), PBA (i)), the sub-table 800-1 is used to record the physical block addresses of all error-correctable physical blocks with 1 error bit (for example, physical block addresses PBA(k), PBA(1 )), and the sub-table 800-N is used to record the physical block addresses of all error uncorrectable physical blocks (eg, physical block addresses PBA(c), PBA(d)).

必须特别说明的是，图5A、5B仅是为了说明而举出的范例，本发明并不对存储器管理电路1043如何实作错误信息对应表加以限制。且标示在图5A、5B中的各实体区块位址也仅是为了方便说明，与其所对应的实体区块实际在可复写式非易失性存储器模组106是否相邻无关。It must be noted that FIGS. 5A and 5B are examples for illustration only, and the present invention does not limit how the memory management circuit 1043 implements the error information correspondence table. Moreover, the physical block addresses marked in FIGS. 5A and 5B are only for convenience of description, and it has nothing to do with whether the corresponding physical blocks are actually adjacent to each other in the rewritable non-volatile memory module 106 .

存储器管理电路1043会将进行开卡程序后首次建立完成的错误信息对应表存储在可复写式非易失性存储器模组106中的某一错误可修正实体区块(例如，被区分为是统区506的错误可修正实体区块)。尔后，在主机系统100对存储器存储装置100进行存取时，存储器管理电路1043会由系统区506将错误信息对应表读回缓冲存储器3004，并利用错误信息对应表来依据各错误可修正实体区块的错误位元数去选择用以写入数据的实体区块。基本上，存储器管理电路1043会较常使用所对应的错误位元数较少的错误可修正实体区块。The memory management circuit 1043 will store the error information correspondence table established for the first time after the card opening procedure in a certain error correctable physical block (for example, classified as a system) in the rewritable non-volatile memory module 106. area 506 error correctable physical block). Afterwards, when the host system 100 accesses the memory storage device 100, the memory management circuit 1043 will read the error information correspondence table from the system area 506 back to the buffer memory 3004, and use the error information correspondence table to calculate the correctable entity area according to each error. The number of error bits of the block is used to select the physical block for writing data. Basically, the memory management circuit 1043 will more often use the error correctable physical blocks corresponding to fewer error bits.

进一步来说，在存储器存储装置100被使用的期间，存储器管理电路1043会查询错误信息对应表来取得各错误可修正实体区块的错误位元数，并据以将所有错误可修正实体区块分为多个区块队列。其中各区块队列分别对应一区块使用率，且所对应的错误位元数越少的区块队列的区块使用率越高。Furthermore, during the period when the memory storage device 100 is in use, the memory management circuit 1043 will query the error information corresponding table to obtain the number of error bits of each error correctable physical block, and use it to store all the error correctable physical blocks Divided into multiple block queues. Each block queue corresponds to a block usage rate, and the corresponding block queue with fewer error bits has a higher block usage rate.

在一范例实施例中，存储器管理电路1043是直接依据错误位元数的数值将所有错误可修正实体区块分为数个区块队列。例如，存储器管理电路1043将所对应的错误位元数为0的所有错误可修正实体区块分为同一个区块队列，并将所对应的错误位元数为1的所有错误可修正实体区块分为同一个区块队列，以此类推。In an exemplary embodiment, the memory management circuit 1043 divides all error correctable physical blocks into several block queues directly according to the value of the number of error bits. For example, the memory management circuit 1043 divides all error correctable physical blocks whose corresponding error bit number is 0 into the same block queue, and divides all error correctable physical blocks whose corresponding error bit number is 1 Blocks are grouped into the same block queue, and so on.

在另一范例实施例中，存储器管理电路1043会依据错误检查与校正电路3002能校正的错误位元数的上限(即，错误位元数门槛值)定义数个错误位元数区间，并将所对应的错误位元数属于相同错误位元数区间的所有错误可修正实体区块分为同一区块队列。举例来说，假设错误位元数门槛值为48，本范例实施例的存储器管理电路1043会将对应的错误位元数为0的所有错误可修正实体区块分为第一区块队列、将对应的错误位元数介于1至20位元的错误可修正实体区块分为第二区块队列、将对应的错误位元数介于21至40位元的错误可修正实体区块分为第三区块队列，以及将对应的错误位元数介于41至48位元的错误可修正实体区块分为第四区块队列。In another exemplary embodiment, the memory management circuit 1043 defines a number of error bit intervals according to the upper limit of the number of error bits that can be corrected by the error checking and correction circuit 3002 (ie, the threshold value of the number of error bits), and All error correctable physical blocks corresponding to the number of error bits belonging to the same range of error bits are classified into the same block queue. For example, assuming that the threshold value of the number of error bits is 48, the memory management circuit 1043 of this exemplary embodiment will divide all error correctable physical blocks corresponding to the number of error bits of 0 into the first block queue, The error correctable physical blocks corresponding to the number of error bits ranging from 1 to 20 bits are divided into the second block queue, and the error correctable physical blocks corresponding to the number of error bits ranging from 21 to 40 bits are divided into is the third block queue, and the error correctable physical blocks corresponding to the number of error bits ranging from 41 to 48 bits are divided into the fourth block queue.

然而必须说明的是，本发明并不对区块队列的数量以及划分规则加以限定。However, it must be noted that the present invention does not limit the number of block queues and division rules.

每当要将一数据写入可复写式非易失性存储器模组106时，存储器管理电路1043根据各区块队列的区块使用率选择一区块队列，并利用所选的区块队列中的错误可修正实体区块来写入数据。举例来说，假设存储器管理电路1043将所有的错误可修正实体区块分为4个区块队列(以下称第一、第二、第三，以及第四区块队列)，且这4个区块队列分别对应的区块使用率为70％、15％、10％，以及5％。那么在100次写入数据的操作中，存储器管理电路1043会有70次从第一区块队列取得用以写入数据的错误可修正实体区块、有15次从第二区块队列取得用以写入数据的错误可修正实体区块、有10次从第三区块队列取得用以写入数据的错误可修正实体区块，并且有5次从第四区块队列取得用以写入数据的错误可修正实体区块。Whenever a piece of data is to be written into the rewritable non-volatile memory module 106, the memory management circuit 1043 selects a block queue according to the block utilization ratio of each block queue, and uses the selected block queue Error correctable physical blocks to write data. For example, assume that the memory management circuit 1043 divides all error correctable physical blocks into 4 block queues (hereinafter referred to as the first, second, third, and fourth block queues), and these 4 regions Block queues correspond to block usage rates of 70%, 15%, 10%, and 5%, respectively. Then, in 100 operations of writing data, the memory management circuit 1043 will acquire error correctable physical blocks for writing data from the first block queue 70 times, and obtain the error correctable physical block from the second block queue 15 times. The error correctable physical block of writing data is obtained from the third block queue 10 times to write the error correctable physical block of data, and there are 5 times obtained from the fourth block queue for writing Errors in data can correct physical blocks.

在另一范例实施例中，为了提供更佳的数据稳定性，对于所有的错误可修正实体区块，存储器管理电路1043仅会将所对应的错误位元数小于或等于特定预设值的错误可修正实体区块分为数个区块队列。举例来说，假设特定预设值为40且错误位元数门槛值为48，对于所对应的错误位元数大于40位元的所有错误可修正实体区块，即便其错误位元数并未超过错误检查与校正电路3002能校正的错误位元数上限，存储器管理电路1043仍不会将其分入任何区块队列。亦即，在有数据需要被写入可复写式非易失性存储器模组106时，存储器管理电路1043并不会使用所对应的错误位元数大于特定预设值的错误可修正实体区块来写入数据。如此一来可避免该些错误可修正实体区块因已有较高的错误位元数，而在此次写入数据时发生错误位元数激增且超过错误位元数门槛值的情况。In another exemplary embodiment, in order to provide better data stability, for all error correctable physical blocks, the memory management circuit 1043 only converts errors whose corresponding number of error bits is less than or equal to a specific preset value The modifiable physical blocks are divided into several block queues. For example, assuming that the specific preset value is 40 and the error bit threshold value is 48, for all error correctable physical blocks corresponding to the error bit number greater than 40 bits, even if the error bit number is not The memory management circuit 1043 will not classify the number of error bits exceeding the upper limit that the error checking and correction circuit 3002 can correct into any block queue. That is, when there is data to be written into the rewritable non-volatile memory module 106, the memory management circuit 1043 will not use the error correctable physical block corresponding to the number of error bits greater than a specific preset value. to write data. In this way, it can be avoided that the number of error bits in these error-correctable physical blocks increases sharply and exceeds the threshold value of error bits when data is written this time due to the high number of error bits.

必须特别说明的是，在使用可复写式非易失性存储器模组106的过程中，存储器管理电路1043会依据各错误可修正实体区块的错误位元数的变化来动态更新错误信息对应表。亦即，存储器管理电路1043将使错误信息对应表能反映每一错误可修正实体区块目前的错误位元数。而一旦有错误可修正实体区块的错误位元数变为大于错误位元数门槛值，存储器管理电路1043则重新将此错误可修正实体区块识别为错误不可修正实体区块，并将其记录在错误信息对应表(例如，记录在图5A所示的不可用实体区块栏位，或图5B所示的不可用实体区块分表800-N)。It must be noted that during the process of using the rewritable non-volatile memory module 106, the memory management circuit 1043 will dynamically update the error information corresponding table according to the change of the number of error bits in each error correctable physical block. . That is, the memory management circuit 1043 will enable the error information mapping table to reflect the current error bit number of each error correctable physical block. And once the number of error bits of an error correctable physical block becomes greater than the threshold value of error bit number, the memory management circuit 1043 will re-identify this error correctable physical block as an error uncorrectable physical block, and save it Recorded in the error information corresponding table (for example, recorded in the unavailable physical block column shown in FIG. 5A, or the unavailable physical block sub-table 800-N shown in FIG. 5B).

当需要抹除某个已使用的实体区块中的数据时，存储器管理电路1043也会根据错误信息对应表决定此实体区块在被抹除后是否要加入区块队列。具体来说，存储器管理电路1043会查找错误信息对应表以取得此实体区块的错误位元数，再根据区块队列的划分规则来判断具有此错误位元数的实体区块是否可被分入任何区块队列。举例来说，假设存储器管理电路1043定义有三个区块队列，其中第一区块队列包括错误位元数为0的错误可修正实体区块、第二区块队列包括错误位元数介于1至20位元的错误可修正实体区块，且第三区块队列包括错误位元数介于21至40位元的错误可修正实体区块。若在查找错误信息对应表取得即将执行抹除程序的实体区块的错误位元数为25个位元，那么在抹除其中的数据后，存储器管理电路1043会将该实体区块记录在第三区块队列中。而倘若在查找错误信息对应表取得此实体区块的错误位元数为45位元，那么在抹除其中的数据后该实体区块将不会被加入任何区块队列。When the data in a used physical block needs to be erased, the memory management circuit 1043 will also determine whether the physical block should be added to the block queue after being erased according to the error information correspondence table. Specifically, the memory management circuit 1043 will search the error information correspondence table to obtain the number of error bits of the physical block, and then judge whether the physical block with the number of error bits can be divided according to the division rule of the block queue. into any block queue. For example, assume that the memory management circuit 1043 defines three block queues, wherein the first block queue includes error correctable physical blocks whose error bit number is 0, and the second block queue includes error bit numbers between 1 The error correctable physical blocks have up to 20 bits, and the third block queue includes error correctable physical blocks with error bits ranging from 21 to 40 bits. If the number of error bits of the physical block that is about to execute the erasing program is obtained by searching the error information corresponding table is 25 bits, then after erasing the data therein, the memory management circuit 1043 will record the physical block in the In the three block queue. And if the number of error bits of the physical block obtained by searching the error information corresponding table is 45 bits, then the physical block will not be added to any block queue after erasing the data therein.

图6是根据本发明的一范例实施例所显示的区块管理方法的流程图。FIG. 6 is a flowchart of a block management method according to an exemplary embodiment of the present invention.

请参阅图6，在存储器存储装置100被制造完成而进行开卡程序时，首先如步骤S610所示，存储器控制器104中的存储器管理电路1043对可复写式非易失性存储器模组106中的所有实体区块执行写入测试、抹除测试，以及读取测试。Please refer to FIG. 6 , when the memory storage device 100 is manufactured and the card opening procedure is performed, first as shown in step S610, the memory management circuit 1043 in the memory controller 104 controls the memory management circuit 1043 in the rewritable non-volatile memory module 106 Perform write test, erase test, and read test on all physical blocks.

接着在步骤S620中，存储器管理电路1043从所有的实体区块中识别出错误可修正实体区块，并将错误可修正实体区块与所对应的错误位元数的对应关系记录于错误信息对应表。其中，错误可修正实体区块是指通过写入测试与抹除测试，且经过读取测试所产生的错误位元数小于或等于错误位元数门槛值的实体区块。Then in step S620, the memory management circuit 1043 identifies the error correctable physical block from all the physical blocks, and records the corresponding relationship between the error correctable physical block and the corresponding error bit number in the error information corresponding surface. Wherein, the error-correctable physical block refers to a physical block that passes the write test and the erase test, and the number of error bits generated by the read test is less than or equal to the threshold value of the number of error bits.

接着如步骤S630所示，存储器管理电路1043依据错误信息对应表中的错误可修正实体区块以及错误可修正实体区块所对应的错误位元数来选择用以写入数据的实体区块。在本范例实施例中，所对应的错误位元数较低的实体区块会具有较高的使用率。并且如步骤S640所示，存储器管理电路1043依据错误可修正实体区块的错误位元数的变化来动态更新错误信息对应表。Next, as shown in step S630 , the memory management circuit 1043 selects a physical block for writing data according to the error correctable physical block in the error information correspondence table and the number of error bits corresponding to the error correctable physical block. In this exemplary embodiment, the corresponding physical block with a lower number of error bits has a higher usage rate. And as shown in step S640, the memory management circuit 1043 dynamically updates the error information corresponding table according to the change of the error bit number of the error correctable physical block.

在使用可复写式非易失性存储器模组106的过程中，存储器管理电路1043会反复执行步骤S630及S640的动作来维护错误信息对应表，以确保错误信息对应表记录的是各错误可修正实体区块目前的错误位元数，而存储器管理电路1043是根据错误信息对应表所记录的错误可修正实体区块与错误位元数的对应关系来决定如何使用错误可修正实体区块。In the process of using the rewritable non-volatile memory module 106, the memory management circuit 1043 will repeatedly execute the actions of steps S630 and S640 to maintain the error information correspondence table, so as to ensure that the errors recorded in the error information correspondence table are correctable The current error bit number of the physical block, and the memory management circuit 1043 determines how to use the error correctable physical block according to the correspondence between the error correctable physical block and the error bit number recorded in the error information correspondence table.

图7是根据本发明的另一范例实施例所显示的区块管理方法的流程图。在本范例实施例中，存储器管理电路1043可在存储器存储装置100出厂前藉由测试操作来维护错误信息对应表，亦可在存储器存储装置100运行中藉由数据写入及读取操作来建立错误信息对应表。FIG. 7 is a flow chart showing a block management method according to another exemplary embodiment of the present invention. In this exemplary embodiment, the memory management circuit 1043 can maintain the error information correspondence table through test operations before the memory storage device 100 leaves the factory, and can also establish the error information correspondence table through data writing and reading operations during the operation of the memory storage device 100 Error message correspondence table.

详细地说，在存储器存储装置100被制造完成后，如步骤S710所示，在存储器存储装置100出厂前，存储器管理电路1043于开卡程序时对可复写式非易失性存储器模组106中的所有实体区块执行写入测试、抹除测试，以及读取测试，以从中识别出错误可修正实体区块，并据以维护错误信息对应表。亦即，存储器管理电路1043将错误可修正实体区块与所对应的错误位元数的对应关系记录在错误信息对应表。Specifically, after the memory storage device 100 is manufactured, as shown in step S710, before the memory storage device 100 leaves the factory, the memory management circuit 1043 updates the rewritable non-volatile memory module 106 during the card opening procedure. Perform write test, erase test, and read test on all physical blocks to identify error correctable physical blocks, and maintain an error information correspondence table accordingly. That is, the memory management circuit 1043 records the correspondence between the error correctable physical block and the corresponding number of error bits in the error information correspondence table.

尔后如步骤S720所示，在存储器存储装置100出厂后，存储器管理电路1043对可复写式非易失性存储器模组106中的所有实体区块执行数据写入操作以及数据读取操作，进而在上述实体区块中识别出错误可修正实体区块，并据以维护错误信息对应表。具体来说，存储器管理电路1043会从实体区块中找出经过数据读取操作而产生的错误位元数小于或等于错误位元数门槛值的实体区块以识别为错误可修正实体区块，并将错误可修正实体区块与所对应的错误位元数的对应关系记录于错误信息对应表。Thereafter, as shown in step S720, after the memory storage device 100 leaves the factory, the memory management circuit 1043 performs data writing operations and data reading operations on all physical blocks in the rewritable non-volatile memory module 106, and then The physical block can be corrected if an error is identified in the physical block, and an error information correspondence table is maintained accordingly. Specifically, the memory management circuit 1043 will find a physical block whose number of error bits generated by the data read operation is less than or equal to the threshold value of the number of error bits from the physical blocks to identify as an error correctable physical block , and record the correspondence relationship between the error correctable physical block and the corresponding error bit number in the error information correspondence table.

接下来如步骤S730所示，存储器管理电路1043依据错误信息对应表中的错误可修正实体区块以及错误可修正实体区块所对应的错误位元数来选择用以写入数据的实体区块。并如步骤S740所示，存储器管理电路1043依据错误可修正实体区块的错误位元数的变化来动态更新错误信息对应表。Next, as shown in step S730, the memory management circuit 1043 selects a physical block for writing data according to the error correctable physical block in the error information correspondence table and the number of error bits corresponding to the error correctable physical block . And as shown in step S740, the memory management circuit 1043 dynamically updates the error information correspondence table according to the change of the error bit number of the error correctable physical block.

综上所述，本发明所述的区块管理方法、存储器控制器与存储器存储装置会维护一错误信息对应表以记录每一错误可修正实体区块所对应的错误位元数，并根据各实体区块的错误位元数来选择要利用哪个实体区块来写入数据。以上述方式对实体区块进行管理不仅能平均可复写式非易失性存储器模组中的各实体区块的使用寿命，还能增加存储器存储装置中的数据稳定性。In summary, the block management method, memory controller, and memory storage device of the present invention maintain an error information correspondence table to record the number of error bits corresponding to each error correctable physical block, and according to each The error bit number of the physical block is used to select which physical block is used to write data. Managing the physical blocks in the above manner can not only average the service life of each physical block in the rewritable non-volatile memory module, but also increase the data stability in the memory storage device.

虽然本发明已以实施例揭示如上，但其并非用以限定本发明，任何所属技术领域的技术人员，在不脱离本发明的精神和范围内，当可作适当的改动和同等替换，故本发明的保护范围应当以本申请权利要求所界定的范围为准。Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make appropriate changes and equivalent replacements without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the claims of the present application.