CN103137642B - The pixel cell of cmos image sensor and cmos image sensor - Google Patents

The invention discloses a kind of pixel cell and cmos image sensor of cmos image sensor, belong to image sensing area.The pixel cell of this cmos image sensor is arranged in 2 × 2 pixel back-to-back type array structures by 4 pixels, wherein two pixels of two pixels of first row and secondary series respectively in row separately shared row selecting transistor, source follow transistor, reset transistor and floating active area; The drain electrode of the row selecting transistor that the drain electrode of the reset transistor of first row pixel, source are followed in the source electrode of transistor and secondary series pixel is interconnected.In pixel cell, eliminate row selecting transistor grid sequencing control metal wire, power line and row picture element signal output line share a row metal wire.Therefore pel array of the present invention effectively can improve the use optical efficiency of small size element sensor, thus improves sensitivity, so the present invention effectively improves the image quality of small size pixel image sensor.

Pixel unit of CMOS image sensor and CMOS image sensor

Technical Field

The present invention relates to a CMOS image sensor, and more particularly, to a pixel unit of a CMOS image sensor using a small-area pixel and a CMOS image sensor.

Background

Image sensors have been widely used in digital cameras, mobile phones, medical devices, automobiles, and other applications. Especially, the rapid development of CMOS (complementary metal oxide semiconductor) image sensors has made higher demands for low power consumption, small size and high resolution image sensors.

In the prior art, the pixel structure of the CMOS image sensor is arranged in a manner of 4T2S (four transistors and two pixels share), and depending on the structural characteristics of the pixel itself, the two-dimensional pixel array generally requires a row decoder control metal line to be connected to the gates of the charge transfer transistor, the row select transistor and the reset transistor, and a power supply metal line and a column pixel signal output metal line to control the pixel array device to realize the function of collecting the photoelectric signal.

The above prior art has at least the following disadvantages: because the small-size pixel sensor has small photosensitive area and low sensitivity, information transmitted under dark light is not clear enough, particularly, a plurality of metal interconnection wires are used in a pixel array, so that the aperture opening ratio of a metal window is low, partial light is prevented from being incident into a photodiode, and the definition of an image is influenced.

Disclosure of Invention

The invention aims to solve the technical problem of providing a pixel unit of a CMOS image sensor and the CMOS image sensor, which improve the aperture opening ratio of a metal window, ensure the definition of an image and solve the problem that the aperture opening ratio of the metal window is low and the definition of the image is influenced because a plurality of metal wires are used in a small-size pixel array of the CMOS image sensor at present and partial light is prevented from being incident into a photodiode.

The technical scheme for solving the technical problems is as follows:

the present invention provides a pixel unit of a CMOS image sensor, including: the pixel comprises a photodiode and a charge transfer transistor connected with the photodiode, wherein 4 pixels are arranged into a 2 x2 pixel back-to-back array structure, a row selection transistor, a source following transistor, a reset transistor and a floating active region are arranged in each column of pixels, and two pixels in each column share the row selection transistor, the source following transistor, the reset transistor and the floating active region which are arranged in the column;

and the drain electrode of the reset transistor of the first column of pixels, the source electrode of the source following transistor and the drain electrode of the row selection transistor in the second column of pixels are mutually connected.

The present invention also provides a CMOS image sensor including: the pixel array comprises a column control device, a row decoder, a signal reading device and a plurality of pixel units connected with the devices, wherein each pixel unit adopts the pixel unit of the invention, and the pixel units are arranged in the vertical and horizontal directions to form a two-dimensional pixel array.

The invention has the beneficial effects that: because the pixel unit of the CMOS image sensor adopts a 4T2S structure, 4 pixels are arranged into a 2 x2 pixel array as a group, and two columns of pixels are arranged in a back-to-back structure; the grid time sequence control metal wire of the row selection transistor is omitted from the pixel unit, and the power line and the column pixel signal output line share one column metal wire, so that the metal window opening rate of the CMOS image sensor is effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a pixel unit according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a CMOS image sensor exemplified by a 6 × 6 pixel array according to an embodiment of the present invention;

fig. 3 is a timing diagram of a row decoder and a timing diagram of a column control device of a pixel array of a CMOS image sensor according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a pixel unit of a CMOS image sensor, as shown in fig. 1, including: the pixel comprises a photodiode and a charge transfer transistor connected with the photodiode, wherein 4 pixels are arranged into a 2 x2 pixel back-to-back array structure, a row selection transistor, a source following transistor, a reset transistor and a floating active region are arranged in each column of pixels, and two pixels in each column share the row selection transistor, the source following transistor, the reset transistor and the floating active region which are arranged in the column;

and the drain electrode of the reset transistor of the first column of pixels, the source electrode of the source following transistor and the drain electrode of the row selection transistor in the second column of pixels are mutually connected.

In the pixel unit, the structure of a 2 × 2 pixel back-to-back array in which 4 pixels are arranged is as follows: the upper pixels of the first column of pixels and the upper pixels of the second column of pixels are in the same row; the lower pixels of the first column of pixels are in the same row as the lower pixels of the second column of pixels.

Can be as follows: the row selection transistor and the source follower transistor of one column of pixels are arranged at the top of the column of pixels, and the row selection transistor and the source follower transistor of the other column of pixels are arranged at the bottom of the column of pixels.

The method specifically comprises the following steps: the row selection transistor and the source following transistor in one column of pixels are arranged at the top of the column of pixels, and the row selection transistor and the source following transistor in the other column of pixels are arranged at the bottom of the column of pixels:

the row selection transistor and the source follower transistor in the first column of pixels are arranged at the top of the column of pixels, and the row selection transistor and the source follower transistor in the second column of pixels are arranged at the bottom of the column of pixels.

In the pixel unit, the drain electrode of the reset transistor and the source electrode of the source following transistor of the first column of pixels are connected with the drain electrode of the row selecting transistor of the second column of pixels through a column metal interconnecting wire. The column metal interconnection lines are used as power supply lines and signal output lines of the first column of pixels and the second column of pixels. Therefore, only one metal wire is adopted in two columns of pixels, a grid time sequence control metal wire of a row selection transistor is omitted, and a power line and a column pixel signal output line share one column metal wire.

In the pixel unit, two pixels in each column share a row selection transistor, a source follower transistor, a reset transistor and a floating active region in the column:

the cathode of the first photodiode of the first pixel in the column is grounded, and the anode is connected with the drain electrode of the first charge transmission transistor;

the cathode of the second photodiode of the second pixel in the column is grounded, and the anode is connected with the drain electrode of the second charge transmission transistor;

the source electrode of the first charge transmission transistor and the source electrode of the second charge transmission transistor are both connected with the source electrode of the reset transistor and the grid electrode of the source following transistor;

the drain of the source follower transistor is connected to the source of the row select transistor.

In the pixel unit, in a first column of pixels, a first pixel in the column is a lower pixel, and a second pixel in the column is an upper pixel;

alternatively, in the second column of pixels, the first pixel in the column is the upper pixel and the second pixel in the column is the lower pixel.

In the pixel unit, the device and wiring structure in the second column of pixels is the same as the structure of the first column of pixels after being turned by 180 degrees relative to the horizontal axis, as shown in fig. 1.

According to the pixel unit of the CMOS image sensor, a row selection transistor grid time sequence control metal wire is omitted between two rows of pixels, and the power line and the row pixel signal output line share one row metal wire, so that the metal window opening rate of the CMOS image sensor is effectively improved, the pixel structure of the CMOS image sensor can improve the light efficiency of a small-area pixel sensor, the sensitivity is improved, and the image quality of the small-area pixel image sensor is effectively improved.

The pixel unit of the CMOS image sensor according to the present invention will be further described with reference to the following embodiments.

Example one

As shown in fig. 1, the pixel unit of the CMOS image sensor of the present embodiment adopts a 4T2S structure, and includes four pixels, wherein the photodiodes of the pixel 11, the pixel 21, the pixel 12, and the pixel 22 are PD11, PD21, PD12, and PD 22; TX11 and TX21 are charge transfer transistors of pixel 11 and pixel 21, respectively, and TX12 and TX22 are charge transfer transistors of pixel 12 and pixel 22, respectively; SX1, SF1, and RX1 are the row select, source follower, and reset transistors of pixel 11 and pixel 21, respectively, for the first column; SX2, SF2, and RX2 are the row select, source follower, and reset transistors of pixel 12 and pixel 22, respectively, for the second column. The pixel 11 and the pixel 21 share the row select transistor SX1, the source follower transistor SF1, the reset transistor RX1, and the floating active region FD1 (floating diffusion), and the pixel 12 and the pixel 22 share the row select transistor SX2, the source follower transistor SF2, the reset transistor RX2, and the floating active region FD 2.

As shown in fig. 1, in the pixel unit, a metal interconnection line T1 is connected with the gates of the charge transfer transistors TX11 and TX12, and a metal interconnection line T2 is connected with the gates of the charge transfer transistors TX21 and TX 22; the metal interconnection line R is connected with the gates of the reset transistors RX1 and RX 2; a metal interconnect S1 is connected to the gate of row select transistor SX2 and a metal interconnect S2 is connected to the gate of row select transistor SX 1. A column metal interconnection line SC1 is connected to the drain of the row select transistor SX1, a column metal interconnection line SC2 is connected to the drain of the reset transistor RX1 and the source of the source follower transistor SF1 of the first column pixel and is also connected to the drain of the row select transistor SX2 of the second column pixel, and a column metal interconnection line SC3 is connected to the drain of the reset transistor RX2 and the source of the source follower transistor SF 2.

In the pixel unit, a pixel 11 and a pixel 21 in a first column and a pixel 12 and a pixel 22 in a second column form a mutual back-to-back structure in the horizontal direction; the row select transistor and source follower transistor of pixel 11 and pixel 21 of the first column are placed on top and the row select transistor and source follower transistor of pixel 12 and pixel 22 of the second column are placed on the bottom. Metal interconnecting lines T1, T2, S1, S2 and R are timing output control lines of the row decoder; metal interconnection lines SC1, SC2, and SC3 are column controller control lines and column signal output lines.

Example two

As shown in fig. 2, an embodiment of the present invention provides a CMOS image sensor, including: the display device comprises a column control device, a row decoder, a signal reading device and a plurality of pixel units connected with the devices, wherein each pixel unit adopts the pixel unit of the first embodiment, and a plurality of groups of pixel units are arranged in the vertical direction and the horizontal direction to form a two-dimensional pixel array.

The CMOS image sensor of the present invention will be further described with reference to specific embodiments.

The image sensor of the present invention is suitable for an m × n two-dimensional pixel array, where m and n may be any positive integer, and this embodiment is described in detail by taking a 6 × 6 pixel array as an example. Fig. 2 is a schematic diagram of a CMOS image sensor circuit exemplified by a 6 × 6 pixel array, which includes a two-dimensional pixel array section, a row decoder 201, a column control device 202 and a column pixel signal reading device 203, and a processing circuit, a memory element, and a read-in and read-out circuit 204. The row decoder 201 is placed to the left of the pixel array (or to the right of the array), the column control device 202 is placed at the top of the pixel array (or to the bottom of the array), and the column pixel signal readout device 203 is placed at the bottom of the pixel array; the locations of the decoder, controller and signal sensing devices are not the only way in which the present invention can be implemented, and may be adjusted according to the specific design layout of the chip.

In fig. 2, PD11 to PD16 are photodiodes of pixels in row 1, PD21 to PD26 are photodiodes of pixels in row 2, PD31 to PD36 are photodiodes of pixels in row 3, PD41 to PD46 are photodiodes of pixels in row 4, PD51 to PD56 are photodiodes of pixels in row 5, and PD61 to PD66 are photodiodes of pixels in row 6; TX 11-TX 16 are charge transfer transistors of pixels in a 1 st row, TX 21-TX 26 are charge transfer transistors of pixels in a 2 nd row, TX 31-TX 36 are charge transfer transistors of pixels in a 3 rd row, TX 41-TX 46 are charge transfer transistors of pixels in a 4 th row, TX 51-TX 56 are charge transfer transistors of pixels in a 5 th row, and TX 61-TX 66 are charge transfer transistors of pixels in a 6 th row; SX 21-SX 26, SF 21-SF 26, and RX 21-RX 26 are row select transistors, source follower transistors, and reset transistors located in the 1 st and 2 nd row pixels, SX 41-SX 46, SF 41-SF 46, and RX 41-RX 46 are row select transistors, source follower transistors, and reset transistors located in the 3 rd and 4 th row pixels, and SX 61-SX 66, SF 61-SF 66, and RX 61-RX 66 are row select transistors, source follower transistors, and reset transistors located in the 5 th and 6 th row pixels, respectively.

In fig. 2, a metal interconnection line T1 is connected to gates of TX11 to TX16, a metal interconnection line T2 is connected to gates of TX21 to TX26, a metal interconnection line T3 is connected to gates of TX31 to TX36, a metal interconnection line T4 is connected to gates of TX41 to TX46, a metal interconnection line T5 is connected to gates of TX51 to TX56, and a metal interconnection line T6 is connected to gates of TX61 to TX 66; the metal interconnection line R2 is connected with the gates of RX 21-RX 26, the metal interconnection line R4 is connected with the gates of RX 41-RX 46, and the metal interconnection line R6 is connected with the gates of RX 61-RX 66; metal interconnection lines S0 are connected to the gates of SX22, SX24 and SX26, metal interconnection lines S2 are connected to the gates of SX21, SX23 and SX25 and to the gates of SX42, SX44 and SX46, metal interconnection lines S4 are connected to the gates of SX41, SX43 and SX45 and to the gates of SX62, SX64 and SX66, and metal interconnection lines S6 are connected to the gates of SX61, SX63 and SX 65. The metal interconnection line SC0 is connected with the drains of SX21, SX41 and SX61 of the first column of pixels, and the metal interconnection line SC1 is connected with the drains of RX21, RX41 and RX61 of the 1 st column of pixels and the sources of SF21, SF41 and SF61 and is simultaneously connected with the drains of SX22, SX42 and SX62 of the 2 nd column of pixels; the metal interconnecting wire SC2 is connected with the drains of RX22, RX42 and RX62 of the second column of pixels and the sources of SF22, SF42 and SF62 and is simultaneously connected with the drains of SX23, SX43 and SX63 of the third column of pixels; the metal interconnecting wire SC3 is connected with the drains of RX23, RX43 and RX63 of the third column of pixels and the sources of SF23, SF43 and SF63 and is simultaneously connected with the drains of SX24, SX44 and SX64 of the fourth column of pixels; the metal interconnection wire SC4 is connected with the drains of RX24, RX44 and RX64 of the fourth column of pixels and the sources of SF24, SF44 and SF64 of the fourth column of pixels and is simultaneously connected with the drains of SX25, SX45 and SX65 of the fifth column of pixels; the metal interconnection wire SC5 is connected with the drains of RX25, RX45 and RX65 of the fifth column of pixels and the sources of SF25, SF45 and SF65 and is simultaneously connected with the drains of SX26, SX46 and SX66 of the sixth column of pixels; the metal interconnection line SC6 is connected to the drains of RX26, RX46 and RX66 of the sixth column of pixels and the sources of SF26, SF46 and SF 66.

Row metal interconnection lines T1 to T6, S0, S2, S4, S6, R2, R4, and R6 are control lines of the row decoder 201, and control lines SC0 to SC6 which are the column controllers 202 are also column pixel signal output lines; after being read and stored by the signal reading device 203 through the row pixel signal output line, the photoelectric signals of the image sensor pixel array enter the processing circuit of the next circuit module, the memory element and the read-in and read-out circuit 204 for further processing. The control timing of the pixel array of the CMOS image sensor provided by the present invention is shown in fig. 3.

The CMOS image sensor of the present invention will be further described with reference to the array signal acquisition process of the CMOS image sensor of this embodiment:

FIG. 3 is a schematic diagram showing the output timing of the row decoder and the timing of the column controller used in the pixel array of the CMOS image sensor of the present invention, in which all N-type transistors are used, and the gate of the N-type transistor is set to high level, i.e. the timing line for controlling the gate of the transistor is set to high level, indicating that the transistor is turned on; setting the grid of the N-type transistor to be at a low level, namely setting a time sequence line for controlling the grid of the transistor to be at the low level, and indicating that the transistor is closed; the on time of the N-type transistor is short, namely the time length of a time sequence line for controlling the grid electrode of the transistor is high level, and is determined by the specific working condition of the sensor; when the signal reading device at the bottom of the pixel array reads signals, the SC line is converted into a signal output line by the timing control line of the column controller, and the signal reading device reads the signals through the signal output line. In fig. 3, SC0, 2, 4, 6 and SC1, 3, 5 indicate that the SC line potential is controlled by the column control device when the timing is a solid line, and indicate that the SC line is converted into a column pixel signal output line when the timing is a dotted line; when the SHR and the SHS are at a high level, the representations respectively read the reset signal 1 and the photoelectric signal 2 of the column pixels, and the pixel real photoelectric signal is the reset signal 1-the photoelectric signal 2, wherein the SHR and the SHS respectively read the signals of the pixels at odd columns (the first, the third, and the fifth columns of pixels) and then respectively read the signals of the pixels at even columns (the second, the fourth, and the sixth columns of pixels).

When the CMOS image sensor pixel array works normally, a row rolling type exposure mode is adopted, pixels of a 1 st row begin to be exposed firstly, pixels of a 2 nd row begin to be exposed, and then pixels of a 3 rd row, a 4 th row, a 5 th row and a 6 th row are formed; the sequence of the end of exposure between the pixels of the rows is the same as the sequence of the start of exposure; the signal reading sequence between the rows of pixels is also the same as the sequence in which the row of pixels is exposed to light. When the sensor collects the pixel array signals of the same frame, the exposure time of each row of pixels is equal.

The following is a detailed description of the timing operation of the row 3 pixels. The R4 and T3 timings are simultaneously pulsed high before the pixel exposure period begins, to clear all the charges in the photodiodes of the pixels in row 3, which are exposed from the falling edge of the T3 pulse. Before the exposure is finished, the SC0, 2, 4, 6 and SC1, 3, 5 are at the ground potential, and the timings R2 and R6 perform a high-level pulse operation to set the pixel FD, which is not read out, to a low potential; after the pixel FD which is not read out by the signal is set to be low potential, SC0, 2, 4, 6 and SC1, 3, 5 are converted into power supply potential, a time sequence R4 performs a high level pulse operation to reset the pixel FD of the 3 rd row read out by the signal to be high potential, then SC1, 3, 5 are converted into a row pixel signal read out line, a time sequence S4 turns on a row selection transistor of the odd-numbered row pixels from low potential to high potential, an SHR time sequence performs a high level pulse operation to read the reset signal 1 of the odd-numbered row pixels, and then S4 is set to be low potential; subsequent switching of SC1, 3, 5 to the power supply potential and switching of SC0, 2, 4, 6 to the column pixel signal readout line, timing S2 turns on the row select transistors of the even column pixels from low to high, reads the even column pixel reset signal 1, and then sets S2 to low. After the even-column pixel reset signal 1 is read, the SC0, 2, 4, 6 is converted into a power supply potential and the SC1, 3, 5 is converted into a column pixel signal read-out line, the T3 performs a high-level pulse operation to transfer photoelectric charges in the photodiode of the 3 rd row pixel to the corresponding pixel FD region, the pixel exposure is finished, then the timing S4 turns on the row selection transistor of the odd-column pixel from a low-level to a high-level, the SHS performs a high-level pulse operation to read the photoelectric signal 2 of the odd-column pixel, and the S4 is set to a low-level; following the transition of SC1, 3, 5 to the power supply potential and SC0, 2, 4, 6 to the column pixel signal readout lines, timing S2 turns on the row select transistors of the even column pixels from a low to a high potential, reads the even column pixel photo signal 2, and sets S2 to a low potential.

The above time sequence operation is only the time sequence operation of 1 row of pixels in the pixel array, and after the above operations are sequentially completed by all the rows of pixels in the pixel array, the reading of one frame of signal of the image sensor is completed.

According to the invention, because metal interconnection lines are saved, the metal window opening rate is improved, and the problem of low small-area pixel sensitivity of the conventional image sensor is well solved.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.