CN103267579A - Detection circuit of line control circuit of infrared focal plane reading circuit - Google Patents
- ️Wed Aug 28 2013
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- CN103267579A CN103267579A CN2013101523628A CN201310152362A CN103267579A CN 103267579 A CN103267579 A CN 103267579A CN 2013101523628 A CN2013101523628 A CN 2013101523628A CN 201310152362 A CN201310152362 A CN 201310152362A CN 103267579 A CN103267579 A CN 103267579A Authority
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Abstract
The invention discloses a detection circuit of a line control circuit of an infrared focal plane reading circuit. The detection circuit comprises a unit gain operation amplifier and a testing circuit. The unit gain operation amplifier comprises an inverted input end, a first in-phase input end, a second in-phase input end and an output end, wherein the first in-phase input end is connected with a detecting circuit of the infrared focal plane reading circuit. The testing circuit is connected with the second in-phase input end of the unit gain operation amplifier. The detection circuit can detect the reading circuit before sensitive picture elements are made through infrared focal plane arrays, unqualified circuits are screened out, and manufacturing cost of the infrared focal plane arrays is saved. When normal work is carried out after the sensitive picture elements are made, the fact that the second in-phase input end does not affect normal work of the unit gain operation amplifier can be guaranteed, and performance attenuation cannot be caused.
Description
技术领域 technical field
本发明涉及红外焦平面阵列探测器的读出电路，尤其涉及一种红外焦平面读出电路的行控制电路的检测电路。 The invention relates to a readout circuit of an infrared focal plane array detector, in particular to a detection circuit of a row control circuit of an infrared focal plane readout circuit.
背景技术 Background technique
目前红外成像系统在军事、空间技术、医学以及国民经济相关领域正得到日益广泛的应用。红外焦平面阵列组件是红外成像技术中获取红外图像信号的核心光电器件。红外焦平面阵列组件由红外探测器和红外焦平面读出电路（ROIC：readout integrated circuits）组成。随着红外焦平面阵列组件规模的不断扩大，作为其重要组成部分的红外焦平面读出电路需要满足更高的工作性能。 At present, infrared imaging systems are being increasingly widely used in military, space technology, medicine and national economy related fields. The infrared focal plane array component is the core optoelectronic device for obtaining infrared image signals in infrared imaging technology. The infrared focal plane array component consists of an infrared detector and an infrared focal plane readout circuit (ROIC: readout integrated circuits). With the continuous expansion of the scale of infrared focal plane array components, the infrared focal plane readout circuit, which is an important part of it, needs to meet higher working performance.
ROIC电路是把红外焦平面的各种功能集成在单一的半导体芯片中的高集成度电路，其基本功能是进行红外探测器信号的转换、放大以及传输，即将数据从许多红外探测器端依次传输到输出端。常见的ROIC电路包括单元电路、列读出级和输出缓冲级、时序产生电路、行选择电路和列选择电路。行选择电路是ROIC电路的重要组成部分，它的性能好坏直接影响整个读出电路的性能。 The ROIC circuit is a highly integrated circuit that integrates various functions of the infrared focal plane into a single semiconductor chip. Its basic function is to convert, amplify, and transmit infrared detector signals, that is, to transmit data sequentially from many infrared detector terminals. to the output. Common ROIC circuits include cell circuits, column readout stages and output buffer stages, timing generation circuits, row selection circuits, and column selection circuits. The row selection circuit is an important part of the ROIC circuit, and its performance directly affects the performance of the entire readout circuit.
在红外读出电路制作完成以后，红外敏感单元阵列制作以前，对红外读出电路进行检测是必要的，这样可以提高红外探测器的成品率，节约成本和时间。 After the infrared readout circuit is fabricated and before the infrared sensitive unit array is fabricated, it is necessary to detect the infrared readout circuit, which can improve the yield of infrared detectors and save cost and time.
红外敏感单元阵列制作以前，红外读出电路的数字电路可以通过测试信号控制选择相应的信号输入进行检测。但是红外焦平面阵列读出电路的模拟电路在红外敏感单元阵列制作以前却很难检测，因为电路不完整，输出为随机信号。 Before the infrared sensitive unit array is manufactured, the digital circuit of the infrared readout circuit can select the corresponding signal input for detection by controlling the test signal. However, the analog circuit of the infrared focal plane array readout circuit is difficult to detect before the infrared sensitive unit array is produced, because the circuit is incomplete and the output is a random signal.
发明内容 Contents of the invention
本发明的目的之一是提供一种能够检测红外焦平面阵列读出电路的红外焦平面读出电路的行控制电路的检测电路。 One of the objects of the present invention is to provide a detection circuit capable of detecting the row control circuit of the infrared focal plane readout circuit of the infrared focal plane array readout circuit.
本发明实施例公开的技术方案包括： The technical solutions disclosed in the embodiments of the present invention include:
提供了一种红外焦平面读出电路的行控制电路的检测电路，其特征在于，包括：单位增益运算放大器10，所述单位增益运算放大器10包括反相输入端、第一同相输入端、第二同相输入端和输出端，所述反相输入端连接到所述输出端，所述第一同相输入端连接到所述红外焦平面读出电路的探测电路；测试电路20，所述测试电路20连接到所述单位增益运算放大器10的第二同相输入端。 A detection circuit of a row control circuit of an infrared focal plane readout circuit is provided, which is characterized in that it includes: a unit gain operational amplifier 10, and the unit gain operational amplifier 10 includes an inverting input terminal, a first non-inverting input terminal, The second noninverting input terminal and output terminal, the inverting input terminal is connected to the output terminal, the first noninverting input terminal is connected to the detection circuit of the infrared focal plane readout circuit; test circuit 20, the described A test circuit 20 is connected to the second non-inverting input of the unity gain operational amplifier 10 .
进一步地，所述单位增益运算放大器包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6，其中：所述第一晶体管M1的栅极连接到所述第一同相输入端，漏极连接到所述第四晶体管M4的漏极，源极连接到所述第六晶体管M6的漏极；所述第二晶体管M2的栅极连接到所述反相输入端，漏极连接到所述第五晶体管M5的漏极，源极连接到所述第六晶体管M6的漏极；所述第三晶体管M3的栅极连接到所述第二同相输入端，漏极连接到所述第四晶体管M4的漏极，源极连接到所述第六晶体管M6的漏极；所述第四晶体管M4的源极连接到系统电源，栅极连接到所述第五晶体管M5的栅极并且连接到所述第四晶体管M4的漏极；所述第五晶体管M5的源极连接到系统电源，漏极连接到所述输出端；所述第六晶体管M6的源极接地，栅极连接到电流端口（Vnbias）。 Further, the unity-gain operational amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6, wherein: the gate of the first transistor M1 The pole is connected to the first non-inverting input terminal, the drain is connected to the drain of the fourth transistor M4, and the source is connected to the drain of the sixth transistor M6; the gate of the second transistor M2 is connected to To the inverting input terminal, the drain is connected to the drain of the fifth transistor M5, the source is connected to the drain of the sixth transistor M6; the gate of the third transistor M3 is connected to the first Two non-inverting input terminals, the drain is connected to the drain of the fourth transistor M4, the source is connected to the drain of the sixth transistor M6; the source of the fourth transistor M4 is connected to the system power supply, and the gate is connected to to the gate of the fifth transistor M5 and connected to the drain of the fourth transistor M4; the source of the fifth transistor M5 is connected to the system power supply, and the drain is connected to the output terminal; the sixth Transistor M6 has its source connected to ground and its gate connected to the current port (Vnbias).
进一步地，还包括积分电路30和采样保持电路40，所述积分电路30连接到所述单位增益运算放大器10的输出端，所述采样保持电路40连接到所述积分电路30的输出端。 Further, it also includes an integration circuit 30 and a sample-and-hold circuit 40 , the integration circuit 30 is connected to the output terminal of the unity-gain operational amplifier 10 , and the sample-and-hold circuit 40 is connected to the output terminal of the integration circuit 30 .
本发明的实施例中，检测电路可以在红外焦平面阵列制作敏感像元之前对读出电路进行检测，筛选出不合格的电路，节省红外焦平面阵列的制作成本。在制作敏感像元后正常工作时，又可以保证测试输入端（即单位增益运算放大器的第二同相输入端）不影响单位增益运算放大器的正常工作，即不会带来性能上的衰减。 In the embodiment of the present invention, the detection circuit can detect the readout circuit before making the sensitive pixel of the infrared focal plane array, and screen out unqualified circuits, saving the manufacturing cost of the infrared focal plane array. When working normally after making sensitive pixels, it can also ensure that the test input (that is, the second non-inverting input of the unity-gain operational amplifier) does not affect the normal operation of the unity-gain operational amplifier, that is, it will not cause performance degradation.
附图说明 Description of drawings
图1是本发明一个实施例的红外焦平面读出电路的行控制电路的检测电路的示意图。 FIG. 1 is a schematic diagram of a detection circuit of a row control circuit of an infrared focal plane readout circuit according to an embodiment of the present invention.
图2是本发明一个实施例的单位增益运算放大器的结构示意图。 FIG. 2 is a schematic structural diagram of a unity-gain operational amplifier according to an embodiment of the present invention.
图3是本发明一个实施例的检测电路在测试时的信号流示意图。 FIG. 3 is a schematic diagram of the signal flow of the detection circuit during testing according to an embodiment of the present invention.
图4是本发明一个实施例的检测电路在正常工作时的信号流示意图。 Fig. 4 is a schematic diagram of the signal flow of the detection circuit in one embodiment of the present invention when it works normally.
具体实施方式 Detailed ways
下面将参考附图详细说明本发明的实施例。 Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
图1为本发明一个实施例的红外焦平面读出电路的行控制电路的检测电路的结构示意图。 FIG. 1 is a schematic structural diagram of a detection circuit of a row control circuit of an infrared focal plane readout circuit according to an embodiment of the present invention.
如图1所示，本发明的一个实施例中，一种红外焦平面读出电路的行控制电路的检测电路包括单位增益运算放大器10。该单位增益运算放大器10包括反相输入端inn、第一同相输入端inp、第二同相输入端inp_ts和输出端，其中反相输入端inn连接到输出端，构成负反馈。 As shown in FIG. 1 , in an embodiment of the present invention, a detection circuit of a row control circuit of an infrared focal plane readout circuit includes a unit gain operational amplifier 10 . The unity gain operational amplifier 10 includes an inverting input terminal inn, a first non-inverting input terminal inp, a second non-inverting input terminal inp_ts and an output terminal, wherein the inverting input terminal inn is connected to the output terminal to form a negative feedback.
本发明的实施例中，第一同相输入端inp作为红外焦平面阵列读出电路正常工作时来自于红外焦平面阵列的信号的输入端口，因此该第一同相输入端inp连接到探测电路100，该探测电路100用于正常工作时从红外焦平面阵列中探测获得正常的信号。探测电路100可以使用本领域内常用的探测电路结构，在此不再详述。而且，可以理解，探测电路100不属于本发明的检测电路的部分。 In the embodiment of the present invention, the first in-phase input terminal inp is used as the input port of the signal from the infrared focal plane array when the infrared focal plane array readout circuit works normally, so the first in-phase input terminal inp is connected to the detection circuit 100, the detection circuit 100 is used to detect and obtain normal signals from the infrared focal plane array during normal operation. The detection circuit 100 may use a common detection circuit structure in the art, which will not be described in detail here. Furthermore, it is understood that the detection circuit 100 is not part of the detection circuit of the present invention.
本发明的实施例中，检测电路还包括测试电路20，该测试电路20连接到单位增益运算放大器10的第二同相输入端inp_ts。测试电路20可以接收测试信号。在红外焦平面阵列的制造过程中，在制造红外敏感元件之前，使用该测试电路20接收测试信号，测试信号从第二同相输入端inp_ts输入单位增益运算放大器10，对电路进行检测。本发明的实施例中，测试电路20可以是本领域内常用的可以接收测试信号的电路，其结构在此不再详述。 In the embodiment of the present invention, the detection circuit further includes a test circuit 20 connected to the second non-inverting input terminal inp_ts of the unity gain operational amplifier 10 . The test circuit 20 may receive a test signal. In the manufacturing process of the infrared focal plane array, before the infrared sensitive element is manufactured, the test circuit 20 is used to receive a test signal, and the test signal is input into the unity gain operational amplifier 10 from the second non-inverting input terminal inp_ts to test the circuit. In the embodiment of the present invention, the test circuit 20 may be a circuit commonly used in the art and capable of receiving test signals, and its structure will not be described in detail here.
如图1所示，本发明的实施例中，还可以包括积分电路30和采样保持电路40。积分电路30连接到单位增益运算放大器10的输出端，采样保持电路40连接到积分电路30的输出端。这样，信号从单位增益运算放大器10的输出端输出之后，经过积分电路30和采样保持电路40后输出。 As shown in FIG. 1 , in the embodiment of the present invention, an integration circuit 30 and a sample-and-hold circuit 40 may also be included. The integrating circuit 30 is connected to the output terminal of the unity-gain operational amplifier 10 , and the sample-and-hold circuit 40 is connected to the output terminal of the integrating circuit 30 . In this way, after the signal is output from the output terminal of the unity gain operational amplifier 10 , it is output after passing through the integrating circuit 30 and the sample and hold circuit 40 .
图2是本发明一个实施例的单位增益运算放大器10的结构示意图。 FIG. 2 is a schematic structural diagram of a unity-gain operational amplifier 10 according to an embodiment of the present invention.
如图2所示，单位增益运算放大器10包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6。 As shown in FIG. 2 , the unity gain operational amplifier 10 includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 and a sixth transistor M6 .
第一晶体管M1的栅极连接到第一同相输入端inp，漏极连接到第四晶体管M4的漏极，源极连接到第六晶体管M6的漏极。 The gate of the first transistor M1 is connected to the first non-inverting input terminal inp, the drain is connected to the drain of the fourth transistor M4, and the source is connected to the drain of the sixth transistor M6.
第二晶体管M2的栅极连接到反相输入端inn，漏极连接到第五晶体管M5的漏极，源极连接到第六晶体管M6的漏极。 The gate of the second transistor M2 is connected to the inverting input terminal inn, the drain is connected to the drain of the fifth transistor M5, and the source is connected to the drain of the sixth transistor M6.
第三晶体管M3的栅极连接到第二同相输入端inp_ts，漏极连接到第四晶体管M4的漏极，源极连接到第六晶体管M6的漏极。 The gate of the third transistor M3 is connected to the second non-inverting input terminal inp_ts, the drain is connected to the drain of the fourth transistor M4, and the source is connected to the drain of the sixth transistor M6.
第四晶体管M4的源极连接到系统电源Vdd，栅极连接到第五晶体管M5的栅极并且连接到第四晶体管M4的漏极。 The source of the fourth transistor M4 is connected to the system power supply V dd , the gate is connected to the gate of the fifth transistor M5 and to the drain of the fourth transistor M4 .
第五晶体管M5的源极连接到系统电源Vdd，漏极连接到输出端out。 The source of the fifth transistor M5 is connected to the system power supply V dd , and the drain is connected to the output terminal out.
第六晶体管M6的源极接地，栅极连接到Vnbias。 The source of the sixth transistor M6 is grounded, and the gate is connected to Vnbias.
图3是本发明一个实施例的检测电路在测试时的信号流的示意图，图4是本发明一个实施例的检测电路在正常工作时的信号流的示意图。 FIG. 3 is a schematic diagram of the signal flow of the detection circuit of an embodiment of the present invention during testing, and FIG. 4 is a schematic diagram of the signal flow of the detection circuit of an embodiment of the present invention during normal operation.
如图3所示，在制作敏感像元之前检测电路时，测试电路20通过第二同相输入端inp_ts输入测试信号，改变单位增益运算放大器10的输出，从而影响读出电路的输出，以检测电路。信号依次流过测试电路20、单位增益运算放大器10、积分电路30和采样保持电路40，最终输出。 As shown in Figure 3, when testing the circuit before making the sensitive pixel, the test circuit 20 inputs a test signal through the second non-inverting input terminal inp_ts to change the output of the unity gain operational amplifier 10, thereby affecting the output of the readout circuit to test the circuit . The signal flows through the test circuit 20 , the unity gain operational amplifier 10 , the integration circuit 30 and the sample-and-hold circuit 40 in sequence, and is finally output.
如图4所示，在敏感像元制造完成后正常工作时，测试电路20可以保证第二同相输入端inp_ts不影响单位增益运算放大器10正常工作。信号依次流过探测电路100、单位增益运算放大器10、积分电路30和采样保持电路40，最终输出。 As shown in FIG. 4 , the test circuit 20 can ensure that the second non-inverting input terminal inp_ts does not affect the normal operation of the unity-gain operational amplifier 10 when the sensitive pixel works normally after manufacturing. The signal flows through the detection circuit 100 , the unity gain operational amplifier 10 , the integration circuit 30 and the sample-and-hold circuit 40 in sequence, and is finally output.
在图2的实施例中，在测试时，测试电路使第二同相输入端的电压Vinp_ts保持一定的高电位（如：Vinp_ts>VP+VT），确保第三晶体管M3导通，从而满足图3所示信号流。其中VP是图2中点P处的电压，VT是第三晶体管的阈值电压。 In the embodiment of FIG. 2 , during the test, the test circuit keeps the voltage V inp_ts of the second non-inverting input terminal at a certain high potential (for example: V inp_ts >V P +V T ), to ensure that the third transistor M3 is turned on, thereby Satisfy the signal flow shown in Figure 3. Where V P is the voltage at point P in Figure 2, and V T is the threshold voltage of the third transistor.
在正常工作时，测试电路使Vinp_ts保持一定的低电位（如：Vinp_ts<VP+VT），确保第三晶体管M3关闭，从而满足图4所示信号流。 During normal operation, the test circuit keeps V inp_ts at a certain low potential (for example: V inp_ts <V P +V T ) to ensure that the third transistor M3 is turned off, thereby satisfying the signal flow shown in FIG. 4 .
当单位增益运算放大器10的结构改变时，测试电路对于Vinp_ts的控制也应相应改变。 When the structure of the unity-gain operational amplifier 10 is changed, the control of V inp_ts by the test circuit should also be changed accordingly.
本发明的实施例中，测试电路可以是直接接受外接模拟电平，也可以是接收外部数字信号在由内部数模转换器（DAC）产生所需模拟电平，或是其它任何满足需求的电路。 In the embodiment of the present invention, the test circuit can directly accept an external analog level, or receive an external digital signal and generate the required analog level by an internal digital-to-analog converter (DAC), or any other circuit that meets the requirements .
本发明的实施例中，检测电路可以在红外焦平面阵列制作敏感像元之前对读出电路进行检测，筛选出不合格的电路，节省红外焦平面阵列的制作成本。在制作敏感像元后正常工作时，又可以保证测试输入端（即单位增益运算放大器的第二同相输入端）不影响单位增益运算放大器的正常工作，即不会带来性能上的衰减。 In the embodiment of the present invention, the detection circuit can detect the readout circuit before making the sensitive pixel of the infrared focal plane array, and screen out unqualified circuits, saving the manufacturing cost of the infrared focal plane array. When working normally after making sensitive pixels, it can also ensure that the test input (that is, the second non-inverting input of the unity-gain operational amplifier) does not affect the normal operation of the unity-gain operational amplifier, that is, it will not cause performance degradation.
以上通过具体的实施例对本发明进行了说明，但本发明并不限于这些具体的实施例。本领域技术人员应该明白，还可以对本发明做各种修改、等同替换、变化等等，这些变换只要未背离本发明的精神，都应在本发明的保护范围之内。此外，以上多处所述的“一个实施例”表示不同的实施例，当然也可以将其全部或部分结合在一个实施例中。 The present invention has been described above through specific examples, but the present invention is not limited to these specific examples. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present invention. As long as these changes do not deviate from the spirit of the present invention, they should all be within the protection scope of the present invention. In addition, "one embodiment" described in many places above represents different embodiments, and of course all or part of them may be combined in one embodiment.
Claims (3)
1. the testing circuit of the line control circuit of an infrared focal plane read-out circuit is characterized in that, comprising:
Unity gain operational amplifier (10), described unity gain operational amplifier (10) comprises inverting input, first in-phase input end, second in-phase input end and output terminal, described inverting input is connected to described output terminal, and described first in-phase input end is connected to the detection circuit of described infrared focal plane read-out circuit;
Test circuit (20), described test circuit (20) is connected to second in-phase input end of described unity gain operational amplifier (10).
2. testing circuit as claimed in claim 1, it is characterized in that, described unity gain operational amplifier (10) comprises the first transistor (M1), transistor seconds (M2), the 3rd transistor (M3), the 4th transistor (M4), the 5th transistor (M5) and the 6th transistor (M6), wherein:
The grid of described the first transistor (M1) is described first in-phase input end, and drain electrode is connected to the drain electrode of described the 4th transistor (M4), and source electrode is connected to the drain electrode of described the 6th transistor (M6);
The grid of described transistor seconds (M2) is described inverting input, and drain electrode is connected to the drain electrode of described the 5th transistor (M5), and source electrode is connected to the drain electrode of described the 6th transistor (M6);
The grid of described the 3rd transistor (M3) is described second in-phase input end, and drain electrode is connected to the drain electrode of described the 4th transistor (M4), and source electrode is connected to the drain electrode of described the 6th transistor (M6);
The source electrode of described the 4th transistor (M4) is connected to system power supply, and grid is connected to the grid of described the 5th transistor (M5) and is connected to the drain electrode of described the 4th transistor (M4);
The source electrode of described the 5th transistor (M5) is connected to system power supply, drains to be described output terminal;
The source ground of described the 6th transistor (M6), grid are connected to electric current port (Vnbias).
3. as claim 1 or 2 described testing circuits, it is characterized in that: also comprise integrating circuit (30) and sampling hold circuit (40), described integrating circuit (30) is connected to the output terminal of described unity gain operational amplifier (10), and described sampling hold circuit (40) is connected to the output terminal of described integrating circuit (30).
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| CN2013101523628A CN103267579A (en) | 2013-04-27 | 2013-04-27 | Detection circuit of line control circuit of infrared focal plane reading circuit |
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| CN2013101523628A CN103267579A (en) | 2013-04-27 | 2013-04-27 | Detection circuit of line control circuit of infrared focal plane reading circuit |
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