CN103365815A - SD card interface supporting IP implementation under SD mode - Google Patents

一种支持SD模式下IP实现的SD存储卡接口，连接在主控系统和Flash控制器之间，可以对Flash进行读写操作，包括：命令收发模块，负责接收主控命令将其解析为SD卡命令，送往状态控制模块和校验模块，并根据状态控制模块给出的响应类型产生对应的响应内容进行回复；数据收发模块，负责数据的接收与发送；状态控制模块，负责接口状态控制；校验模块，负责命令与数据的完整性校验，本发明支持SD2.0物理层规范的基本命令，能自动解析主机发送的命令并响应，为了解决数据存取的时序问题使用了数据缓存技术，本发明可以在不同集成电路工艺下方便地移植，而且可以在FPGA平台上运行，方便的应用在SOC芯片中，减少了设计成本和研发周期。

An SD memory card interface that supports IP implementation in SD mode, connected between the main control system and the Flash controller, can read and write Flash, including: command transceiver module, responsible for receiving the main control command and parsing it into SD The card command is sent to the status control module and the verification module, and the corresponding response content is generated according to the response type given by the status control module to reply; the data sending and receiving module is responsible for receiving and sending data; the status control module is responsible for interface status control The verification module is responsible for the integrity verification of commands and data. The present invention supports the basic commands of the SD2.0 physical layer specification, and can automatically analyze the commands sent by the host and respond. In order to solve the timing problem of data access, data cache is used technology, the present invention can be conveniently transplanted under different integrated circuit technologies, and can run on the FPGA platform, and is conveniently applied in the SOC chip, reducing the design cost and the research and development cycle.

支持SD模式下IP实现的SD存储卡接口Support SD memory card interface implemented by IP in SD mode

技术领域technical field

本发明涉及嵌入式SOC芯片设计中的接口技术领域，尤其涉及到SD卡接口技术，具体涉及一种支持SD模式下IP实现的SD存储卡接口。The invention relates to the field of interface technology in embedded SOC chip design, in particular to SD card interface technology, in particular to an SD memory card interface supporting IP implementation in SD mode.

背景技术Background technique

随着便携式数码产品的广泛应用，消费电子设备中对非易失性存储卡的需求越来越大。非易失性存储卡包括SD(Secure Digital)卡,MMC卡，CF卡记忆棒等。其中SD卡具有高记忆容量，快速数据传输率，极大的移动灵活性以及很好的安全性，成本相对便宜的特点，因此被广泛应用在PC机、相机、手机等视频音频设备上。SD卡是“安全数码存储卡”的简称，于1999年8月由美国SanDisk公司、日本东芝和松下公司共同开发研制成功。为了保证不同厂家设计的SD卡的兼容性，制定了SD卡标准通信协议，管脚分布，电气特性等。从整个市场的规模和趋势看，SD卡的应用范围广阔，发展空间很大，带有SD接口的设备会更便捷地应用于各个领域，SD接口的设计和开发也成为热点问题。With the wide application of portable digital products, the demand for non-volatile memory cards in consumer electronic devices is increasing. Non-volatile memory cards include SD (Secure Digital) cards, MMC cards, CF cards, memory sticks, etc. Among them, SD card has the characteristics of high memory capacity, fast data transmission rate, great mobile flexibility, good security, and relatively cheap cost, so it is widely used in video and audio equipment such as PCs, cameras, and mobile phones. SD card is the abbreviation of "Secure Digital Memory Card". It was successfully developed in August 1999 by SanDisk Corporation of the United States, Toshiba Corporation of Japan and Panasonic Corporation of Japan. In order to ensure the compatibility of SD cards designed by different manufacturers, the SD card standard communication protocol, pin distribution, electrical characteristics, etc. have been formulated. Judging from the scale and trend of the entire market, SD cards have a wide range of applications and great room for development. Devices with SD interfaces will be more conveniently used in various fields, and the design and development of SD interfaces has also become a hot issue.

目前市场上对于SD卡控制器的设计较多，但是对于SD卡接口的设计很少。并且目前Flash芯片种类多样，很难实现通用性的存储设计。At present, there are many designs for SD card controllers in the market, but few designs for SD card interfaces. Moreover, there are various types of Flash chips at present, and it is difficult to realize a universal storage design.

发明内容Contents of the invention

为了克服上述现有技术的缺点，本发明的目的在于提供一种支持SD模式下IP实现的SD存储卡接口，符合SD标准，能够在SD主控设备下完成数据读写操作，并且具有较强的灵活性。In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of SD memory card interface that supports IP realization under SD mode, conforms to SD standard, can finish data reading and writing operation under SD main control equipment, and has stronger flexibility.

为了实现上述目的，本发明采用的技术方案是：In order to achieve the above object, the technical scheme adopted in the present invention is:

支持SD模式下IP实现的SD存储卡接口，连接在主控系统和Flash控制器之间，包括：Support the SD memory card interface implemented by IP in SD mode, connected between the main control system and the Flash controller, including:

命令收发模块，包括命令接收模块和命令响应模块，命令接收模块接收主控命令将其解析为SD卡命令，送往状态控制模块和校验模块，命令响应模块根据状态控制模块给出的响应类型产生对应的响应内容进行回复；The command sending and receiving module includes a command receiving module and a command response module. The command receiving module receives the main control command and parses it into an SD card command, and sends it to the status control module and the verification module. The command response module is based on the response type given by the status control module. Generate corresponding response content to reply;

数据收发模块，包括数据接收模块和数据发送模块，数据接收模块负责数据的接收，数据发送模块负责数据的发送；The data transceiver module includes a data receiving module and a data sending module, the data receiving module is responsible for receiving data, and the data sending module is responsible for sending data;

状态控制模块，负责接口状态控制；State control module, responsible for interface state control;

校验模块，包括设置于命令接收模块和命令响应模块之间负责命令完整性校验的命令校验模块以及设置于数据接收模块和数据发送模块之间负责命令完整性校验的数据校验模块。The verification module includes a command verification module arranged between the command receiving module and the command response module for command integrity verification and a data verification module arranged between the data receiving module and the data sending module for command integrity verification .

所述命令收发模块接收来自SD卡物理层的标准命令，解析得到6位命令索引、32位命令参数和CRC7校验位，将得到的参数传给状态控制模块和校验模块，响应时根据状态控制模块给出的响应类型，产生对应的响应内容，然后发送出去。The command transceiver module receives the standard command from the physical layer of the SD card, parses and obtains 6-bit command index, 32-bit command parameter and CRC7 check bit, and passes the obtained parameter to the state control module and the check module, and responds according to the status Control the response type given by the module, generate the corresponding response content, and then send it out.

所述响应内容包括R1、R1b、R2、R3、R6、R7六种，其中R1、R1b、R3、R6、R7为6字节长度，R2为17字节长度，用于读取SD卡的CID/CSD寄存器内容。The response content includes six types of R1, R1b, R2, R3, R6, and R7, wherein R1, R1b, R3, R6, and R7 are 6 bytes in length, and R2 is 17 bytes in length, which are used to read the CID of the SD card /CSD register contents.

所述状态控制模块根据命令收发模块传送的命令编号产生与之对应的命令响应类型，进一步解析命令收发模块传送的命令参数。The state control module generates a corresponding command response type according to the command number transmitted by the command transceiver module, and further analyzes the command parameters transmitted by the command transceiver module.

所述校验模块包括CRC7命令校验模块和CRC16数据校验模块，CRC7命令校验模块负责校验命令收发模块中的命令和响应；CRC16数据校验模块负责校验数据收发模块中的数据。The verification module includes a CRC7 command verification module and a CRC16 data verification module. The CRC7 command verification module is responsible for verifying the commands and responses in the command transceiver module; the CRC16 data verification module is responsible for verifying the data in the data transceiver module.

所述数据收发模块中设置有数据接收缓存单元和数据发送缓存单元。The data transceiving module is provided with a data receiving buffer unit and a data sending buffer unit.

所述SD数据传输以块为单位，每个块总是由数据起始位、数据位、CRC16校验位和数据结束位组成，数据收发模块接收数据时按照数据块的格式进行接收，并将数据存入到数据接收缓存单元中，数据发送时先将待发送的数据写入到数据发送缓存单元中，然后按照同样的格式进行发送。Described SD data transmission takes block as a unit, and each block is always made up of data start bit, data bit, CRC16 parity bit and data end bit, and data transceiver module receives according to the format of data block when receiving data, and will The data is stored in the data receiving buffer unit, and when the data is sent, the data to be sent is first written into the data sending buffer unit, and then sent in the same format.

所述数据缓冲的位宽16比特，深度为256。The data buffer has a bit width of 16 bits and a depth of 256 bits.

与现有技术相比，本发明能够完成对主控命令的解析与响应，完成主控系统与Flash之间的数据传输，并且，基于该结构使得可以在不同集成电路工艺下方便地移植，减少了设计成本和研发周期。Compared with the prior art, the present invention can complete the analysis and response to the main control command, complete the data transmission between the main control system and the Flash, and, based on this structure, it can be easily transplanted under different integrated circuit technologies, reducing design cost and development cycle.

附图说明Description of drawings

图1是按照本发明一种实施方式的整体结构电路图。Fig. 1 is an overall structural circuit diagram according to an embodiment of the present invention.

图2是按照本发明一种实施方式的命令收发电路图。Fig. 2 is a circuit diagram of command sending and receiving according to an embodiment of the present invention.

图3是按照本发明一种实施方式的数据收发电路图。Fig. 3 is a circuit diagram of data transceiving according to an embodiment of the present invention.

图4是按照本发明一种实施方式的状态控制电路图。Fig. 4 is a state control circuit diagram according to an embodiment of the present invention.

具体实施方式Detailed ways

下面结合附图和实施例详细说明本发明的实施方式。The implementation of the present invention will be described in detail below in conjunction with the drawings and examples.

如图1所示，本发明的SD存储卡接口，连接在主控系统和Flash控制器之间，包括：命令收发模块、数据收发模块、状态控制模块和校验模块。其中命令收发模块、数据收发模块和状态控制模块均连接于主控系统的顶层模块。命令收发模块包括命令接收模块和命令响应模块，数据收发模块包括数据接收模块和数据发送模块，校验模块包括数据校验模块和命令校验模块，数据校验模块连接于数据接收模块和数据发送模块之间进行数据完整性校验，命令校验模块连接于命令接收模块和命令响应模块之间进行命令完整性校验。数据接收模块连接数据接收缓存单元对接收数据进行缓存，数据发送模块连接数据发送缓存单元对发送数据进行缓存。As shown in Figure 1, the SD memory card interface of the present invention is connected between the main control system and the Flash controller, including: a command transceiver module, a data transceiver module, a state control module and a verification module. The command transceiver module, the data transceiver module and the state control module are all connected to the top module of the main control system. The command transceiver module includes a command receiving module and a command response module. The data transceiver module includes a data receiving module and a data sending module. The verification module includes a data verification module and a command verification module. The data verification module is connected to the data receiving module and the data sending module. Data integrity verification is performed between modules, and the command verification module is connected between the command receiving module and the command response module to perform command integrity verification. The data receiving module is connected to the data receiving buffer unit to buffer the received data, and the data sending module is connected to the data sending buffer unit to buffer the sent data.

如图2所示，本发明命令收发模块的命令接收与响应发送都是在命令线CMD上传输的，所以该端口为一个三态门，其使能端接控制器，由输出使能信号En控制是否输出。控制器接有第二计数器和第二移位寄存器，第二移位寄存器接第二寄存器由其向三态门提供输入。三态门的输出接一个起始位检测单元，起始位检测单元接第一计数器、第一移位寄存器和第一寄存器，第一计数器接有一个比较器。命令接收时，起始位检测单元首先检测命令起始位，检测到起始位后给出Start1信号使得第一计数器开始工作。根据比较器的判断，当接收完一个完整命令，发出接收完成信号End，分别得到第一移位寄存器中对应的命令索引Ind、命令参数Arg和命令校验Crc7。命令接收过程中，同时将数据dCrc7传给CRC7校验模块，用于生成校验数据。响应发送时，根据状态控制模块给出的响应类型Rsp_type产生对应的响应内容，当接收到发送使能信号Start2后，给出发送使能信号En，并将响应的内容通过第二移位寄存器发送出去。响应内容发送完成后给出响应完成信号Rsp_over。As shown in Figure 2, the command reception and response transmission of the command transceiver module of the present invention are all transmitted on the command line CMD, so the port is a tri-state gate, which enables the terminal controller to be output by the enable signal En Control whether to output. The controller is connected with a second counter and a second shift register, and the second shift register is connected with the second register to provide input to the tri-state gate. The output of the tri-state gate is connected to a start bit detection unit, the start bit detection unit is connected to the first counter, the first shift register and the first register, and the first counter is connected to a comparator. When the command is received, the start bit detection unit first detects the command start bit, and after detecting the start bit, a Start1 signal is given to make the first counter start to work. According to the judgment of the comparator, when a complete command is received, the receiving completion signal End is sent, and the corresponding command index Ind, command parameter Arg and command check Crc7 in the first shift register are respectively obtained. During the command receiving process, the data dCrc7 is simultaneously transmitted to the CRC7 verification module for generating verification data. When the response is sent, the corresponding response content is generated according to the response type Rsp_type given by the state control module. After receiving the sending enable signal Start2, the sending enabling signal En is given, and the content of the response is sent through the second shift register go out. After the response content is sent, the response completion signal Rsp_over is given.

如图3所示，本发明数据收发模块的数据线是双向的，其中数据发送模块包括一个带有计数器的控制器，该控制器通过第四移位寄存器接数据发送缓存单元，数据接收模块也包括一个带有计数器的控制器，该控制器通过第三移位寄存器接数据接收缓存单元。Width信号指明当前数据传输模式为标准总线模式或宽总线模式。Size信号指示每个数据块包含的字节数。该模块包含两个数据缓冲，接收缓冲RxFIFO和发送缓冲TrFIFO，数据缓冲位宽16比特，深度为256，这是因为数据块最大为512字节。数据接收状态时，首先检测数据起始位，检测到起始位后计数器开始工作。接收Size个字节的数据后，接收CRC16校验位，最后完成数据块接收，发出接收完成信号End。数据接收过程中，每接收16位数据给出写入信号Wr，将数据写入RxFIFO。如果RxFIFO满，给出Busy信号，主机进入数据发送等待。数据发送状态时，接收控制器收到Start3信号后，开始发出Rd信号读取TrFIFO数据，并将数据传给移位寄存器，使能数据输出控制信号Out_en，移位寄存器根据数据传输模式将数据输出。As shown in Figure 3, the data line of the data transceiver module of the present invention is bidirectional, wherein the data transmission module includes a controller with a counter, the controller is connected to the data transmission buffer unit through the fourth shift register, and the data reception module also A controller with a counter is included, and the controller is connected to the data receiving buffer unit through the third shift register. The Width signal indicates that the current data transmission mode is a standard bus mode or a wide bus mode. The Size signal indicates the number of bytes each data block contains. This module contains two data buffers, receiving buffer RxFIFO and sending buffer TrFIFO, the data buffer bit width is 16 bits, and the depth is 256, because the maximum data block is 512 bytes. In the state of data reception, the data start bit is detected first, and the counter starts to work after the start bit is detected. After receiving Size bytes of data, receive the CRC16 check digit, and finally complete the data block reception, and send the reception completion signal End. During data reception, every 16 bits of data received gives a write signal Wr, and writes the data into RxFIFO. If the RxFIFO is full, a Busy signal is given, and the host computer waits for data transmission. In the state of data transmission, after the receiving controller receives the Start3 signal, it starts to send the Rd signal to read the TrFIFO data, and transmits the data to the shift register, enabling the data output control signal Out_en, and the shift register outputs the data according to the data transmission mode .

如图4所示，状态控制模块：根据接收模块传送的命令编号产生与之对应的命令响应类型，进一步解析接收模块传送的命令参数。工作过程共有9个状态。接收到CMD0命令后都会从其它状态进入到空闲状态IDLE。接收到acmd41命令后，模块进入READY状态，接收到cmd2后进入IDENT状态，接收到cmd3后进入STBY状态，此时完成了卡的初始化和识别过程。接下来接收到cmd7命令进入数据传输TRAN状态。此状态下，接收到数据写入命令cmd24、cmd25等则进入数据接收RCV状态，等待接收数据。接收完成则进入数据写入PROG状态，此状态下将数据接收缓存的数据写入到Flash中。完成数据写入后回到数据传输TRAN状态；此状态下，接收到数据读取命令cmd17、cmd18等则进入数据读取DATA状态，将Flash中数据先写入到数据发送缓冲中，再通过接口发送给主控模块，完成数据发送后返回到数据传输TRAN状态。As shown in Figure 4, the state control module: generates a corresponding command response type according to the command number transmitted by the receiving module, and further analyzes the command parameters transmitted by the receiving module. There are 9 states in the working process. After receiving the CMD0 command, it will enter the idle state IDLE from other states. After receiving the acmd41 command, the module enters the READY state, enters the IDENT state after receiving cmd2, and enters the STBY state after receiving cmd3, at this time the card initialization and identification process is completed. Next, the cmd7 command is received to enter the data transmission TRAN state. In this state, after receiving the data write command cmd24, cmd25, etc., it will enter the data receiving RCV state, waiting to receive data. After the receiving is completed, it will enter the data writing PROG state. In this state, the data in the data receiving buffer is written into Flash. After completing the data writing, return to the data transmission TRAN state; in this state, after receiving the data reading command cmd17, cmd18, etc., it enters the data reading DATA state, and writes the data in the Flash to the data sending buffer first, and then through the interface Send it to the main control module, and return to the data transmission TRAN state after completing the data transmission.

校验模块：CRC7负责校验命令收发模块中的命令和响应。命令收发模块中的Crc7与该模块的数据输入端连接，作为校验模块的数据输入端口；CRC16负责校验数据收发模块中的数据，共有四个数据校验模块，当为1位模式时其中与DAT0连接的校验模块工作，为4位模式时四个数据校验模块同时工作。Verification module: CRC7 is responsible for verifying the commands and responses in the command transceiver module. Crc7 in the command transceiver module is connected to the data input terminal of the module as the data input port of the verification module; CRC16 is responsible for verifying the data in the data transceiver module, and there are four data verification modules in total. When it is in 1-bit mode, the The verification module connected to DAT0 works, and four data verification modules work at the same time when it is in 4-bit mode.

本设计用Verilog进行FPGA仿真验证，验证SD接口的可靠性和可行性。基于Altera FPGA Cyclone II系列FPGA进行综合并下载到FPGA芯片中验证，与电脑连接后可以识别为SD存储卡。因而证明本设计是正确的与可行的。This design uses Verilog for FPGA simulation verification to verify the reliability and feasibility of the SD interface. Based on Altera FPGA Cyclone II series FPGA, it is synthesized and downloaded to the FPGA chip for verification. After connecting to the computer, it can be recognized as an SD memory card. Thus it is proved that the design is correct and feasible.

以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.