CN103399607B - The high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit - Google Patents

The present invention relates to power management techniques.The invention solves existing low pressure difference linear voltage regulator mostly to increase circuit complexity, lower the problem that load capacity and increase output voltage noise etc. are cost solution output voltage generation due to voltage spikes, provide a kind of high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, its technical scheme can be summarized as: compared with existing LDO, add slew rate enhancing circuit and building-out capacitor, and the normal phase input end of error amplifier is connected with reference voltage source, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube, one end of building-out capacitor is connected with the inverting input of error amplifier, the other end of building-out capacitor is connected with output terminal.The invention has the beneficial effects as follows, improve transient response, be applicable to low pressure difference linear voltage regulator.

集成摆率增强电路的高PSR低压差线性稳压器High PSR Low Dropout Linear Regulator with Integrated Slew Rate Enhancement Circuit

技术领域technical field

本发明涉及电源管理技术，特别涉及低压差线性稳压器的技术。The invention relates to power management technology, in particular to the technology of low-dropout linear regulator.

背景技术Background technique

低压差线性稳压器（LDO）是电源管理领域中的一类重要电路，具有输出噪声小、成本低、结构简单、低功耗等优点。随着电子系统对电源要求的不断提高，传统的LDO已不能满足人们对芯片噪声、电源抑制、瞬态性能等指标的要求。因而，高性能LDO的研究成了电源管理领域的研究热点。Low-dropout linear regulator (LDO) is an important circuit in the field of power management, which has the advantages of low output noise, low cost, simple structure, and low power consumption. With the continuous improvement of the power supply requirements of electronic systems, the traditional LDO can no longer meet people's requirements for chip noise, power supply rejection, transient performance and other indicators. Therefore, the study of high-performance LDO has become a research hotspot in the field of power management.

如图1所示，典型的LDO电路一般由基准电压源Vref、误差放大器、电源电压输入端VDD、调整管Mp及电阻反馈电路构成，误差放大器的正相输入端与电阻反馈电路连接，反相输入端与基准电压源Vref连接，输出端与调整管Mp的栅极连接，调整管Mp的漏极为输出端，并与电阻反馈电路连接，调整管Mp的源极与电源电压输入端VDD连接，具体的，电阻反馈电路包括第一电阻R1及第二电阻R2，第一电阻R1的一端与第二电阻R2的一端连接，并与误差放大器的正相输入端连接，第一电阻R1的另一端与输出端连接，第二电阻的另一端与地线连接，调整管Mp一般采用MOS管，如PMOS管，使用时，负载RL一般跨接在输出端与地线之间，片外电容CL与负载并联，其原理是通过带隙基准源产生的稳定电压以及负反馈控制环路得到基本不随环境变化的输出电压。为了提高带负载能力，一般调整管Mp的面积很大，从而在调整管Mp栅极形成数十pF的寄生电容，同时为提高LDO的功耗，静态工作电流很小，从而对调整管Mp栅极充放电将比较缓慢，在输出电流跳变时，输出电压将产生大的上冲、下冲电压尖峰，同时电压恢复稳定时间也将比较长。一些文献对此问题提出了相应的解决方案，例如在文献“Mohammad Al-Shyoukh,Hoi Leeand and Raul Perez.A Transient-EnhancedLow-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation.IEEEJOURNAL OF SOLID-STATE CIRCUITS,VOL.42,NO.8,AUGUST2007”中提出，在误差放大器和调整管之间加入瞬态增强电路，但增加了系统补偿的复杂度，而且只能在一定程度上改善LDO的摆率，同时高频下的电源抑制能力并没有很大的改善。As shown in Figure 1, a typical LDO circuit is generally composed of a reference voltage source Vref, an error amplifier, a power supply voltage input terminal VDD, a regulator transistor Mp, and a resistor feedback circuit. The input terminal is connected to the reference voltage source Vref, the output terminal is connected to the gate of the adjustment tube Mp, the drain of the adjustment tube Mp is the output terminal, and is connected to the resistance feedback circuit, the source of the adjustment tube Mp is connected to the power supply voltage input terminal VDD, Specifically, the resistance feedback circuit includes a first resistance R1 and a second resistance R2, one end of the first resistance R1 is connected to one end of the second resistance R2, and is connected to the non-inverting input end of the error amplifier, and the other end of the first resistance R1 It is connected to the output terminal, and the other end of the second resistor is connected to the ground wire. The adjustment tube Mp generally adopts a MOS tube, such as a PMOS tube. When used, the load RL is generally connected between the output terminal and the ground wire, and the off-chip capacitor CL and The load is connected in parallel, and the principle is to obtain an output voltage that basically does not change with the environment through the stable voltage generated by the bandgap reference source and the negative feedback control loop. In order to improve the load carrying capacity, generally the area of the pass transistor Mp is very large, so tens of pF of parasitic capacitance is formed on the gate of the pass transistor Mp. The charge and discharge of the pole will be relatively slow. When the output current jumps, the output voltage will produce large overshoot and undershoot voltage spikes, and the voltage recovery and stabilization time will be relatively long. Some literatures have proposed corresponding solutions to this problem, for example in the literature "Mohammad Al-Shyoukh, Hoi Leeand and Raul Perez. A Transient-Enhanced Low-Quescent Current Low-Dropout Regulator With Buffer Impedance Attenuation. IEEEJOURNAL OF SOLID-STATE CIRCUITS It is proposed in VOL.42, NO.8, AUGUST2007 to add a transient enhancement circuit between the error amplifier and the adjustment tube, but it increases the complexity of system compensation and can only improve the slew rate of the LDO to a certain extent. At the same time Power supply rejection at high frequencies has not improved much.

近年来，论文中出现很多高电源抑制比LDO解决方案，但是大都以增加电路复杂度、减低负载能力和增加输出电压噪声等为代价，并且很多解决方案在高频段特别是1MHz以上没有得到大的改善。In recent years, many high-power supply rejection ratio LDO solutions have appeared in papers, but most of them are at the cost of increasing circuit complexity, reducing load capacity and increasing output voltage noise, and many solutions have not achieved great results in high-frequency bands, especially above 1MHz. improve.

发明内容Contents of the invention

本发明的目的是要克服目前低压差线性稳压器大都以增加电路复杂度、减低负载能力和增加输出电压噪声等为代价解决输出电压产生电压尖峰的缺点，提供一种集成摆率增强电路的高PSR低压差线性稳压器。The purpose of the present invention is to overcome the shortcomings of the current low dropout linear regulators that mostly solve the problem of output voltage spikes at the cost of increasing circuit complexity, reducing load capacity, and increasing output voltage noise, and provides an integrated slew rate enhancement circuit. High PSR Low Dropout Linear Regulator.

本发明解决其技术问题，采用的技术方案是，集成摆率增强电路的高PSR低压差线性稳压器，包括基准电压源、误差放大器、电源电压输入端、调整管及电阻反馈电路，其特征在于，还包括摆率增强电路及补偿电容，所述误差放大器的正相输入端与基准电压源连接，反相输入端与电阻反馈电路连接，输出端与摆率增强电路的输入端连接，摆率增强电路的输出端与调整管的栅极连接，调整管的漏极为输出端，并与电阻反馈电路连接，调整管的源极与电源电压输入端连接，补偿电容的一端与误差放大器的反相输入端连接，补偿电容的另一端与输出端连接。The present invention solves its technical problem, and the technical solution adopted is that the high PSR low dropout linear voltage regulator of the integrated slew rate enhancement circuit includes a reference voltage source, an error amplifier, a power supply voltage input terminal, an adjustment tube and a resistance feedback circuit, and its characteristics In that, it also includes a slew rate enhancement circuit and a compensation capacitor, the non-inverting input terminal of the error amplifier is connected to the reference voltage source, the inverting input terminal is connected to the resistance feedback circuit, and the output terminal is connected to the input terminal of the slew rate enhancement circuit. The output terminal of the rate enhancement circuit is connected to the gate of the adjustment tube, the drain of the adjustment tube is the output terminal, and is connected to the resistance feedback circuit, the source of the adjustment tube is connected to the input terminal of the power supply voltage, and one end of the compensation capacitor is connected to the reverse of the error amplifier. The phase input terminal is connected, and the other end of the compensation capacitor is connected to the output terminal.

具体的，所述误差放大器为-3dB带宽大于2MHz的放大器。Specifically, the error amplifier is an amplifier with a -3dB bandwidth greater than 2MHz.

进一步的，所述误差放大器包括偏置电压输入端、第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管及第五NMOS管，所述第一PMOS管的栅极与第二PMOS管的栅极连接，第二PMOS管的栅极与其自身的漏极连接，第一PMOS管的漏极与第四NMOS管的栅极连接，第四NMOS管的栅极与其自身的漏极连接，第二PMOS管的栅极与第一NMOS管的漏极连接，第三PMOS管的栅极与其自身的漏极连接，并与第二NMOS管的漏极连接，第四PMOS管的栅极与第三PMOS管的栅极连接，漏极与第五NMOS管的栅极连接，第五NMOS管的栅极与其自身的漏极连接，第一NMOS管的栅极为误差放大器反相输入端，源级与第三NMOS管的漏极连接，第二NMOS管的栅极为误差放大器正相输入端，源级与第三NMOS管的漏极连接，第一PMOS管、第二PMOS管、第三PMOS管及第四PMOS管的源级都与电源电压输入端连接，第三NMOS管、第四NMOS管及第五NMOS管的源级都与地连接，第三NMOS管的栅极与偏置电压输入端连接，以产生尾电流。Further, the error amplifier includes a bias voltage input terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a Four NMOS transistors and the fifth NMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the second PMOS transistor is connected to its own drain, and the drain of the first PMOS transistor is connected to the drain of the first PMOS transistor. The gate of the fourth NMOS transistor is connected, the gate of the fourth NMOS transistor is connected to its own drain, the gate of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the third PMOS transistor is connected to its own drain. The drain is connected to the drain of the second NMOS transistor, the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, the drain is connected to the gate of the fifth NMOS transistor, and the gate of the fifth NMOS transistor The pole is connected to its own drain, the gate of the first NMOS transistor is the inverting input of the error amplifier, the source is connected to the drain of the third NMOS transistor, the gate of the second NMOS transistor is the non-inverting input of the error amplifier, and the source It is connected to the drain of the third NMOS transistor, the source stages of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are all connected to the input terminal of the power supply voltage, the third NMOS transistor, the fourth NMOS transistor and the The sources of the fifth NMOS transistors are all connected to the ground, and the gates of the third NMOS transistors are connected to the bias voltage input end to generate tail current.

具体的，所述摆率增强电路包括第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第六NMOS管、第七NMOS管、第八NMOS管及第九NMOS管，所述第五PMOS管与第六NMOS管组成第一反相器，第七PMOS管与第七NMOS管组成第二反相器，第一反相器的输入端同误差放大器的输出端相连，第一反相器输出端同第六PMOS管漏极以及第二反相器输入端相连，第六PMOS管栅极与其漏极相连，并与第二反相器输入端连接，第二反相器输出端同第八NMOS管栅极、漏极及第九NMOS管栅极相连，第八NMOS管栅极与第九NMOS管栅极连接，第八POMS管栅极与其漏极连接，并与调整管栅极连接。Specifically, the slew rate enhancement circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, The fifth PMOS transistor and the sixth NMOS transistor form a first inverter, the seventh PMOS transistor and the seventh NMOS transistor form a second inverter, the input terminal of the first inverter is connected to the output terminal of the error amplifier, The output end of the first inverter is connected to the drain of the sixth PMOS transistor and the input end of the second inverter, the gate of the sixth PMOS transistor is connected to the drain, and connected to the input end of the second inverter, and the second inverter The output terminal of the device is connected with the gate of the eighth NMOS transistor, the drain and the gate of the ninth NMOS transistor, the gate of the eighth NMOS transistor is connected with the gate of the ninth NMOS transistor, the gate of the eighth POMS transistor is connected with the drain, and is connected with the gate of the ninth NMOS transistor. Adjust the tube grid connection.

具体的，所述电阻反馈电路包括第一电阻及第二电阻，第一电阻的一端与第二电阻的一端连接，并与误差放大器的反相输入端连接，第一电阻的另一端与输出端连接，第二电阻的另一端与地线连接。Specifically, the resistance feedback circuit includes a first resistance and a second resistance, one end of the first resistance is connected to one end of the second resistance, and is connected to the inverting input end of the error amplifier, and the other end of the first resistance is connected to the output end connected, and the other end of the second resistor is connected to the ground.

再进一步的，所述调整管为PMOS管。Still further, the adjusting transistor is a PMOS transistor.

具体的，还包括片外电容，所述片外电容的一端与输出端连接，另一端与地线连接，该片外电容的寄生电阻小于10mΩ，片外电容的电容值大于2.2uF。Specifically, it also includes an off-chip capacitor, one end of the off-chip capacitor is connected to the output terminal, and the other end is connected to the ground wire, the parasitic resistance of the off-chip capacitor is less than 10mΩ, and the capacitance value of the off-chip capacitor is greater than 2.2uF.

本发明的有益效果是，在本发明方案中的集成摆率增强电路的高PSR低压差线性稳压器，通过集成摆率增强电路使摆率增强，提高了瞬态响应，同时还增强了对电源抑制的能力，特别是在高频下的电源抑制。The beneficial effects of the present invention are that the high PSR low dropout linear voltage regulator integrated with the slew rate enhancement circuit in the scheme of the present invention enhances the slew rate through the integrated slew rate enhancement circuit, improves the transient response, and simultaneously enhances the The ability to reject power supplies, especially at high frequencies.

附图说明Description of drawings

图1为现有LDO的系统框图。Figure 1 is a system block diagram of an existing LDO.

图2为本发明集成摆率增强电路的高PSR低压差线性稳压器的系统框图。FIG. 2 is a system block diagram of the high-PSR low-dropout linear voltage regulator integrated with the slew rate enhancement circuit of the present invention.

图3为本发明实施例中集成摆率增强电路的高PSR低压差线性稳压器的电路示意图。FIG. 3 is a schematic circuit diagram of a high-PSR low-dropout linear voltage regulator integrated with a slew rate enhancement circuit in an embodiment of the present invention.

图4为本发明实施例中电源电压2V输出负载200mA的增益相位曲线图。FIG. 4 is a gain-phase curve diagram of a power supply voltage of 2V outputting a load of 200mA in an embodiment of the present invention.

图5为本发明实施例中电源电压2V输出负载0A的增益相位曲线图。FIG. 5 is a gain-phase curve diagram of a power supply voltage of 2V outputting a load of 0A in an embodiment of the present invention.

图6为本发明实施例中电源电压2V输出负载1us由0A跳到200mA，再由200mA跳到0A的瞬态特性图。Fig. 6 is a transient characteristic diagram of the power supply voltage 2V output load 1us jumping from 0A to 200mA, and then jumping from 200mA to 0A in the embodiment of the present invention.

图7为本发明实施例中输出负载200mA下电源电压1us由2V跳到3.3V的瞬态特性图。FIG. 7 is a transient characteristic diagram of a power supply voltage 1us jumping from 2V to 3.3V under an output load of 200mA in an embodiment of the present invention.

图8为本发明实施例中不同输出负载下的电源抑制比特性图。FIG. 8 is a characteristic diagram of the power supply rejection ratio under different output loads in the embodiment of the present invention.

其中，Vref为基准电压源，VDD为电源电压，Mp为调整管，Cm为补偿电容，Va为偏置电压，MA₁为第一PMOS管，MA₂为第二PMOS管，MA₃为第三PMOS管，MA₄为第四PMOS管，MA₅为第一NMOS管，MA₆为第二NMOS管，MA₇为第三NMOS管，MA₈为第四NMOS管，MA₉为第五NMOS管，MB₁为第五PMOS管，MB₂为第六PMOS管，MB₃为第七PMOS管，MB₄为第八PMOS管，MB₅为第六NMOS管，MB₆为第七NMOS管，MB₇为第八NMOS管，MB₈为第九NMOS管，R1为第一电阻，R2为第二电阻，CL为片外电容，RL为负载。Among them, Vref is the reference voltage source, VDD is the power supply voltage, Mp is the adjustment tube, Cm is the compensation capacitor, Va is the bias voltage, MA ₁ is the first PMOS tube, MA ₂ is the second PMOS tube, and MA ₃ is the third PMOS tube. PMOS tube, MA ₄ is the fourth PMOS tube, MA ₅ is the first NMOS tube, MA ₆ is the second NMOS tube, MA ₇ is the third NMOS tube, MA ₈ is the fourth NMOS tube, MA ₉ is the fifth NMOS tube , MB ₁ is the fifth PMOS transistor, MB ₂ is the sixth PMOS transistor, MB ₃ is the seventh PMOS transistor, MB ₄ is the eighth PMOS transistor, MB ₅ is the sixth NMOS transistor, MB ₆ is the seventh NMOS transistor, MB ₇ is the eighth NMOS transistor, MB ₈ is the ninth NMOS transistor, R1 is the first resistor, R2 is the second resistor, CL is an off-chip capacitor, and RL is a load.

具体实施方式Detailed ways

下面结合实施例及附图，详细描述本发明的技术方案。The technical solution of the present invention will be described in detail below in combination with the embodiments and the accompanying drawings.

本发明的集成摆率增强电路的高PSR低压差线性稳压器的系统框图如图2。本发明的集成摆率增强电路的高PSR低压差线性稳压器，包括基准电压源Vref、误差放大器、电源电压输入端、调整管Mp、电阻反馈电路、摆率增强电路及补偿电容Cm，所述误差放大器的正相输入端与基准电压源Vref连接，反相输入端与电阻反馈电路连接，输出端与摆率增强电路的输入端连接，摆率增强电路的输出端与调整管Mp的栅极连接，调整管Mp的漏极为输出端，并与电阻反馈电路连接，调整管Mp的源极与电源电压输入端连接，补偿电容Cm的一端与误差放大器的反相输入端连接，补偿电容Cm的另一端与输出端连接。The system block diagram of the high-PSR low-dropout linear voltage regulator integrated with the slew rate enhancement circuit of the present invention is shown in FIG. 2 . The high-PSR low-dropout linear voltage regulator with an integrated slew rate enhancement circuit of the present invention includes a reference voltage source Vref, an error amplifier, a power supply voltage input terminal, a regulator tube Mp, a resistance feedback circuit, a slew rate enhancement circuit, and a compensation capacitor Cm. The non-inverting input terminal of the error amplifier is connected to the reference voltage source Vref, the inverting input terminal is connected to the resistance feedback circuit, the output terminal is connected to the input terminal of the slew rate enhancement circuit, and the output terminal of the slew rate enhancement circuit is connected to the gate of the adjustment tube Mp The drain of the adjustment tube Mp is the output terminal and connected to the resistor feedback circuit, the source of the adjustment tube Mp is connected to the input terminal of the power supply voltage, one end of the compensation capacitor Cm is connected to the inverting input terminal of the error amplifier, and the compensation capacitor Cm The other end is connected to the output end.

实施例Example

本发明实施例的集成摆率增强电路的高PSR低压差线性稳压器的系统框图如图2所示，电路示意图如图3所示。本例的集成摆率增强电路的高PSR低压差线性稳压器，包括基准电压源Vref、误差放大器、电源电压输入端、调整管Mp、电阻反馈电路、摆率增强电路及补偿电容Cm，所述误差放大器的正相输入端与基准电压源Vref连接，反相输入端与电阻反馈电路连接，输出端与摆率增强电路的输入端连接，摆率增强电路的输出端与调整管Mp的栅极连接，调整管Mp的漏极为输出端，并与电阻反馈电路连接，调整管Mp的源极与电源电压输入端连接，补偿电容Cm的一端与误差放大器的反相输入端连接，补偿电容Cm的另一端与输出端连接，本例中，调整管Mp为PMOS管，电源电压输入端输入电源电压VDD。A system block diagram of a high-PSR low-dropout linear regulator integrating a slew rate enhancement circuit according to an embodiment of the present invention is shown in FIG. 2 , and a schematic circuit diagram is shown in FIG. 3 . The high-PSR low-dropout linear regulator with an integrated slew rate enhancement circuit in this example includes a reference voltage source Vref, an error amplifier, a power supply voltage input terminal, a pass transistor Mp, a resistor feedback circuit, a slew rate enhancement circuit, and a compensation capacitor Cm. The non-inverting input terminal of the error amplifier is connected to the reference voltage source Vref, the inverting input terminal is connected to the resistance feedback circuit, the output terminal is connected to the input terminal of the slew rate enhancement circuit, and the output terminal of the slew rate enhancement circuit is connected to the gate of the adjustment tube Mp The drain of the adjustment tube Mp is the output terminal and connected to the resistor feedback circuit, the source of the adjustment tube Mp is connected to the input terminal of the power supply voltage, one end of the compensation capacitor Cm is connected to the inverting input terminal of the error amplifier, and the compensation capacitor Cm The other end of is connected to the output terminal. In this example, the adjustment tube Mp is a PMOS tube, and the power supply voltage input terminal inputs the power supply voltage VDD.

本例中误差放大器为-3dB带宽大于2MHz的放大器，其包括偏置电压输入端、第一PMOS管MA₁、第二PMOS管MA₂、第三PMOS管MA₃、第四PMOS管MA₄、第一NMOS管MA₅、第二NMOS管MA₆、第三NMOS管MA₇、第四NMOS管MA₈及第五NMOS管MA₉，其中，第一PMOS管MA₁的栅极与第二PMOS管MA₂的栅极连接，第二PMOS管MA₂的栅极与其自身的漏极连接，第一PMOS管MA₁的漏极与第四NMOS管MA₈的栅极连接，第四NMOS管MA₈的栅极与其自身的漏极连接，第二PMOS管MA₂的栅极与第一NMOS管MA₅的漏极连接，第三PMOS管MA₃的栅极与其自身的漏极连接，并与第二NMOS管MA₆的漏极连接，第四PMOS管MA₄的栅极与第三PMOS管MA₃的栅极连接，漏极与第五NMOS管MA₉的栅极连接，第五NMOS管MA₉的栅极与其自身的漏极连接，第一NMOS管MA₅的栅极为误差放大器反相输入端，源级与第三NMOS管MA₇的漏极连接，第二NMOS管MA₆的栅极为误差放大器正相输入端，源级与第三NMOS管MA₇的漏极连接，第一PMOS管MA₁、第二PMOS管MA₂、第三PMOS管MA₃及第四PMOS管MA₄的源级都与电源电压输入端连接，第三NMOS管MA₇、第四NMOS管MA₈及第五NMOS管MA₉的源级都与地连接，第三NMOS管MA₇的栅极与偏置电压输入端连接，以产生尾电流，偏置电压输入端用以输入偏置电压Va。为了使误差放大器不引入低频极点，其输出电阻Ro不能太大，同时考虑到降低静态功耗和增大摆率，其尾电流应取个相对适中的值，其低频增益A_EA为50dB，输出极点为3M Hz。In this example, the error amplifier is an amplifier with a -3dB bandwidth greater than 2MHz, which includes a bias voltage input terminal, a first PMOS transistor MA ₁ , a second PMOS transistor MA ₂ , a third PMOS transistor MA ₃ , a fourth PMOS transistor MA ₄ , The first NMOS transistor MA ₅ , the second NMOS transistor MA ₆ , the third NMOS transistor MA ₇ , the fourth NMOS transistor MA ₈ and the fifth NMOS transistor MA ₉ , wherein the gate of the first PMOS transistor MA ₁ is connected to the second PMOS transistor MA 1 The gate of the transistor MA ₂ is connected, the gate of the second PMOS transistor MA ₂ is connected to its own drain, the drain of the first PMOS transistor MA ₁ is connected to the gate of the fourth NMOS transistor MA ₈ , and the fourth NMOS transistor MA The gate of ₈ is connected with its own drain, the gate of the second PMOS transistor MA ₂ is connected with the drain of the first NMOS transistor MA ₅ , the gate of the third PMOS transistor MA ₃ is connected with its own drain, and is connected with the drain of the first NMOS transistor MA 5. The drain of the second NMOS transistor MA ₆ is connected, the grid of the fourth PMOS transistor MA ₄ is connected with the grid of the third PMOS transistor MA ₃ , the drain is connected with the grid of the fifth NMOS transistor MA ₉ , and the grid of the fifth NMOS transistor MA 9 is connected. The gate of MA ₉ is connected to its own drain, the gate of the first NMOS transistor MA ₅ is the inverting input terminal of the error amplifier, the source is connected to the drain of the third NMOS transistor MA ₇ , and the gate of the second NMOS transistor MA ₆ The non-inverting input terminal of the pole error amplifier, the source is connected to the drain of the third NMOS transistor MA ₇ , the first PMOS transistor MA ₁ , the second PMOS transistor MA ₂ , the third PMOS transistor MA ₃ and the fourth PMOS transistor MA ₄ The source stages are all connected to the power supply voltage input terminal, the source stages of the third NMOS transistor MA ₇ , the fourth NMOS transistor MA ₈ and the fifth NMOS transistor MA ₉ are all connected to the ground, and the gate of the third NMOS transistor MA ₇ is connected to the bias The voltage input terminal is connected to generate a tail current, and the bias voltage input terminal is used for inputting a bias voltage Va. In order to prevent the error amplifier from introducing low-frequency poles, its output resistance Ro should not be too large. At the same time, taking into account the reduction of static power consumption and the increase of slew rate, its tail current should take a relatively moderate value. Its low-frequency gain A _EA is 50dB, and the output The pole is 3M Hz.

本例中的摆率增强电路包括第五PMOS管MB₁、第六PMOS管MB₂、第七PMOS管MB₃、第八PMOS管MB₄、第六NMOS管MB₅、第七NMOS管MB₆、第八NMOS管MB₇及第九NMOS管MB₈，其中，第五PMOS管MB₁与第六NMOS管MB₅组成第一反相器，第七PMOS管MB₃与第七NMOS管MB₆组成第二反相器，第一反相器的输入端同误差放大器的输出端相连，第一反相器输出端同第六PMOS管MB₂漏极以及第二反相器输入端相连，第六PMOS管MB₂栅极与其漏极相连，并与第二反相器输入端连接，第二反相器输出端同第八NMOS管MB₇栅极、漏极及第九NMOS管MB₈栅极相连，第八NMOS管MB₇栅极与第九NMOS管MB₈栅极连接，第八POMS管MB₄栅极与其漏极连接，并与调整管Mp栅极连接。The slew rate enhancement circuit in this example includes a fifth PMOS transistor MB ₁ , a sixth PMOS transistor MB ₂ , a seventh PMOS transistor MB ₃ , an eighth PMOS transistor MB ₄ , a sixth NMOS transistor MB ₅ , and a seventh NMOS transistor MB ₆ , the eighth NMOS transistor MB ₇ and the ninth NMOS transistor MB ₈ , wherein the fifth PMOS transistor MB ₁ and the sixth NMOS transistor MB ₅ form a first inverter, and the seventh PMOS transistor MB ₃ and the seventh NMOS transistor MB ₆ The second inverter is formed, the input end of the first inverter is connected with the output end of the error amplifier, the output end of the first inverter is connected with the drain of the sixth PMOS transistor MB ₂ and the input end of the second inverter, and the input end of the second inverter The gates of the six PMOS transistors MB ₂ are connected to their drains, and connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate and drain of the eighth NMOS transistor MB ₇ and the gate of the ninth NMOS transistor MB ₈ The gate of the eighth NMOS transistor MB ₇ is connected to the gate of the ninth NMOS transistor MB ₈ , the gate of the eighth POMS transistor MB ₄ is connected to its drain, and connected to the gate of the adjustment transistor Mp.

本例中的电阻反馈电路包括第一电阻R1及第二电阻R2，第一电阻R1的一端与第二电阻R2的一端连接，并与误差放大器的反相输入端连接，第一电阻R1的另一端与输出端连接，第二电阻R2的另一端与地线连接。The resistance feedback circuit in this example includes a first resistance R1 and a second resistance R2, one end of the first resistance R1 is connected to one end of the second resistance R2, and is connected to the inverting input end of the error amplifier, and the other end of the first resistance R1 One end is connected to the output end, and the other end of the second resistor R2 is connected to the ground wire.

使用时，负载RL跨接在输出端与地线之间，片外电容CL与负载RL并联，即片外电容CL的一端与输出端连接，另一端与地线连接，该片外电容CL的寄生电阻小于10mΩ，片外电容CL的电容值大于2.2uF。When in use, the load RL is connected between the output terminal and the ground wire, and the off-chip capacitor CL is connected in parallel with the load RL, that is, one end of the off-chip capacitor CL is connected to the output end, and the other end is connected to the ground wire. The parasitic resistance is less than 10mΩ, and the capacitance value of the off-chip capacitor CL is greater than 2.2uF.

摆率增强电路为本发明的重点，摆率增强的作用是在负载变化的时候能快速改变调整管Mp的栅极输入，从而在极短的时间内调整输出电压稳定。The slew rate enhancement circuit is the key point of the present invention. The function of the slew rate enhancement is to quickly change the gate input of the adjustment transistor Mp when the load changes, thereby adjusting the output voltage to be stable in a very short time.

在稳定条件下，第八PMOS管MB₄镜像负载RL电流，同时偏置第九NMOS管MB₈，第八NMOS管MB₇镜像第九NMOS管MB₈电流，比例为1：k，第八NMOS管MB₇栅极电压固定；由于第八NMOS管MB₇栅极电压固定，所以第二反相器的输入电压也固定；第六PMOS管MB₂镜像第七PMOS管MB₃的电流，并且第六PMOS管MB₂为二极管连接，从而第一反相器的输出端极点工作在极高频率处；第一反相器的输出端同第二反相器输入端相连，第二反相器的输入端电压固定，即第一反相器的输出端电压固定，从而第一反相器的输入端电压固定。Under stable conditions, the eighth PMOS transistor MB ₄ mirrors the load RL current, and at the same time biases the ninth NMOS transistor MB ₈ , the eighth NMOS transistor MB ₇ mirrors the ninth NMOS transistor MB ₈ current, the ratio is 1:k, and the eighth NMOS The gate voltage of the tube MB ₇ is fixed; since the gate voltage of the eighth NMOS tube MB ₇ is fixed, the input voltage of the second inverter is also fixed; the sixth PMOS tube MB ₂ mirrors the current of the seventh PMOS tube MB ₃ , and the The six PMOS transistors MB ₂ are diode-connected, so that the pole of the output terminal of the first inverter works at a very high frequency; the output terminal of the first inverter is connected with the input terminal of the second inverter, and the output terminal of the second inverter The voltage at the input end is fixed, that is, the voltage at the output end of the first inverter is fixed, so the voltage at the input end of the first inverter is fixed.

当负载由轻载跳到重载时，输出电压将会有下冲电压，通过误差放大器放大，第一反相器输入端将被快速充电，第一反相器输入电压增大，从而第一反相器为输出端电容快速放电，流过第六PMOS管MB₂的电流将会增大，第二反相器输入电压将快速减小，第二反相器为输出端电容快速充电，从而第九NMOS管MB₈栅极电压增大，第九NMOS管MB₈将流过更大电流为调整管栅极放电，最终系统稳定。当负载由重载跳到轻载时，输出电压将会有上冲电压，通过误差放大器放大，第一反相器输入端将被快速放电，第一反相器输入电压降低，从而第一反相器为输出端电容快速充电，流过第六PMOS管MB₂的电流将会减小，第二反相器输入电压将快速增大，第二反相器为输出端电容快速放电，从而第九NMOS管MB₈栅极电压减小，第八PMOS管MB₄将流过更大电流为调整管栅极充电，最终系统稳定。When the load jumps from light load to heavy load, the output voltage will have an undershoot voltage, amplified by the error amplifier, the input terminal of the first inverter will be charged quickly, and the input voltage of the first inverter will increase, so that the first The inverter quickly discharges the capacitor at the output end, the current flowing through the sixth PMOS transistor MB ₂ will increase, the input voltage of the second inverter will quickly decrease, and the second inverter quickly charges the capacitor at the output end, thus As the gate voltage of the ninth NMOS transistor MB ₈ increases, a larger current will flow through the ninth NMOS transistor MB ₈ to discharge the gate of the regulating transistor, and finally the system is stable. When the load jumps from heavy load to light load, the output voltage will have an overshoot voltage, amplified by the error amplifier, the input terminal of the first inverter will be quickly discharged, and the input voltage of the first inverter will drop, so that the first inverter The phase inverter quickly charges the capacitor at the output end, the current flowing through the sixth PMOS transistor MB ₂ will decrease, the input voltage of the second inverter will rapidly increase, and the second inverter quickly discharges the capacitor at the output end, so that the first The gate voltage of the ninth NMOS transistor MB ₈ decreases, and the eighth PMOS transistor MB ₄ will flow a larger current to charge the gate of the adjustment transistor, and finally the system is stable.

本发明中的摆率增强电路极大的提高了瞬态响应速度，并有效的减小了输出电压的尖峰。The slew rate enhancement circuit in the present invention greatly improves the transient response speed and effectively reduces the peak value of the output voltage.

对于摆率增强电路：第一反相器输出端接二极管连接形式的第六PMOS管MB₂，从而第一反相器输出端零极点将工作在极高频率下；第二反相器输出端接二极管连接形式的第八NMOS管MB₇，从而第二反相器输出端零极点将工作在极高频率下；第八PMOS管MB₄为二极管连接形式，调整管Mp栅极将引入高频极点。所以摆率增强电路没有引入多余的低频极点，在10MHz内整个系统有三个极点和一个补偿零点。For the slew rate enhancement circuit: the output terminal of the first inverter is connected to the sixth PMOS transistor MB ₂ in the form of a diode connection, so that the zero-pole point of the output terminal of the first inverter will work at a very high frequency; the output terminal of the second inverter Connect the eighth NMOS transistor MB ₇ in the form of diode connection, so that the zero pole of the output terminal of the second inverter will work at a very high frequency; the eighth PMOS transistor MB ₄ is in the form of diode connection, and the gate of the adjustment transistor Mp will introduce high frequency pole. Therefore, the slew rate enhancement circuit does not introduce redundant low-frequency poles, and the whole system has three poles and one compensation zero within 10MHz.

三个极点分别如下所示：The three poles are as follows:

PP 11 == 11 CLCL ** RoutRouting

PP 22 == 11 RR PP ** CC PP

PP 33 == 11 CC Oo ** RR Oo

其中，P1是输出端对应的输出极点，P2是调整管Mp栅极极点对应Rp和Cp，P3是误差放大器输出极点对应Ro和Co，Resr为片外电容的寄生电阻，Rp为调整管栅极的寄生电阻，Cp为调整管栅极的寄生电容，Co为误差放大器的负载电容，Ro为误差放大器的输出电阻，Rout是LDO的输出等效电阻，Rout=1/(gdsp+GL)，其中gdsp为调整管Mp的输出等效电导，GL为负载电阻RL的倒数。Among them, P1 is the output pole corresponding to the output terminal, P2 is the gate pole of the adjustment tube Mp corresponding to Rp and Cp, P3 is the output pole of the error amplifier corresponding to Ro and Co, Resr is the parasitic resistance of the off-chip capacitor, and Rp is the gate of the adjustment tube Cp is the parasitic capacitance of the pass gate, Co is the load capacitance of the error amplifier, Ro is the output resistance of the error amplifier, Rout is the output equivalent resistance of the LDO, Rout=1/(gdsp+GL), where gdsp is the output equivalent conductance of the adjustment tube Mp, and GL is the reciprocal of the load resistance RL.

补偿电容Cm和电阻反馈电路中第一电阻R1、第二电阻R2产生一对零极点，零点为：The first resistor R1 and the second resistor R2 in the compensation capacitor Cm and the resistance feedback circuit generate a pair of zero-pole points, and the zero points are:

ZmZm == 11 Cmcm ** RR 11

极点为：The poles are:

PmPM == 11 Cmcm ** RR 11 // // RR 22

稳定性分析：Stability Analysis:

输出端的输出极点P1作为为主极点负载电容为2.2uF以上，为不引入低频零点，影响系统稳定性，片外电容CL的串联寄生电阻Resr要小于10mΩ。The output pole P1 of the output terminal is used as the main pole and the load capacitance is more than 2.2uF. In order not to introduce low-frequency zero point and affect the system stability, the series parasitic resistance Resr of the off-chip capacitor CL should be less than 10mΩ.

调整管Mp的栅极引入次极点P₂，由于第八PMOS管MB₄为二极管连接形式，则： _The gate of the adjusting transistor Mp introduces the secondary pole P2, since the eighth PMOS transistor _MB4 is in the form of a diode connection, then:

RpRp ≈≈ 11 gmbgmb 44

PP 22 ≈≈ gmbgmb 44 CpCp

其中，gmb4为第八PMOS管MB₄跨导。设计第八PMOS管MB₄宽长比使得gmb4足够大，从而把次极点P2推到主极点P1的100倍以上，保证系统稳定性。Wherein, gmb4 is the transconductance of the eighth PMOS transistor MB ₄ . The width-to-length ratio of the eighth PMOS transistor MB ₄ is designed so that gmb4 is large enough to push the secondary pole P2 to more than 100 times of the main pole P1 to ensure system stability.

由于误差放大器的输出电阻Ro较小，并且其所带负载电容Co也很小，其产生的极点P₃将工作在高频处。Because the output resistance Ro of the error amplifier is small, and its load capacitance Co is also very small, the pole P ₃ generated by it will work at high frequency.

补偿电容Cm和电阻反馈电路中的第一电阻R₁、第二电阻R₂产生一对零极点，Zm和Pm，设计第一电阻R₁和第二电阻R₂的比值，使得零点Zm补偿误差放大器输出极点P₃，同时使得产生的极点Pm工作于很高频率。补偿电容Cm的引入很好的改善了系统的稳定性。The _first resistor R1 and the _second resistor R2 in the compensation capacitor Cm and the resistance feedback circuit generate a pair of zero poles, Zm and Pm, and the ratio of the _first resistor R1 to the _second resistor R2 is designed so that the zero point Zm compensates for the error The amplifier outputs pole P ₃ while making the resulting pole Pm work at a very high frequency. The introduction of the compensation capacitor Cm improves the stability of the system very well.

本发明提出的集成摆率增强电路的高PSR低压差线性稳压器还具有高电源抑制能力，摆率增强电路将会提高整个环路增益，低频下低压差线性稳压器对电源抑制能力和开环增益成正比，从而提高了低频下的电源抑制比。The high PSR low-dropout linear voltage regulator integrated with the slew rate enhancement circuit proposed by the present invention also has high power supply suppression capability, the slew rate enhancement circuit will improve the whole loop gain, and the low-frequency low-dropout linear voltage regulator has a high power supply suppression capability and The open-loop gain is proportional, which improves the power supply rejection ratio at low frequencies.

低频开环增益Aol如下：The low frequency open loop gain Aol is as follows:

AolAol == ββ ** AA EAEA ** GmG m ** gmpgmp gmbgmb 44 ** (( gdspgdsp ++ GLGL )) == ββ ** AA EAEA ** GmG m ** gmpgmp ** RoutRouting gmbgmb 44

其中，为反馈因子,gmp为调整管Mp的跨导，gmb4为第八PMOS管MB₄的跨导，Gm为摆率增强电路的等效跨导，A_EA为误差放大器增益，Rout为输出等效电阻，gdsp为功率管Mp的输出导纳，GL为负载电阻的倒数。。in, is the feedback factor, gmp is the transconductance of the adjustment tube Mp, _gmb4 is the transconductance of the eighth PMOS transistor MB4, Gm is the equivalent transconductance of the slew rate enhancement circuit, A _EA is the gain of the error amplifier, and Rout is the output equivalent resistance , gdsp is the output admittance of the power tube Mp, and GL is the reciprocal of the load resistance. .

由于误差放大器输出极点P1被补偿电容Cm产生的零点补偿掉，所以误差放大器输出极点P1和补偿电容Cm不会对PSR产生影响。通过计算，高频小信号输出电压v_out与高频小信号输入电源电压v_in的比值如下式：Since the error amplifier output pole P1 is compensated by the zero generated by the compensation capacitor Cm, the error amplifier output pole P1 and the compensation capacitor Cm will not affect the PSR. By calculation, the ratio of the high-frequency small-signal output voltage v _out to the high-frequency small-signal input power supply voltage v _in is as follows:

vv outout vv inin ≈≈ gdspgdsp (( gmbgmb 44 ++ sCpsCp )) (( sCLsCL ++ gdspgdsp ++ GLGL )) (( sCpsCp ++ gmbgmb 44 )) ++ AolAol ** gmbgmb 44 ** (( gdspGLgdspGL ))

PSR传输函数有一个零点在频率处，该零点将会使得系统PSR降低，然而很快就有两个极点产生，第一个极点抵消零点对PSR的削弱，第二个极点将使得系统PSR上升。在更高频率处负载电容的等效电感将会使得整个系统PSR降低。The PSR transfer function has a zero at frequency At , this zero will reduce the PSR of the system, but soon there will be two poles, the first pole cancels the weakening of the PSR by the zero, and the second pole will increase the PSR of the system. The equivalent inductance of the load capacitor at higher frequencies will lower the overall system PSR.

如图4所示，为电源电压2V输出负载200mA的增益相位曲线图。A为相位曲线，B为增益曲线。在负载200mA时，相位裕度为75.26°，系统稳定。As shown in Figure 4, it is the gain-phase curve of the power supply voltage 2V output load 200mA. A is the phase curve, B is the gain curve. When the load is 200mA, the phase margin is 75.26°, and the system is stable.

如图5所示，为电源电压2V输出负载0A的增益相位曲线图。A为相位曲线，B为增益曲线。在负载为0A时，相位裕度为77.15°，系统稳定。As shown in Figure 5, it is a gain-phase curve diagram of a power supply voltage of 2V outputting a load of 0A. A is the phase curve, B is the gain curve. When the load is 0A, the phase margin is 77.15°, and the system is stable.

采用和本发明一样的工艺库、一样的功耗、一样的负载RL及片外电容CL，重新设计背景技术中所提文献的结构，图6和图7将对该结构LDO和本发明LDO的负载调整率和线性调整率进行比较。Adopt the same process library as the present invention, the same power consumption, the same load RL and the off-chip capacitor CL, redesign the structure of the document mentioned in the background technology, and Fig. 6 and Fig. 7 will explain the structure of the LDO and the LDO of the present invention Load regulation and line regulation are compared.

如图6所示，为电源电压2V输出负载1us由0A跳到200mA，再由200mA跳到0A的瞬态特性图。A为背景技术所提文献（Mohammad Al-Shyoukh,Hoi Leeand and Raul Perez.ATransient-Enhanced Low-Quiescent Current Low-Dropout Regulator With BufferImpedance Attenuation.IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.42,NO.8,AUGUST2007）中LDO的输出电压随负载的变化曲线，B为本发明LDO的输出电压随负载的变化曲线压，C为负载的瞬态变化。As shown in Figure 6, it is a transient characteristic diagram of the power supply voltage 2V output load 1us jumping from 0A to 200mA, and then jumping from 200mA to 0A. A is the document proposed by the background technology (Mohammad Al-Shyoukh, Hoi Leeand and Raul Perez. A Transient-Enhanced Low-Quescent Current Low-Dropout Regulator With Buffer Impedance Attenuation. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.42, NO.8, In AUGUST2007), the output voltage of the LDO varies with the load curve, B is the output voltage of the LDO of the present invention varies with the load curve, and C is the transient change of the load.

背景技术所提文献中LDO的输出电压在负载1us由0A跳到200mA时，输出电压在50us后才能稳定，并且下冲的峰值为96.2mV，在负载1us由200mA跳到0A时，输出电压在5us以内就稳定了，上冲的峰值为30.2mV，其负载调整率为0.33mV/mA。Background Art The output voltage of the LDO mentioned in the literature is when the load 1us jumps from 0A to 200mA, the output voltage can be stabilized after 50us, and the peak value of the undershoot is 96.2mV, when the load 1us jumps from 200mA to 0A, the output voltage is at It will be stable within 5us, the peak value of the overshoot is 30.2mV, and its load regulation rate is 0.33mV/mA.

本发明LDO的输出电压在负载1us由0A跳到200mA时，输出电压在5us内就能稳定，并且下冲的峰值为2.9mV，在负载1us由200mA跳到0A时，输出电压在5us以内就能稳定，并且上冲的峰值为2.7mV，本发明的低压差线性稳压器负载调整率为0.0135mV/mA，本发明的低压差线性稳压器对负载的调整率远远好于背景技术中的LDO。The output voltage of the LDO of the present invention jumps from 0A to 200mA when the load is 1us, the output voltage can be stable within 5us, and the peak value of the undershoot is 2.9mV, and when the load 1us jumps from 200mA to 0A, the output voltage is stable within 5us Can be stable, and the peak value of overshoot is 2.7mV, the load adjustment rate of the low dropout linear voltage regulator of the present invention is 0.0135mV/mA, the adjustment rate of the low dropout linear voltage regulator of the present invention is far better than the background technology LDO in.

如图7为输出负载200mA下电源电压1us由2V跳到3.3V的瞬态特性图。A为背景技术所提文献中LDO的输出电压随输入电压的变化曲线，B为本发明LDO的输出电压随输入电压的变化曲线压，C为输入电压的瞬态变化。Figure 7 is a transient characteristic diagram of the power supply voltage 1us jumping from 2V to 3.3V under the output load of 200mA. A is the change curve of the output voltage of the LDO with the input voltage in the literature mentioned in the background technology, B is the change curve of the output voltage of the LDO of the present invention with the input voltage, and C is the transient change of the input voltage.

背景技术所提文献中LDO的输入电压1us由2V跳到3.3V时，输出电压在50us后才稳定，最大峰值为66.6mV；当电源电压1us由3.3V跳到2V时，输出电压在10us后才稳定，最大峰值为26.8mV。其线性调整率为1.38%。Background technology When the input voltage 1us of the LDO in the mentioned literature jumps from 2V to 3.3V, the output voltage stabilizes after 50us, and the maximum peak value is 66.6mV; when the power supply voltage 1us jumps from 3.3V to 2V, the output voltage is 10us Only stable, the maximum peak value is 26.8mV. Its linear adjustment rate is 1.38%.

本发明LDO的输入电压1us由2V跳到3.3V时，输出电压在2us内稳定，最大峰值为0.694mV；当电源电压1us由3.3V跳到2V时，输出电压在2us内稳定，最大压差为0.9mV。本发明的低压差线性稳压器的线性调整率为0.053%，远远好于背景技术中的LDO，线性调制率得到了很大改善。When the input voltage 1us of the LDO of the present invention jumps from 2V to 3.3V, the output voltage is stable within 2us, and the maximum peak value is 0.694mV; when the power supply voltage 1us jumps from 3.3V to 2V, the output voltage is stable within 2us, and the maximum voltage difference is 0.9mV. The linear adjustment rate of the low dropout linear voltage regulator of the present invention is 0.053%, which is far better than that of the LDO in the background technology, and the linear modulation rate has been greatly improved.

如图8为输出负载分别为1mA、10mA、100mA、200mA的电源抑制比。其中，A为1mA的电源抑制比曲线，B为10mA的电源抑制比曲线，C为100mA的电源抑制比曲线，D为200mA的电源抑制比曲线。Figure 8 shows the power supply rejection ratios when the output loads are 1mA, 10mA, 100mA, and 200mA respectively. Among them, A is the power supply rejection ratio curve of 1mA, B is the power supply rejection ratio curve of 10mA, C is the power supply rejection ratio curve of 100mA, and D is the power supply rejection ratio curve of 200mA.

输出负载为1mA时，低频PSR为-72.82dB,100kHz时为-69.65dB，1MHz时为-69.16dB，10MHz时为-89.41dB；输出负载为10mA时，低频PSR为-73.73dB,100kHz时为-69.09dB，1MHz时为-55.596dB，10MHz时为-69.28dB；输出负载为100mA时，低频PSR为-68.08dB,100kHz时为-67.64dB，1MHz时为-61.34dB，10MHz时为-57.84dB；输出负载为200mA时，低频PSR为-59.29dB,100kHz时为-59.39dB，1MHz时为-68.13dB，10MHz时为-56.8dB。不同负载下的PSR曲线符合理论分析。在频率为10MHz时，最小的电源抑制比为-56.8dB，本发明有效提高了电源抑制比，特别是高频下的电源抑制比。When the output load is 1mA, the low frequency PSR is -72.82dB, -69.65dB at 100kHz, -69.16dB at 1MHz, -89.41dB at 10MHz; when the output load is 10mA, the low frequency PSR is -73.73dB, -69.09dB, -55.596dB at 1MHz, -69.28dB at 10MHz; LF PSR is -68.08dB at 100mA output load, -67.64dB at 100kHz, -61.34dB at 1MHz, -57.84 at 10MHz dB; when the output load is 200mA, the low frequency PSR is -59.29dB, -59.39dB at 100kHz, -68.13dB at 1MHz, -56.8dB at 10MHz. The PSR curves under different loads are consistent with the theoretical analysis. When the frequency is 10MHz, the minimum power supply rejection ratio is -56.8dB, and the invention effectively improves the power supply rejection ratio, especially the power supply rejection ratio at high frequency.

本领域的普通技术人员将会意识到，这里所述的实例是为了帮助读者理解本发明的原理，应被理解为本发明的保护范围并不局限与这样的特别陈述和实例。以上实施例仅用以说明本发明的技术方案。本领域的普通技术人员应当理解，可以对本方向的技术方案进行修改或者等同替换，而不脱离本方面技术方案的精神和范围，均应涵盖在本发明的权利保护范围当中。Those skilled in the art will appreciate that the examples described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and examples. The above embodiments are only used to illustrate the technical solution of the present invention. Those of ordinary skill in the art should understand that the technical solutions in this direction can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions in this aspect, and all should be covered by the protection scope of the present invention.