CN103440879A - Address change monitoring circuit, device and generation method thereof - Google Patents

公开了一种地址变化监测电路、装置和方法。该电路包括：清零和延迟单元，在第二输入端接收输入信号以及在第一输入端接收反相的输入信号；翻转单元，串联连接在第一输出端和第二输出端之间；以及判断单元，基于第一和第二输出端上的信号之间的逻辑关系，输出时序信号。根据实施例的方法可生成不同速度的地址变化监测电路，满足不同尺寸的存储电路的要求。

Disclosed are an address change monitoring circuit, device and method. The circuit includes: a clearing and delay unit receiving an input signal at a second input terminal and an inverted input signal at a first input terminal; an inversion unit connected in series between the first output terminal and the second output terminal; and The judging unit outputs timing signals based on the logic relationship between the signals on the first and second output terminals. The method according to the embodiment can generate address change monitoring circuits with different speeds to meet the requirements of storage circuits with different sizes.

地址变化监测电路、装置及其生成方法Address change monitoring circuit, device and generating method thereof

技术领域technical field

本技术大体涉及存储类集成电路中所使用的地址变化监测，具体涉及一种地址变化监测电路、装置以及生成该电路的方法。The technology generally relates to address change monitoring used in storage integrated circuits, and specifically relates to an address change monitoring circuit, device and method for generating the circuit.

背景技术Background technique

很多集成电路中需要使用存储电路，例如静态随机存储器或闪速存储器，用于临时保存电子系统运行所需的中间数据，或长期保存某些记录数据。存储电路中往往集成有地址变化监测电路，它在存储地址变化时生成存储电路进行读取操作所需的时序控制信号。Many integrated circuits need to use storage circuits, such as static random access memory or flash memory, to temporarily store intermediate data required for the operation of electronic systems, or to store certain recorded data for a long time. An address change monitoring circuit is often integrated in the storage circuit, which generates a timing control signal required for the storage circuit to perform a read operation when the storage address changes.

如图1所示，根据现有技术的地址变化监测电路包括由多个地址传输监测(ATD)单元101和逻辑电路102(如图1所示的逻辑或电路)。地址变化监测电路的多个输入端子103接收多条地址信号A[0]，…，A[N-1]。地址变化监测电路的输出端子104输出为存储电路的读取操作提供的时序控制信号ATD。图2示出了如图1所示的ATD单元的电路图。As shown in FIG. 1 , the address change monitoring circuit according to the prior art includes a plurality of address transfer monitoring (ATD) units 101 and a logic circuit 102 (logic OR circuit as shown in FIG. 1 ). Multiple input terminals 103 of the address change monitoring circuit receive multiple address signals A[0], . . . , A[N-1]. The output terminal 104 of the address change monitoring circuit outputs the timing control signal ATD provided for the read operation of the memory circuit. FIG. 2 shows a circuit diagram of the ATD unit shown in FIG. 1 .

如图2所示，每个ATD单元包括接收输入信号AIN的输入端子和输出时序信号ATDU的输出端子。每个ATD单元中，经过多个串联的延迟单元延迟后的输入信号与未延迟的输入信号AIN输入到或非门电路的输入端，在输出端输出时序信号ATDU。As shown in FIG. 2 , each ATD unit includes an input terminal for receiving an input signal AIN and an output terminal for outputting a timing signal ATDU. In each ATD unit, the input signal delayed by multiple series-connected delay units and the undelayed input signal AIN are input to the input terminal of the NOR gate circuit, and the timing signal ATDU is output at the output terminal.

图3示出了如图2所示的ATD单元的输入输出信号时序图。如图3所示，当输入的地址信号产生逻辑变化时，例如从逻辑“0”变成“1”时，ATD单元的输出端会产生高电平区间，其可以对应存储电路读操作所需的时间T的读取有效信号。FIG. 3 shows a timing diagram of input and output signals of the ATD unit shown in FIG. 2 . As shown in Figure 3, when the input address signal changes logic, for example, from logic "0" to "1", the output terminal of the ATD unit will generate a high-level interval, which can correspond to the read operation of the storage circuit. The read valid signal of time T.

一方面，如图2所示的电路由于采用了缓冲器与电容器的串并结构，无法通过简单地增加或者减少某些部件来形成新的地址变化监测电路。因此，现有技术中，针对不同速度和存储尺寸的存储电路都需要新设计地址变化监测电路。On the one hand, since the circuit shown in FIG. 2 adopts a serial-parallel structure of buffers and capacitors, it is impossible to form a new address change monitoring circuit by simply adding or subtracting some components. Therefore, in the prior art, an address change monitoring circuit needs to be newly designed for storage circuits with different speeds and storage sizes.

另一方面，以计算机算法为实现基础，可以生成存储电路，满足集成电路设计人员对于闪速存储电路的不同的尺寸要求。通常需要预先人工设计一组不同速度的地址变化监测电路，以对应不同尺寸存储电路的读取速度。但是，现有技术中，难以通过自动算法生成各种不同速度(不同的有效时间T)的地址变化监测电路。On the other hand, based on computer algorithms, memory circuits can be generated to meet the different size requirements of integrated circuit designers for flash memory circuits. Usually, a group of address change monitoring circuits with different speeds need to be manually designed in advance to correspond to the reading speeds of storage circuits of different sizes. However, in the prior art, it is difficult to generate address change monitoring circuits with various speeds (different effective times T) through an automatic algorithm.

发明内容Contents of the invention

考虑到现有技术中的一个或多个问题，提出了一种地址变化监测电路、装置及其生成方法。Considering one or more problems in the prior art, an address change monitoring circuit, device and generating method thereof are proposed.

根据本技术的实施例，一种地址变化监测电路，包括：清零和延迟单元，具有第一输入端和第二输入端以及第一输出端和第二输出端，在所述第二输入端接收输入信号以及在第一输入端接收反相的输入信号；翻转单元，串联连接在所述第一输出端和所述第二输出端之间；以及判断单元，基于所述第一输出端上的信号和所述第二输出端上的信号之间的逻辑关系，输出时序信号；其中，所述第二输出端处的输入信号从逻辑低改变为逻辑高之前，所述第一输出端处的信号处于逻辑低，所述第二输出端处的信号处于逻辑高，所述判断单元的输出端处的信号处于逻辑低，当第二输入端处的信号从逻辑低变化成逻辑高时，迫使所述第二输出端处的信号变为强逻辑低，而所述第一输入端处的信号变为逻辑高，使得所述清零和延迟单元解除了对所述第一输出端处信号的控制，所述第二输出端和所述第一输出端处的信号均为逻辑低，所述判断单元在其输出端输出逻辑高，开始使存储电路的读操作有效，所述翻转单元在受到所述第二输出端处产生的强逻辑低的影响，对所述第一输出端产生较弱的翻转逻辑，当所述第一输出端受此作用变为逻辑高时，所述判断单元通过判断所述第一输出端和所述第二输出端处的信号之间的逻辑关系，在其输出端处输出逻辑低，结束存储电路的读操作。According to an embodiment of the present technology, an address change monitoring circuit includes: a clearing and delay unit having a first input terminal and a second input terminal and a first output terminal and a second output terminal, and at the second input terminal receiving an input signal and receiving an inverted input signal at a first input terminal; an inversion unit connected in series between the first output terminal and the second output terminal; and a judging unit based on the first output terminal The logical relationship between the signal on the second output terminal and the signal on the second output terminal, output timing signal; wherein, before the input signal at the second output terminal changes from logic low to logic high, the first output terminal The signal at the logic low, the signal at the second output terminal is logic high, the signal at the output terminal of the judgment unit is logic low, when the signal at the second input terminal changes from logic low to logic high, forcing the signal at the second output to a strong logic low while the signal at the first input goes to a logic high such that the clear and delay unit deasserts the signal at the first output control, the signals at the second output terminal and the first output terminal are both logic low, the judgment unit outputs logic high at its output terminal, and start to make the read operation of the storage circuit effective, and the flipping unit is at Affected by the strong logic low generated at the second output terminal, a weaker inversion logic is generated on the first output terminal, and when the first output terminal is affected by this effect and becomes logic high, the judgment unit By judging the logic relationship between the signals at the first output terminal and the second output terminal, a logic low is output at the output terminal, and the read operation of the storage circuit is ended.

根据本技术的实施例，一种地址变化监测装置，包括：According to an embodiment of the present technology, an address change monitoring device includes:

多个并联的地址变化监测电路，每个地址变化检测电路为如上所述的地址变化监测电路；A plurality of parallel address change detection circuits, each address change detection circuit is an address change detection circuit as described above;

或电路，接收从所述多个地址变化监测电路输出的时序信号，输出用于存储器读取操作的时序控制信号。An OR circuit receives timing signals output from the plurality of address change monitoring circuits, and outputs timing control signals for memory read operations.

根据本技术的实施例，一种利用计算机生成地址变化监测电路的方法，包括步骤：提供至少一个或并联的多个清零和延迟单元，每个清零和延迟单元具有第一和第二输入端以及第一和第二输出端，在所述第二输入端接收输入信号以及在第一输入端接收反相的输入信号；提供翻转单元，所述翻转单元串联连接在所述第一输出端和所述第二输出端之间；提供判断单元，所述判断单元基于所述第一输出端上的信号和所述第二输出端上的信号之间的逻辑关系，输出时序信号；提供或电路，所述或电路接收从多个地址变化监测电路输出的时序信号，输出用于存储器读取操作的时序控制信号；其中，所述第二输出端处的输入信号从逻辑低改变为逻辑高之前，所述第一输出端处的信号处于逻辑低，所述第二输出端处的信号处于逻辑高，所述判断单元的输出端处的信号处于逻辑低，当第二输入端处的信号从逻辑低变化成逻辑高时，迫使所述第二输出端处的信号变为强逻辑低，而所述第一输入端处的信号变为逻辑高，使得所述清零和延迟单元解除了对所述第一输出端处信号的控制，所述第二输出端和所述第一输出端处的信号均为逻辑低，所述判断单元在其输出端输出逻辑高，开始使存储电路的读操作有效，所述翻转单元在受到所述第二输出端处产生的强逻辑低的影响，对所述第一输出端产生较弱的翻转逻辑，当所述第一输出端受此作用变为逻辑高时，所述判断单元通过判断所述第一输出端和所述第二输出端处的信号之间的逻辑关系，在其输出端处输出逻辑低，结束存储电路的读操作。According to an embodiment of the present technology, a method of utilizing a computer to generate an address change monitoring circuit includes the steps of: providing at least one or a plurality of clearing and delaying units connected in parallel, each clearing and delaying unit having first and second inputs terminal and first and second output terminals, an input signal is received at the second input terminal and an inverted input signal is received at the first input terminal; an inversion unit is provided, and the inversion unit is connected in series at the first output terminal and between the second output terminal; a judging unit is provided, and the judging unit outputs a timing signal based on the logic relationship between the signal on the first output terminal and the signal on the second output terminal; providing or A circuit, the OR circuit receives timing signals output from a plurality of address change monitoring circuits, and outputs a timing control signal for a memory read operation; wherein, the input signal at the second output terminal changes from logic low to logic high Before, the signal at the first output terminal is logic low, the signal at the second output terminal is logic high, the signal at the output terminal of the judgment unit is logic low, when the signal at the second input terminal is A change from a logic low to a logic high forces the signal at the second output to a strong logic low while the signal at the first input goes to a logic high, causing the clear and delay unit to deactivate For the control of the signal at the first output terminal, the signals at the second output terminal and the first output terminal are both logic low, and the judgment unit outputs logic high at its output terminal, starting to make the storage circuit The read operation is valid, the inversion unit is affected by the strong logic low generated at the second output terminal, and generates a weaker inversion logic on the first output terminal, and when the first output terminal is affected by this effect, it becomes When it is logic high, the judging unit outputs a logic low at its output end by judging the logic relationship between the signals at the first output end and the second output end, and ends the read operation of the storage circuit.

根据本技术实施例的地址变化监测电路和地址变化监测装置用于监测外部地址信号变化，为存储类集成电路的读取操作提供时序控制信号。另外，本技术的实施例应用于集成电路中不同尺寸的存储电路中地址变化监测电路的快速生成，以满足集成电路设计人员对于存储电路读取速度的不同需求。The address change monitoring circuit and the address change monitoring device according to the embodiments of the present technology are used to monitor changes of external address signals, and provide timing control signals for read operations of storage integrated circuits. In addition, the embodiments of the present technology are applied to the rapid generation of address change monitoring circuits in storage circuits of different sizes in integrated circuits, so as to meet the different requirements of integrated circuit designers for the reading speed of storage circuits.

附图说明Description of drawings

根据以下说明和所附权利要求，结合附图，本公开的前述和其他特征将更加清楚。在认识到这些附图仅仅示出了根据本公开的一些示例且因此不应被认为是限制本公开范围的前提下，通过使用附图以额外的特征和细节来详细描述本公开，附图中：The foregoing and other features of the present disclosure will become more apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. The disclosure is described in detail with additional character and detail through the use of the accompanying drawings, with the understanding that these drawings only illustrate some examples according to the disclosure and therefore should not be considered as limiting the scope of the disclosure. :

图1示出了根据现有技术的地址变化监测电路的结构示意图；FIG. 1 shows a schematic structural diagram of an address change monitoring circuit according to the prior art;

图2示出了如图1所示的地址变化监测电路中的ATD单元的电路图；Fig. 2 shows the circuit diagram of the ATD unit in the address change monitoring circuit shown in Fig. 1;

图3示出了如图2所示的ATD单元的输入输出信号时序关系；Fig. 3 shows the timing relationship of the input and output signals of the ATD unit as shown in Fig. 2;

图4A示出了根据本技术一个实施例的地址变化监测电路的示意性框图；FIG. 4A shows a schematic block diagram of an address change monitoring circuit according to one embodiment of the present technology;

图4B示出了如图4A所示的地址变化监测电路的示意性时序图；FIG. 4B shows a schematic timing diagram of the address change monitoring circuit shown in FIG. 4A;

图5是描述根据本技术的地址变化监测电路的生成方法的流程图；5 is a flowchart describing a method of generating an address change monitoring circuit according to the present technology;

图6示出了根据本技术另一实施例的地址变化监测电路的示意性框图；以及6 shows a schematic block diagram of an address change monitoring circuit according to another embodiment of the present technology; and

图7示出了根据本技术的又一实施例的地址变化监测电路的示意性电路图。FIG. 7 shows a schematic circuit diagram of an address change monitoring circuit according to yet another embodiment of the present technology.

具体实施方式Detailed ways

将在下文中结合附图对本技术的实施例进行详细描述。虽然结合实施例进行阐述，但应理解为这并非意指将本技术限定于这些实施例中。相反，本技术意在涵盖由所附权利要求所界定的本技术精神和范围内所定义的各种可选方案、修改方案和等同方案。Embodiments of the present technology will be described in detail below with reference to the accompanying drawings. While described in conjunction with embodiments, it will be understood that it is not intended to limit the present technology to these embodiments. On the contrary, the technology is intended to cover various alternatives, modifications and equivalents as defined within the spirit and scope of the technology as defined by the appended claims.

此外，为了更好的理解本技术，在下面的描述中，阐述了大量具体的细节，比如具体的电路、器件、连接关系等。然而，本技术的领域的普通技术人员应该理解，没有这些具体的细节，本技术依然可以实施。在其他的一些实施例中，为了便于凸显本技术的主旨，对于熟知的技术未作详细的描述。In addition, in order to better understand the present technology, a large number of specific details are set forth in the following description, such as specific circuits, devices, connection relationships, and the like. However, it will be understood by those of ordinary skill in the art that the technology may be practiced without these specific details. In some other embodiments, well-known technologies are not described in detail in order to highlight the gist of the technology.

在下文所述的特定实施例代表本技术的示例性实施例，并且本质上仅为示例说明而非限制。在说明书中，提及“一个实施例”或者“实施例”意味着结合该实施例所描述的特定特征、结构或者特性包括在本技术的至少一个实施例中。术语“在一个实施例中”在说明书中各个位置出现并不全部涉及相同的实施例，也不是相互排除其他实施例或者可变实施例。本说明书中公开的所有特征，或公开的所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以以任何方式组合。此外，本领域普通技术人员应当理解，在此提供的示图都是为了说明的目的，并且示图不一定是按比例绘制的。应当理解，当称“元件”“连接到”或“耦接”到另一元件时，它可以是直接连接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接连接到”或“直接耦接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。The specific embodiments described below represent exemplary embodiments of the technology and are merely illustrative in nature and not limiting. In the specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present technology. The appearances of the term "in one embodiment" in various places in the specification are not all referring to the same embodiment, nor are they intended to mutually exclude other or alternative embodiments. All features disclosed in this specification, or steps in all methods or processes disclosed, may be combined in any manner, except for mutually exclusive features and/or steps. Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It will be understood that when an "element" is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. The same reference numerals designate the same elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

根据本技术实施例的地址变化监测电路和地址变化监测装置用于监测外部地址信号变化，为存储类集成电路的读取操作提供时序控制信号。另外，本技术的实施例应用于集成电路中不同尺寸的存储电路中地址变化监测电路的快速生成，以满足集成电路设计人员对于存储电路读取速度的不同需求。The address change monitoring circuit and the address change monitoring device according to the embodiments of the present technology are used to monitor changes of external address signals, and provide timing control signals for read operations of storage integrated circuits. In addition, the embodiments of the present technology are applied to the rapid generation of address change monitoring circuits in storage circuits of different sizes in integrated circuits, so as to meet the different requirements of integrated circuit designers for the reading speed of storage circuits.

图4A示出了根据本技术一个实施例的地址变化监测电路的示意性框图。图4A所示的地址变化监测电路，在第一层结构上仍如图1所示，区别特征在于ATD单元的内部结构。FIG. 4A shows a schematic block diagram of an address change monitoring circuit according to one embodiment of the present technology. The address change monitoring circuit shown in FIG. 4A is still as shown in FIG. 1 on the first layer structure, and the distinguishing feature lies in the internal structure of the ATD unit.

如图4A所示，每个ATD单元包括清零和延迟单元13、翻转单元11和判断单元12。As shown in FIG. 4A , each ATD unit includes a clearing and delay unit 13 , an inversion unit 11 and a judging unit 12 .

清零和延迟单元13，具有第一输入端和第二输入端以及第一输出端16和第二输出端17。在第二输入端接收来自装置的输入端14的输入信号以及在第一输入端接收反相的输入信号。The clearing and delay unit 13 has a first input terminal and a second input terminal as well as a first output terminal 16 and a second output terminal 17 . The input signal from the input 14 of the device is received at the second input and the inverted input signal is received at the first input.

翻转单元11串联连接在清零和延迟单元13的第一输出端16和第二输出端17之间。The inversion unit 11 is connected in series between the first output terminal 16 and the second output terminal 17 of the clearing and delay unit 13 .

判断单元12基于第一输出端16上的信号和第二输出端17上的信号之间的逻辑关系，在输出端15输出时序信号。The judging unit 12 outputs a timing signal at the output terminal 15 based on the logical relationship between the signal on the first output terminal 16 and the signal on the second output terminal 17 .

例如，ATD单元的输入端14本身及反相的输入信号18连接清零和延迟单元13的两个输入端，控制两个输出端(逻辑寄存点)16和17的信号是否清零。当反相的输入信号18为逻辑“1”时，第一输出端16被置为逻辑“0”。当输入信号14为逻辑“1”时，第二输出端17被置为逻辑“0”。翻转单元11为第一和第二输出端16和17提供较弱逻辑强度的翻转逻辑，也就是其提供的逻辑强度比清零和延迟单元13产生的逻辑强度弱，从而保证第一和第二输出端16和17处的信号在稳定后其逻辑值相反。这里，“逻辑强度”的含义是指产生某个逻辑的驱动源的带载能力比较强，比如说，当输出低电平时，能承受较大的灌电流，输出高电平时能承受较大的拉电流。例如，翻转单元11所提供的翻转逻辑的逻辑强度低于第一和第二输出端16和17上的信号，例如逻辑“0”信号的逻辑强度。然后，判断单元12通过判断第一和第二输出端16和17上的信号之间的逻辑关系，在输出端15输出存储电路的读操作控制时序信号。根据一个实施例，在时间周期T内，当第一和第二输出端16和17的信号均为逻辑“0”时，判断单元12在其输出端15输出信号为逻辑“1”。For example, the input terminal 14 of the ATD unit itself and the inverted input signal 18 are connected to the two input terminals of the clearing and delay unit 13 to control whether the signals of the two output terminals (logic register points) 16 and 17 are cleared. When the inverted input signal 18 is a logic "1", the first output 16 is set to a logic "0". When the input signal 14 is logic "1", the second output terminal 17 is set to logic "0". The inversion unit 11 provides the inversion logic with weaker logic strength for the first and second output terminals 16 and 17, that is, the logic strength provided by it is weaker than the logic strength produced by the clearing and delay unit 13, thereby ensuring that the first and second The signals at outputs 16 and 17 have opposite logical values after stabilization. Here, "logic strength" means that the driving source that generates a certain logic has a relatively strong load capacity. For example, when the output is low, it can withstand a large sink current, and when the output is high, it can withstand a large pull current. For example, the logic strength of the inversion logic provided by the inversion unit 11 is lower than that of the signals on the first and second output terminals 16 and 17 , eg a logic "0" signal. Then, the judging unit 12 outputs a timing signal for controlling the read operation of the storage circuit at the output terminal 15 by judging the logical relationship between the signals on the first and second output terminals 16 and 17 . According to one embodiment, during the time period T, when the signals at the first and second output terminals 16 and 17 are both logic "0", the judgment unit 12 outputs a signal at its output terminal 15 as a logic "1".

根据本发明的一个实施例，当翻转单元12提供从逻辑“0”到逻辑“1”的翻转逻辑时，清零和延迟单元13可以在其输出端16提供对该逻辑“1”的建立延迟一段时间。这例如通过在清零和延迟单元13内设置电容器来实现。存储电路读操作所需的读取有效信号的高电平有效时间T由清零和延迟单元13对第一和第二输出端16和17处的信号施加的延迟能力和翻转单元11施加的逻辑强度共同决定。According to one embodiment of the present invention, when the flipping unit 12 provides flipping logic from a logic "0" to a logic "1", the clear and delay unit 13 may provide a setup delay for this logic "1" at its output 16 a period of time. This is achieved, for example, by arranging capacitors in the clear and delay unit 13 . The high-level effective time T of the read valid signal required for the read operation of the storage circuit is the delay capability applied by the clearing and delay unit 13 to the signals at the first and second output terminals 16 and 17 and the logic applied by the flip unit 11 Intensity is determined jointly.

图4B示出了如图4A所示的地址变化监测电路的示意性时序图。如图4B所示，当ATD单元的输入端14处的地址信号产生地址信号变化前，即从逻辑“0”改变为逻辑“1”之前，第一输出端16处的信号处于逻辑“0”，第二输出端17处的信号处于逻辑“1”，判断单元12的输出端15处的信号处于逻辑“0”。当输入端14处的信号从逻辑“0”变化成逻辑“1”时，会迫使第二输出端17处的信号变为强逻辑“0”，而经过反相器20反相后的输入信号18变为逻辑“0”，使得清零和延迟单元13解除了对第一输出端16处信号的控制。此时第二输出端17和第一输出端16处的信号均为逻辑“0”，从而判断单元12在其输出端15输出逻辑“1”，开始使存储电路的读操作有效。翻转单元11在此时受到第二输出端17处产生的强逻辑“0”的影响，对第一输出端16产生较弱的翻转逻辑，当第一输出端16受此作用变为逻辑“1”时，判断单元12通过判断第一输出端16和第二输出端17处的信号之间的逻辑关系，在输出端15处输出逻辑“0”，结束存储电路的读操作。在第一输出端16的信号从“0”变为“1”的过程所花费的时间可以由清零和延迟单元13提供的延迟能力来确定。这样，输出端15处的信号从变为逻辑“1”到恢复逻辑“0”的时间为T。FIG. 4B shows a schematic timing diagram of the address change monitoring circuit shown in FIG. 4A. As shown in FIG. 4B, when the address signal at the input terminal 14 of the ATD unit produces an address signal change, that is, before changing from logic "0" to logic "1", the signal at the first output terminal 16 is at logic "0". , the signal at the second output terminal 17 is logic “1”, and the signal at the output terminal 15 of the judging unit 12 is logic “0”. When the signal at the input terminal 14 changes from logic "0" to logic "1", it will force the signal at the second output terminal 17 to become a strong logic "0", and the input signal inverted by the inverter 20 18 becomes logic “0”, so that the clear and delay unit 13 releases control of the signal at the first output 16 . At this time, the signals at the second output terminal 17 and the first output terminal 16 are both logic "0", so the judgment unit 12 outputs a logic "1" at its output terminal 15, and the read operation of the storage circuit is enabled. Inverting unit 11 is affected by the strong logic "0" generated at the second output terminal 17 at this time, and produces a weaker inverting logic to the first output terminal 16, when the first output terminal 16 is affected by this effect and becomes logic "1" ", the judging unit 12 judges the logical relationship between the signals at the first output terminal 16 and the second output terminal 17, outputs a logic "0" at the output terminal 15, and ends the read operation of the storage circuit. The time it takes for the signal at the first output 16 to change from “0” to “1” can be determined by the delay capability provided by the clear and delay unit 13 . Thus, the time T from when the signal at the output terminal 15 changes to a logic "1" to when it returns to a logic "0" is T.

图5是描述根据本技术的地址变化监测电路的生成方法的流程图。根据本技术的生成方法可以根据特定读取速度来对地址变化监测电路进行配置。FIG. 5 is a flowchart describing a method of generating an address change monitoring circuit according to the present technology. The generation method according to the present technology can configure the address change monitoring circuit according to a specific reading speed.

在步骤51，提供至少一个或并联的多个清零和延迟单元13，每个清零和延迟单元具有第一和第二输入端以及第一和第二输出端16和17，在所述第二输入端接收输入信号以及在第一输入端接收反相的输入信号。In step 51, at least one or a plurality of clearing and delay units 13 connected in parallel are provided, each clearing and delay unit having first and second input terminals and first and second output terminals 16 and 17, in which The two input terminals receive the input signal and the first input terminal receives the inverted input signal.

在步骤52，提供翻转单元11，所述翻转单元11串联连接在所述第一输出端16和所述第二输出端17之间；In step 52, an inversion unit 11 is provided, and the inversion unit 11 is connected in series between the first output terminal 16 and the second output terminal 17;

在步骤53，提供判断单元12，所述判断单元12基于所述第一输出端16上的信号和所述第二输出端17上的信号之间的逻辑关系，输出时序信号；In step 53, a judging unit 12 is provided, and the judging unit 12 outputs a timing signal based on the logical relationship between the signal on the first output terminal 16 and the signal on the second output terminal 17;

在步骤54，提供或电路，所述或电路接收从多个地址变化监测电路输出的时序信号，输出用于存储器读取操作的时序控制信号。In step 54, an OR circuit is provided, the OR circuit receives timing signals output from a plurality of address change monitoring circuits, and outputs a timing control signal for a memory read operation.

当地址变化监测电路的输入端14处的地址信号产生地址信号变化前，即从逻辑“0”改变为逻辑“1”之前，第一输出端16处的信号处于逻辑“0”，第二输出端17处的信号处于逻辑“1”，判断单元12的输出端15处的信号处于逻辑“0”。当输入端14处的信号从逻辑“0”变化成逻辑“1”时，会迫使第二输出端17处的信号变为强逻辑“0”，而经过反相器20反相后的输入信号18变为逻辑“0”，使得清零和延迟单元13解除了对第一输出端16处信号的控制。此时第二输出端17和第一输出端16处的信号均为逻辑“0”，从而判断单元12在其输出端15输出逻辑“1”，开始使存储电路的读操作有效。翻转单元11在此时受到第二输出端17处产生的强逻辑“0”的影响，对第一输出端16产生较弱的翻转逻辑，当第一输出端16受此作用变为逻辑“1”时，判断单元12通过判断第一输出端16和第二输出端17处的信号之间的逻辑关系，在输出端15处输出逻辑“0”，结束存储电路的读操作。在第一输出端16的信号从“0”变为“1”的过程所花费的时间可以由清零和延迟单元13提供的延迟能力来确定。这样，输出端15处的信号从变为逻辑“1”到恢复逻辑“0”的时间为T。When the address signal at the input terminal 14 of the address change monitoring circuit produces before the address signal changes, that is, before changing from logic "0" to logic "1", the signal at the first output terminal 16 is at logic "0", and the second output The signal at terminal 17 is at logic "1", the signal at output 15 of judgment unit 12 is at logic "0". When the signal at the input terminal 14 changes from logic "0" to logic "1", it will force the signal at the second output terminal 17 to become a strong logic "0", and the input signal inverted by the inverter 20 18 becomes logic “0”, so that the clear and delay unit 13 releases control of the signal at the first output 16 . At this time, the signals at the second output terminal 17 and the first output terminal 16 are both logic "0", so the judgment unit 12 outputs a logic "1" at its output terminal 15, and the read operation of the storage circuit is enabled. Inverting unit 11 is affected by the strong logic "0" generated at the second output terminal 17 at this time, and produces a weaker inverting logic to the first output terminal 16, when the first output terminal 16 is affected by this effect and becomes logic "1" ", the judging unit 12 judges the logical relationship between the signals at the first output terminal 16 and the second output terminal 17, outputs a logic "0" at the output terminal 15, and ends the read operation of the storage circuit. The time it takes for the signal at the first output 16 to change from “0” to “1” can be determined by the delay capability provided by the clear and delay unit 13 . Thus, the time T from when the signal at the output terminal 15 changes to a logic "1" to when it returns to a logic "0" is T.

虽然图5中按照序号示出了生成清零和延迟单元的步骤51，生成翻转单元的步骤52、生成判断单元的步骤53、以及生成逻辑或结构的步骤54，但是本领域的普通技术人员应该意识到，上述的步骤之间并无任何的先后顺序。上述的附图标记仅仅是出于描述的目的，而不是限定这些步骤之间的先后关系。Although the step 51 of generating the clearing and delay unit, the step 52 of generating the flipping unit, the step 53 of generating the judging unit, and the step 54 of generating the logic or structure are shown according to the serial numbers in Fig. 5, those of ordinary skill in the art should Realize that there is no sequential order between the above steps. The above reference numerals are for the purpose of description only, and do not limit the sequence relationship between these steps.

在如图5所示的方法中，可以根据特定读取速度来配置清零和延迟单元，例如可通过对于清零和延迟单元13中的模块进行并联配置实现。In the method shown in FIG. 5 , the clearing and delaying unit can be configured according to a specific reading speed, for example, it can be realized by configuring the modules in the clearing and delaying unit 13 in parallel.

图6示出了根据本技术另一实施例的地址变化监测电路的示意性框图。如图6所示，清零和延迟单元13中有本征单元21以及附加单元22。附加单元的个数可以为0，也可以为若干个。单元21和22及与22相当的单元之间具有并联关系。由于翻转逻辑的强度由翻转单元11确定，在此前提下，所产生的逻辑翻转时间(即存储电路读操作的有效时间T)由清零和延迟单元13的逻辑延迟能力唯一确定。根据本发明的实施例，清零和延迟单元13中的单元21及22等的延迟能力相等，但是也可以不相等。FIG. 6 shows a schematic block diagram of an address change monitoring circuit according to another embodiment of the present technology. As shown in FIG. 6 , the clearing and delaying unit 13 includes an intrinsic unit 21 and an additional unit 22 . The number of additional units can be 0 or several. Units 21 and 22 and units equivalent to 22 have a parallel relationship. Since the strength of the inversion logic is determined by the inversion unit 11 , under this premise, the generated logic inversion time (ie, the effective time T of the storage circuit read operation) is uniquely determined by the logic delay capability of the clearing and delay unit 13 . According to an embodiment of the present invention, the delay capabilities of the units 21 and 22 in the clearing and delay unit 13 are equal, but may not be equal.

当需要配置特定的读取速度(即读操作的有效时间T)时，只需对清零和延迟单元13的延迟能力进行配置，即只需对与本征单元21并联的附加单元进行个数或类型上的配置，无需人工进行电路设计。且该配置为并联配置，既无需修改已有布局，也无需修改电路中已有的连接关系，使得该方法可通过计算机程序快速实现。When it is necessary to configure a specific read speed (that is, the effective time T of the read operation), it is only necessary to configure the delay capability of the clearing and delay unit 13, that is, it is only necessary to count the additional units connected in parallel with the intrinsic unit 21. Or configuration on the type, without manual circuit design. Moreover, the configuration is a parallel configuration, and neither the existing layout nor the existing connection relationship in the circuit needs to be modified, so that the method can be quickly realized through a computer program.

图7示出了根据本技术的又一实施例的地址变化监测电路的示意性电路图。如图7所示，清零和延迟单元13中的本征清零和延迟单元31包括第一MOS晶体管，例如NMOS晶体管，其栅极接收反相的输入信号，漏极端作为或连接到第一输出端子16；第一电容器，串联连接在第一MOS晶体管的漏极和源极之间；第二MOS晶体管，例如NMOS晶体管，其栅极接收输入信号，漏极端作为或连接到第二输出端子，第二电容器，串联连接在第二MOS晶体管的漏极和源极之间。图7所示的单元31中NMOS的驱动能力远大于翻转单元11中反相器的驱动能力。另外，单元32和33与单元31的结构基本上相同，并且与单元31在清零和延迟单元13中的连接方式相同。FIG. 7 shows a schematic circuit diagram of an address change monitoring circuit according to yet another embodiment of the present technology. As shown in FIG. 7 , the intrinsic clearing and delaying unit 31 in the clearing and delaying unit 13 includes a first MOS transistor, such as an NMOS transistor, whose gate receives an inverted input signal, and whose drain terminal serves as or is connected to the first Output terminal 16; a first capacitor connected in series between the drain and source of the first MOS transistor; a second MOS transistor, such as an NMOS transistor, whose gate receives an input signal and whose drain serves as or is connected to the second output terminal , a second capacitor connected in series between the drain and the source of the second MOS transistor. The driving capability of the NMOS in the unit 31 shown in FIG. 7 is much greater than that of the inverter in the flipping unit 11 . In addition, units 32 and 33 have basically the same structure as unit 31 and are connected in the same manner as unit 31 in clear and delay unit 13 .

根据本技术实施例的方法可生成不同速度的地址变化监测电路，满足不同尺寸的存储电路的要求。另外，上述方法可由计算机程序实现，提高生成不同速度地址变化监测电路的效率。The method according to the embodiment of the present technology can generate address change monitoring circuits with different speeds to meet the requirements of storage circuits with different sizes. In addition, the above method can be implemented by a computer program to improve the efficiency of generating address change monitoring circuits with different speeds.

如本领域的技术人员可以意识到的那样上述的清零和延迟单元、翻转单元、判断单元既可以由模拟电路实现，也可以由数字电路实现，或由模拟及数字混合电路实现。As those skilled in the art can appreciate, the above-mentioned clearing and delaying unit, flipping unit, and judging unit can be implemented by analog circuits, digital circuits, or mixed analog and digital circuits.

另外，虽然上述实施例中以正逻辑来进行详细描述，但是本领域的技术人员可以意识到，这并不是对本技术的限定，本技术同样可以用于负逻辑系统中。In addition, although positive logic is used for detailed description in the above embodiments, those skilled in the art can realize that this is not a limitation of the present technology, and the present technology can also be used in a negative logic system.

另外，在系统方案的硬件和软件实现方式之间可以存在一些小差别。硬件或软件的使用一般(但并非总是，因为在特定情况下硬件和软件之间的选择可能变得很重要)是一种体现成本与效率之间权衡的设计选择。可以各种手段(例如，硬件、软件和/或固件)来实施这里所描述的系统和/或其他技术，并且优选的方案随着所应用的环境而改变。例如，如果实现方确定速度和准确性是最重要的，则实现方可以选择主要为硬件和/或固件的手段；如果灵活性是最重要的，则实现方可以选择主要是软件的实施方式；或者，同样也是可选地，实现方可以选择硬件、软件和/或固件的特定组合。Additionally, some minor differences may exist between hardware and software implementations of system solutions. The use of hardware or software is generally (but not always, since the choice between hardware and software may become important in specific cases) a design choice that embodies a trade-off between cost and efficiency. The systems described herein and/or other techniques can be implemented by various means (eg, hardware, software, and/or firmware), and the preferred approach varies with the circumstances of the application. For example, if the implementer determines that speed and accuracy are paramount, the implementer may choose a primarily hardware and/or firmware approach; if flexibility is paramount, the implementer may select a primarily software implementation; Or, also optionally, an implementer may choose a particular combination of hardware, software, and/or firmware.

以上的详细描述通过使用方框图、流程图和/或示例，已经阐述了设备和/或方法的众多实施例。在这种方框图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种方框图、流程图或示例中的每一功能和/或操作可以通过各种硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。在一个实施例中，本技术所述主题的若干部分可以通过专用集成电路(ASIC)、现场可编程门阵列(FPGA)、数字信号处理器(DSP)、或其他集成格式来实现。然而，本领域技术人员应认识到，这里所公开的实施例的一些方面在整体上或部分地可以等同地实现在集成电路中，实现为在一台或多台计算机上运行的一个或多个计算机程序(例如，实现为在一台或多台计算机系统上运行的一个或多个程序)，实现为在一个或多个处理器上运行的一个或多个程序(例如，实现为在一个或多个微处理器上运行的一个或多个程序)，实现为固件，或者实质上实现为上述方式的任意组合，并且本领域技术人员根据本公开，将具备设计电路和/或写入软件和/或固件代码的能力。此外，本领域技术人员将认识到，本公开所述主题的机制能够作为多种形式的程序产品进行分发，并且无论实际用来执行分发的信号承载介质的具体类型如何，本技术所述主题的示例性实施例均适用。信号承载介质的示例包括但不限于：可记录型介质，如软盘、硬盘驱动器、紧致盘(CD)、数字通用盘(DVD)、数字磁带、计算机存储器等；以及传输型介质，如数字和/或模拟通信介质(例如，光纤光缆、波导、有线通信链路、无线通信链路等)。The foregoing detailed description has set forth numerous embodiments of devices and/or methods by using block diagrams, flowcharts, and/or examples. Where such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, those skilled in the art will understand that each function and/or operation in such block diagrams, flowcharts, or examples may Individually and/or collectively implemented by various hardware, software, firmware, or essentially any combination thereof. In one embodiment, several portions of the subject matter described in this technology may be implemented in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), digital signal processors (DSPs), or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein may be equivalently implemented in whole or in part in an integrated circuit, implemented as one or more Computer programs (e.g., implemented as one or more programs running on one or more computer systems), implemented as one or more programs running on one or more processors (e.g., implemented as One or more programs running on multiple microprocessors), implemented as firmware, or substantially implemented as any combination of the above methods, and those skilled in the art will have the ability to design circuits and/or write software and and/or firmware code capabilities. Furthermore, those skilled in the art will recognize that the mechanisms of the subject matter described in this disclosure can be distributed as a variety of forms of program products and that regardless of the specific type of signal bearing media actually used to carry out the distribution, the subject matter described in the present technology Exemplary embodiments are applicable. Examples of signal bearing media include, but are not limited to: recordable-type media such as floppy disks, hard drives, compact discs (CDs), digital versatile discs (DVDs), digital tapes, computer memory, etc.; and transmission-type media such as digital and and/or simulated communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

本领域技术人员应认识到，上文详细描述了设备和/或工艺，此后使用工程实践来将所描述的设备和/或工艺集成到数据处理系统中是本领域的常用手段。也即，这里所述的设备和/或工艺的至少一部分可以通过合理数量的试验而被集成到数据处理系统中。本领域技术人员将认识到，典型的数据处理系统一般包括以下各项中的一项或多项：系统单元外壳；视频显示设备；存储器，如易失性和非易失性存储器；处理器，如微处理器和数字信号处理器；计算实体，如操作系统、驱动程序、图形用户接口、以及应用程序；一个或多个交互设备，如触摸板或屏幕；和/或控制系统，包括反馈环和控制电机(例如，用于感测位置和/或速度的反馈；用于移动和/或调节成分和/或数量的控制电机)。典型的数据处理系统可以利用任意合适的商用部件(如数据计算/通信和/或网络计算/通信系统中常用的部件)予以实现。Those skilled in the art should recognize that the above described devices and/or processes in detail, and then using engineering practice to integrate the described devices and/or processes into a data processing system is a common means in the art. That is, at least a portion of the devices and/or processes described herein can be integrated into a data processing system with a reasonable amount of experimentation. Those skilled in the art will recognize that a typical data processing system generally includes one or more of the following: a system unit housing; a video display device; memory, such as volatile and nonvolatile memory; a processor, such as microprocessors and digital signal processors; computing entities such as operating systems, drivers, graphical user interfaces, and applications; one or more interactive devices such as touchpads or screens; and/or control systems, including feedback loops and control motors (eg, feedback for sensing position and/or velocity; control motors for moving and/or adjusting ingredients and/or quantities). A typical data processing system can be implemented using any suitable commercially available components, such as those commonly used in data computing/communication and/or network computing/communication systems.

本技术所述的主题有时说明不同部件包含在不同的其他部件内或者不同部件与不同的其他部件相连。应当理解，这样描述的架构只是示例，事实上可以实现许多能够实现相同功能的其他架构。在概念上，有效地“关联”用以实现相同功能的部件的任意设置，从而实现所需功能。因此，这里组合实现具体功能的任意两个部件可以被视为彼此“关联”从而实现所需功能，而无论架构或中间部件如何。同样，任意两个如此关联的部件也可以看作是彼此“可操作地连接”或“可操作地耦合”以实现所需功能，且能够如此关联的任意两个部件也可以被视为彼此“能可操作地耦合”以实现所需功能。能可操作地耦合的具体示例包括但不限于物理上可配对和/或物理上交互的部件，和/或无线交互和/或可无线交互的部件，和/或逻辑交互和/或可逻辑交互的部件。The technically described subject matter sometimes illustrates that different components are contained within, or connected with, different other components. It is to be understood that such described architectures are examples only, and that in fact many other architectures can be implemented which achieve the same functionality. In concept, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a specified functionality can be seen as "associated with" each other such that the required functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be considered to be "operably connected" or "operably coupled" to each other to achieve the desired functionality, and any two components capable of being so associated can also be considered to be "operably coupled" to each other. can be operably coupled" to achieve the desired functionality. Specific examples of operable coupling include, but are not limited to, physically mateable and/or physically interacting components, and/or wirelessly interacting and/or wirelessly interacting components, and/or logically interacting and/or logically interactable parts.

至于本文中任何关于多数和/或单数术语的使用，本领域技术人员可以从多数形式转换为单数形式，和/或从单数形式转换为多数形式，以适合具体环境和应用。为清楚起见，在此明确声明单数形式/多数形式可互换。As with any use of plural and/or singular terms herein, those skilled in the art can switch from plural to singular and/or from singular to plural as appropriate to particular circumstances and applications. For clarity, it is expressly stated herein that the singular/plural forms are interchangeable.

本领域技术人员应当理解，一般而言，所使用的术语，特别是所附权利要求中(例如，在所附权利要求的主体部分中)使用的术语，一般地应理解为“开放”术语(例如，术语“包括”应解释为“包括但不限于”，术语“具有”应解释为“至少具有”等)。本领域技术人员还应理解，如果意在所引入的权利要求中标明具体数目，则这种意图将在该权利要求中明确指出，而在没有这种明确标明的情况下，则不存在这种意图。Those skilled in the art will understand that terms used in general, and in particular terms used in the appended claims (eg, in the body of the appended claims), should generally be understood as "open" terms ( For example, the term "comprising" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least" etc.). It will also be understood by those skilled in the art that if a specific number is intended to be identified in an introduced claim, such intent will be explicitly stated in that claim, and in the absence of such explicit identification, no such intention.

以上对本技术的示出示例的描述，包括摘要中所描述的，并不希望是穷尽的或者是对所公开的精确形式的限制。尽管出于说明性目的在此描述了本技术的特定实施例和示例，但是在不偏离本技术的更宽的精神和范围的情况下，各种等同修改是可以的。实际上，应当理解，特定信号、电流、频率、功率范围值、时间等被提供用于说明目的，并且其他值也可以用在根据本技术教导的其他实施例和示例中。The above description of illustrated examples of the technology, including what is described in the Abstract, is not intended to be exhaustive or to be limiting to the precise forms disclosed. While specific embodiments of, and examples for, the technology are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the technology. Indeed, it should be understood that specific signal, current, frequency, power range values, times, etc. are provided for illustration purposes, and that other values may also be used in other embodiments and examples in accordance with the teachings of the present technology.