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CN103455469B - A kind of method of control processor frequency, Apparatus and system - Google Patents

️Wed Jun 08 2016

Disclosure of Invention

The embodiment of the invention provides a method, a device and a system for controlling processor frequency, which aim to solve the technical problems that the cost is increased and the expansibility of an electronic product is reduced due to the fact that the frequency of a multiprocessor in the electronic product is controlled in the prior art.

To solve the above problem, an embodiment of the present invention provides a method for controlling a processor frequency, where the method includes:

acquiring expected frequency parameters of a plurality of processors expected by a user to work and acquiring maximum frequency parameters of the plurality of processors allowed to work;

if the expected frequency parameter is greater than the maximum frequency parameter, generating a first clock signal according to the maximum frequency parameter;

outputting the first clock signal to the processor, and controlling the processor to work at a first frequency corresponding to the first clock signal, wherein the first frequency is a maximum frequency

An embodiment of the present invention further provides a device for controlling a processor frequency, including:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring expected frequency parameters of a plurality of processors expected by a user to work and acquiring maximum frequency parameters of the plurality of processors allowed to work;

a first generating unit, configured to generate a first clock signal according to the maximum frequency parameter when the desired frequency parameter is greater than the maximum frequency parameter;

the first control unit is used for outputting the first clock signal to the processor so as to control the processor to work at a first frequency corresponding to the first clock signal; wherein the first frequency is a maximum frequency.

An embodiment of the present invention further provides a processing system, where the system includes: a one-time programmable logic controller, a one-time programmable logic array device, a frequency limit value memory, an expected value memory, a frequency template comparator, a phase-locked loop, at least two switching devices,

the one-time programmable logic controller is used for acquiring one-time programmable logic array data expected to be programmed, performing format conversion on the one-time programmable logic array data, and outputting the converted one-time programmable logic array data to the one-time programmable logic array device;

the one-time programmable logic array device is used for programming the received and converted one-time programmable logic array data to obtain maximum frequency parameters of the multiple processors allowed to work and permanent high-level signals or low-level signals, sending the maximum frequency parameters of the multiple processors allowed to work to a frequency limiting value memory, and outputting the high-level signals or the low-level signals to corresponding switch equipment;

the frequency limiting value memory is used for storing the maximum frequency parameters which are input by the one-time programmable logic array device and allowed to work by the processors, and outputting the maximum frequency parameters to the frequency template comparator;

the expected value memory is used for acquiring and storing expected frequency parameters of a plurality of processors expected by a user to work and outputting the expected frequency parameters to the frequency template comparator;

the frequency template comparator is used for judging whether the expected frequency parameter is greater than the maximum frequency parameter or not, and if so, outputting the maximum frequency parameter to the phase-locked loop; otherwise, outputting the expected frequency parameter to the phase-locked loop;

the phase-locked loop is used for generating a first clock signal from the maximum frequency parameter input by the frequency template comparator; outputting the first clock signal to a corresponding processor, and controlling the processor to work at a first frequency corresponding to the first clock signal; or generating a second clock signal by using the expected frequency parameter input by the frequency template comparator, outputting the second clock signal to a corresponding processor, and controlling the processor to work at a second frequency corresponding to the second clock signal; wherein the first frequency is a maximum frequency and the second frequency is a desired frequency;

and the switch equipment is used for controlling a processor corresponding to the switch equipment to be in a permanent closing state or an opening state according to the high level signal or the low level signal of the one-time programmable logic array device for several days.

As can be seen from the foregoing technical solutions, in the embodiments of the present invention, by comparing the obtained expected frequency parameter with the maximum frequency parameter (i.e., the frequency limit value), and when the expected frequency parameter is greater than the maximum frequency parameter, a clock signal with a corresponding frequency is generated according to the maximum frequency parameter, and the processor is controlled to operate at a frequency corresponding to the clock signal; thereby achieving the effect of limiting the frequency of the processor.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart of a method for controlling a processor frequency according to an embodiment of the present invention, the method including:

step 101: acquiring expected frequency parameters of a plurality of processors expected by a user to work and acquiring maximum frequency parameters of the plurality of processors allowed to work;

the method comprises the steps of obtaining expected frequency parameters of a plurality of processors expected to work by a user, and obtaining the expected frequency parameters of the plurality of processors through a configuration interface; and stores the desired frequency parameter, such as by a desired memory, etc.

The process of obtaining the maximum frequency parameter of the multiple processors allowed to work comprises the following steps: acquiring the one-time programmable logic (such as eFuse) array data corresponding to the preset frequency parameter (namely, the frequency parameter estimated by a technician according to the application environment of the product during chip design or product layout, or certainly, the frequency parameter can be formulated according to a preset rule) through a bus interface; carrying out format conversion on the one-time programmable logic array data; and programming the one-time programmable logic array data with the converted format to obtain a corresponding maximum frequency parameter, and storing the maximum frequency parameter through a frequency limit value latch. Of course, the one-time programmable logic array data after format conversion can be programmed to obtain not only the corresponding maximum frequency parameter, but also a permanent high level state or a permanent low level state.

The obtaining of the otp array data corresponding to the preset frequency parameter may be performed by a otp controller, and then the otp array data is converted into data of an otp array device interface after internal processing, the otp array data is programmed by the otp array device to obtain a maximum frequency parameter, and the maximum frequency parameter is output to a frequency limit latch for storage, but is not limited thereto, and the process may be implemented by other similar devices, which is not limited in this embodiment.

Step 102: if the expected frequency parameter is greater than the maximum frequency parameter, generating a first clock signal according to the maximum frequency parameter;

in this embodiment, the frequency template comparator may compare the magnitude relationship of the expected frequency parameter stored by the expected value latch with the maximum frequency parameter stored by the frequency limit value latch; when the expected frequency parameter is greater than the maximum frequency parameter (i.e., the frequency limit value), the frequency template comparator outputs the maximum frequency parameter to a phase-locked loop (PLL), otherwise, outputs the expected frequency parameter to the PLL. The PLL is a commonly used basic device, and generates a clock signal corresponding to a frequency according to a value (such as a maximum frequency parameter or an expected frequency parameter) output from the frequency template comparator after receiving the value. The specific generation process is well known to those skilled in the art and will not be described herein.

Step 103: and outputting the first clock signal to the processor, and controlling the processor to work at a first frequency corresponding to the first clock signal. Wherein the first frequency is the maximum frequency.

In this embodiment, the PLL outputs a clock signal with a corresponding frequency to the processor, and controls the processor to operate at a maximum frequency (i.e., a first frequency) corresponding to the first clock signal.

Referring to fig. 2, fig. 2 is a flowchart of another method for controlling processor frequency according to an embodiment of the present invention, the method includes:

step 201: acquiring expected frequency parameters of a plurality of processors expected by a user to work and acquiring maximum frequency parameters of the plurality of processors allowed to work;

the obtaining process of this step is described in detail in step 101, and is not described herein again.

Step 202: judging whether the expected frequency parameter is greater than the maximum frequency parameter, if so, executing step 203 and step 204; otherwise, step 205 and step 206 are executed;

in this step, the frequency template comparator may compare the magnitude relationship between the expected frequency parameter obtained from the expected value latch storage and the maximum frequency parameter obtained from the frequency limit value latch, for example, if the expected frequency parameter corresponds to a frequency of 2GHZ and the maximum frequency parameter corresponds to a frequency of 1GHZ, the frequency template comparator sends the frequency parameter of 1GHZ to the PLL after comparison.

Step 203: generating a first clock signal according to the maximum frequency parameter;

in this step, the PLL generates a clock signal with a corresponding frequency according to the input maximum frequency parameter, which may be compared with a clock reference source of the PLL itself, and then generates the clock signal with the corresponding frequency.

Step 204: outputting the first clock signal to the processor, and controlling the processor to work at a first frequency corresponding to the first clock signal;

step 205: generating a second clock signal according to the expected frequency parameter;

the generating process has the same principle as the generating process of step 203, and is described in detail above, and will not be described herein again.

Step 206: and outputting the second clock signal to the processor, and controlling the processor to work at a second frequency corresponding to the second clock signal. Wherein the second frequency is the desired frequency.

In the embodiment of the invention, by comparing the acquired expected frequency parameter with the maximum frequency parameter (namely, the frequency limit value), and when the expected frequency parameter is greater than the maximum frequency parameter, a first clock signal is generated according to the maximum frequency parameter, and a processor is controlled to work at a first frequency corresponding to the first clock signal; and when the expected frequency parameter is less than or equal to the maximum frequency parameter, generating a second clock signal according to the expected frequency parameter, and controlling the processor to work at a second frequency corresponding to the second clock signal. Thereby achieving the effect of limiting the frequency of the processor.

On the basis of the above embodiment, the method may further include: when the one-time programmable logic array data after the programming format conversion is carried out, a plurality of permanent high-level signals or low-level signals are obtained; controlling a corresponding processor in the plurality of processors to be in a permanent closing state or a permanent opening state according to the high level signal or the low level signal; wherein the on state may include: an active state and an inactive state of the processor.

When the one-time programmable logic array device is used for programming data of the one-time programmable logic array, the internal fuse wire of the one-time programmable logic array device can be programmed only once, and the output of the one-time programmable logic array device is in a permanent high or low level state after programming. It should be noted that, the one-time programmable logic array devices have different capacities and different numbers of output pins.

In the embodiment of the invention, the requirement of permanent frequency limitation on a device (such as a processor) can be realized by using a one-time programmable logic mode.

Optionally, for the processor in the non-permanent off state, the method may further include: if a signal for closing the processor in the non-permanent closing state is received, which is input by the software controller, controlling the corresponding processor in the non-permanent closing state to be in a closing state; and after the processor in the closing non-permanent closing state is in the closing state, if an opening signal for opening the processor in the closing state is received, which is input by the software controller, the processor in the closing state is controlled to be in the opening state.

For example, if one of the processors in the non-permanent off state processes the operating state, and the designer desires to turn off the processor in the operating state, the designer may output a signal for the designer to turn off the processor to the switching device through the software controller, and the switching device turns off the processor after receiving the signal for turning off the desired processor, that is, the processor is in the off state, which may be a permanent off state; if the designer then again desires to turn on this off processor, a signal is sent to the switching device, which turns on the off processor, i.e. the processor is in the on state, also via the software controller, which expects the processor to turn on.

That is, when the otp output signal causes the processor to be in a reset state, the processor is permanently turned off; conversely, for a processor in a non-permanent off state, the processor in the non-permanent off state may be turned off by a control signal output by the software controller, and after the processor is turned off, the processor may be turned on.

For another example, a product supports 2 CPU processors, but when market demand changes, a product with only 1 CPU processor is needed, so that chips do not need to be newly developed and produced, and only one of the CPUs is permanently turned off through one-time programmable logic.

Based on the implementation process of the foregoing method, an embodiment of the present invention further provides a device for controlling a processor frequency, where a corresponding structural schematic diagram is shown in fig. 3, and the device includes: an acquisition unit 31, a first generation unit 32, and a first control unit 33, wherein,

the acquiring unit 31 is configured to acquire an expected frequency parameter at which a user expects a plurality of processors to operate, and acquire a maximum frequency parameter at which the plurality of processors are allowed to operate; the first generating unit 32 is configured to generate a first clock signal according to the maximum frequency parameter when the desired frequency parameter is greater than the maximum frequency parameter; the first control unit 33 is configured to output the first clock signal to the processor, so as to control the processor to operate at a first frequency (i.e., a maximum frequency) corresponding to the first clock signal.

Optionally, the apparatus may further include: the second generating unit is used for generating a second clock signal according to the expected frequency parameter when the expected frequency parameter is less than or equal to the maximum frequency parameter; and the second control unit is used for outputting the second clock signal to the processor and controlling the processor to work at a second frequency (namely a desired frequency) corresponding to the second clock signal.

Optionally, an embodiment of the present invention further provides another apparatus for controlling a frequency of a processor, and a corresponding schematic structural diagram of the apparatus is shown in fig. 4, where the apparatus includes: an acquisition unit 41, a judgment unit 42, a first generation unit 43 and a first control unit 44, a second generation unit 45 and a second control unit 46, wherein,

the obtaining unit 41 is configured to obtain expected frequency parameters of a plurality of processors expected to operate by a user, and obtain maximum frequency parameters of the plurality of processors allowed to operate;

the judging unit 42 is configured to judge whether the expected frequency parameter acquired by the acquiring unit 41 is greater than the maximum frequency parameter, and send a result of the judgment that the expected frequency parameter is greater than the maximum frequency parameter to the first generating unit 43; sending the judgment result smaller than or equal to the second generation unit 45;

the first generating unit 43 is configured to generate a first clock signal according to the maximum frequency parameter when receiving the judgment result that the judgment result is greater than the maximum frequency parameter sent by the judging unit; the first control unit 44 is configured to output the first clock signal to the processor, so as to control the processor to operate at a first frequency corresponding to the first clock signal

The second generating unit 45, when receiving the judgment result that is less than or equal to the judgment result sent by the judging unit, generates a second clock signal according to the expected frequency parameter; the second control unit 46 is configured to output the second clock signal to the processor, and control the processor to operate at a second frequency corresponding to the second clock signal.

Optionally, the obtaining unit includes: a first acquisition unit and a second acquisition unit, wherein,

the first obtaining unit is used for obtaining expected frequency parameters of the multiple processors through a configuration interface; the second obtaining unit is used for obtaining the one-time programmable logic array data corresponding to the preset frequency parameter through a bus interface; carrying out format conversion on the one-time programmable logic array data; and programming the one-time programmable logic array data with the converted format to obtain the maximum frequency parameter of the multiple processors.

Wherein the second acquisition unit includes: the system comprises a one-time programmable logic controller and a one-time programmable logic array device, wherein the one-time programmable logic controller is used for acquiring one-time programmable logic array data corresponding to the preset frequency parameter through a bus interface; converting the one-time programmable logic array data into a format recognized by the one-time programmable logic array device; the one-time programmable logic array device is used for programming the converted one-time programmable logic array data and outputting the maximum frequency parameter of the multiple processors.

Optionally, when the converted one-time programmable logic array data is programmed, the one-time programmable logic array device further outputs a plurality of permanent high-level signals or low-level signals; the apparatus may further comprise: a third acquisition unit and a third control unit, wherein,

the third obtaining unit is used for receiving a plurality of permanent high-level signals or low-level signals output by the one-time programmable logic array device; and the third control unit is used for controlling the corresponding processor in the plurality of processors to be in a permanent closing state or a permanent opening state according to the high level signal or the low level signal.

Optionally, for the processor in the non-permanent off state, the apparatus may further include: further comprising: the device comprises a first receiving unit, a fourth control unit, a second receiving unit and a fifth control unit, wherein the first receiving unit is used for receiving a signal which is input by a software controller and used for closing a processor in a non-permanent closing state; the fourth control unit is used for turning off the processor in the non-permanent turning-off state according to the signal of the processor in the non-permanent turning-off state; the second receiving unit is used for receiving a signal of the processor in the opening and closing state input by the software controller after the processor in the non-permanent closing state is closed; and the fifth control unit is used for starting the processor in the closed state according to the signal of the processor in the closed state.

In this embodiment, the first receiving unit and the second receiving unit may be integrated together or may be deployed independently, and this embodiment is not limited.

In the embodiment of the invention, the devices which do not need to work permanently are closed in a hard way by the one-time programmable logic technology; frequency limiting is applied to devices that require permanent frequency limiting.

Referring to fig. 5, a schematic structural diagram of a processing system according to an embodiment of the present invention is shown in fig. 5, where the system includes: a otp controller 51, an otp array device 52, a limited frequency value memory 53, an expected value memory 54, a frequency template comparator 55, a phase-locked loop 56, at least two switching devices 57 (three switching devices are taken as an example in the present embodiment), and a plurality of processors 58, which are illustrated as CPUs 0 to CPUn. Wherein,

the otp controller 51 is configured to obtain (for example, obtain through a bus interface) otp array data that is preset to be programmed, perform format conversion on the otp array data, and output the converted otp array data to the otp array device;

that is, the otp controller can obtain the pre-programmed otp (e.g., eFuse) array data through the bus interface, and after internal processing, convert the data into the data of the otp array device interface, so as to facilitate the otp array device to write the otp array.

The otp array device 52 is configured to perform programming on the received and converted otp array data to obtain a maximum frequency parameter allowed to operate by the multiple processors and a permanent high-level signal or a permanent low-level signal, send the maximum frequency parameter allowed to operate by the multiple processors to the frequency limit value memory, and output the high-level signal or the low-level signal to the corresponding switch device;

for example, an eFuse array device, which contains a fuse that can be programmed only once, will output a permanent high or low signal after programming. It should be noted that different eFuse array devices have different capacities and therefore different output pin counts.

The frequency limiting value memory 53 is configured to store a maximum frequency parameter, which is input by the otp array device and allows the multiple processors to operate, and output the maximum frequency parameter to the frequency template comparator;

that is, the frequency limit memory latches the maximum frequency parameter that allows the processor to operate, and after a successful programming of the eFuse array, the value in the frequency limit memory is a fixed value.

The expected value memory 54 is used for acquiring (for example, acquiring through a configuration interface) and storing expected frequency parameters of a plurality of processors expected to work by a user, and outputting the expected frequency parameters to the frequency template comparator;

the value of the expected value memory cannot be modified by the user but is set by the chipman before the product is finished. When it is desired that a device, such as a processor, operates at a certain frequency (but this value is not necessarily the final operating frequency, and needs to be compared with a limit value), the phase locked loop PLL needs to be configured with the correct parameters, the desired value memory is used to latch the parameter values, and the parameter values are input through the configuration interface.

The frequency template comparator 55 is configured to determine whether the expected frequency parameter is greater than the maximum frequency parameter, and if so, output the maximum frequency parameter to the phase-locked loop; otherwise, outputting the expected frequency parameter to the phase-locked loop;

the phase-locked loop 56 is configured to generate a first clock signal corresponding to a first frequency from the maximum frequency parameter input by the frequency template comparator; outputting the first clock signal to a corresponding processor, and controlling the processor to work at a first frequency corresponding to the first clock signal; or generating a second clock signal corresponding to a second frequency from the expected frequency parameter input by the frequency template comparator, outputting the second clock signal to a corresponding processor, and controlling the processor to work at the second frequency corresponding to the second clock signal;

and the switch device 57 is configured to control a processor corresponding to the switch device to be in a permanent off state or an on state according to the high level signal or the low level signal of the otp array device for several days.

Optionally, for a processor in a non-permanent off state, the method further includes: the software controller 59 is schematically shown in fig. 5. Wherein,

the software controller 59 is configured to obtain (for example, through a control interface) and store a parameter of turning off or on of the processor in a desired non-permanent off state, and output a signal corresponding to the parameter to the switching device;

the switch device 57 is further configured to, when receiving a signal of a processor in a non-permanent off state, input by the software controller, control the processor in the non-permanent off state corresponding to the switch device to be turned off; and after the processor in the non-permanent closing state is closed, if a signal of the processor in the opening and closing state input by the software controller is received, the processor in the closing state is opened according to the signal of the processor in the opening and closing state.

As can be seen from the above technical solutions, the purpose of the embodiment of the present invention is two: 1. the method for controlling the processor to perform permanent hard frequency limiting specifically comprises the following steps: by limiting the processor's operation to a certain frequency range through one-time programmable logic (e.g., eFuses), the present invention forces the processor to operate only at the maximum of the frequency range when the operating frequency externally configured to the processor exceeds the eFuse frequency range. When the operating frequency externally configured to the processor does not exceed the frequency range of the eFuse limit, the processor will operate at the actually configured frequency; 2. the method for controlling the processor to perform permanent hard function shutdown specifically comprises the following steps: the one-time programmable logic (such as an eFuse) is used for blowing fuses, and controlling switches of internal functional units (such as a processor) of the product to achieve permanent and hard closing of the functions, and conversely, the selection of opening and closing of the internal functions (such as the processor) of the product can be performed through software configuration.

Therefore, in the embodiment of the present invention, the one-time programmable logic (e.g., eFuse) technology may be adopted to perform hard shutdown on a device (e.g., a processor) which does not need to work permanently; frequency limiting may also be performed on devices that require permanent frequency limiting, such as processors.

For ease of understanding, the following description will take core locking and frequency limiting for multi-core and high-frequency application processors as examples.

For example, the product can support up to 16 CPU processors, and the working frequency can reach up to 2 GHz. It is now necessary to permanently shut down some of the CPUs so that they do not operate, and to reduce the maximum operating frequency of all operating CPUs to 1 GHz. This allows 1GHz values to be programmed into the eFuse array using the solution described in the present invention, thereby making the output pins of the eFuse array correct. Therefore, the value of the frequency limiting value latch enables the output clock signal of the PLL to be 1GHz, and the frequency limiting effect is achieved. If a certain CPU is desired to be turned off, the corresponding selection switch outputs a control signal for turning off the CPU to the selection switch (i.e., a switch device) through the software controller because the output pin of the eFuse array is invalid, the selection switch keeps the CPU in a reset state all the time, and the CPU stops working.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be construed as the protection scope of the present invention.