CN103472748A - Verification system and method of sequential control circuit - Google Patents
- ️Wed Dec 25 2013
CN103472748A - Verification system and method of sequential control circuit - Google Patents
Verification system and method of sequential control circuit Download PDFInfo
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- CN103472748A CN103472748A CN2013103980702A CN201310398070A CN103472748A CN 103472748 A CN103472748 A CN 103472748A CN 2013103980702 A CN2013103980702 A CN 2013103980702A CN 201310398070 A CN201310398070 A CN 201310398070A CN 103472748 A CN103472748 A CN 103472748A Authority
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Abstract
The invention provides a verification system and method of a sequential control circuit. The verification system of the sequential control circuit comprises a field-programmable gate array which is used for setting up the sequential control circuit to be verified and an IIC bus controller. The IIC bus controller is connected to the sequential control circuit and is used for receiving testing instructions from an IIC bus debugging interface and analyzing the testing instructions, and reading-writing operation instructions generated by analyzing are sent to the sequential control circuit. The sequential control circuit receives and executes the reading-writing operation instructions. The verification system further comprises the IIC bus debugging interface which is connected to the IIC bus controller, and the IIC bus debugging interface receives the input testing instructions and transmits the testing instructions to the IIC bus controller. According to the sequential control circuit verification mode based on the field-programmable gate array, the IIC bus controller of hardware is achieved, soft supporting is of no need, a CPU module is of no need, and a quick and convenient debugging method is achieved.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of verification system of sequential control circuit and a kind of verification method of sequential control circuit.
Background technology
Sequential control circuit (TCON) is the important module on display device, for example, for the driving circuit on display device (source driving circuit, gate drive circuit and VCOM Polarity Control) provides timing control signal, and view data is processed to (FRC, OD etc.), thereby realize the demonstration control of analog rgb signal.Because the display panel of different manufacturers, different series is used different source driving circuits and gate drive circuit, therefore corresponding timing control signal will be variant, and the TCON chip need meet the requirement of compatible polymorphic type display panel.
Before the TCON chip is by flow, need be verified the TCON function.In the proof procedure of TCON chip, can verify by the register of each module in debugging TCON chip the compatibility of TCON.In order to regulate flexibly the register of modules, just need a kind of conveniently debud mode.Have a lot of systems to adopt the jtag interface debugging, at first this mode needs system to possess the CPU of this debugging interface of support, must have debugger and the debugging software of supporting this debugging interface in addition, and therefore many restrictions are arranged, another debud mode commonly used is by UART interface debugging register, this kind of hardware debug instrument simple (RS232-TTL card extender) that mode needs, the debugging interface of selecting is also simple, and most systems all can leave the UART interface, if but need to debug the register of all modules of TCON chip internal, the CPU that must be just the TCON chip internal works together, and operation UART drive software, at the initial stage of tcon checking, for example, while verifying separately certain module, just CPU must be added, simultaneously by CPU configuration normal operation, also to write the UART drive software, just can be debugged, this can increase workload and the difficulty of debugging undoubtedly, increase debug time.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of verification system and verification method of new sequential control circuit, can edit gate array based on scene, realize the iic bus controller of hardware, do not need software support, do not need the built-in with CPU module yet, simplified debug process.
In view of this, according to an aspect of the present invention, a kind of verification system of sequential control circuit has been proposed, comprise field programmable gate array, for building sequential control circuit to be verified, described on-the-spot logic gate array is also for building the iic bus controller, described iic bus controller is connected to described sequential control circuit, for receiving from the test instruction of iic bus debugging interface and described test instruction being resolved, by resolving the read-write operation instruction generated, be sent to described sequential control circuit; Described sequential control circuit is for receiving and carry out described read-write operation instruction; Described verification system also comprises: described iic bus debugging interface, be connected to described iic bus controller, and receive the described test instruction of input and described test instruction is transferred to described iic bus controller.
Because field programmable gate array (FPGA) is a kind of semidefinite inhibition and generation circuit, can realize combination logic function, can realize again the basic logic unit module of sequential logic function.Being stored in the value in register in logical block has determined between the logic function of this logical block and each module or the connecting mode between module and I/O, and final decision the function that realizes of FPGA, therefore, can adopt FPGA to build sequential control circuit and iic bus controller (IIC controller), like this, the sequential control circuit of building and iic bus controller just consist of hardware fully, and the iic bus controller of building does not need internal processor, do not need corresponding support software yet, at the chip checking initial stage, reach the purpose that upper computer software can the fast debugging sequential control circuit, the i2c debugging interface by host computer obtains data, do not need the CPU executive software, when debugging module changes, only need arrange and carry out slight variations at the host computer interface, do not need change debugging software, therefore reduced the complexity of debugging, with jtag interface and UART interface, compare, simple and fast more.Secondly, iic bus is a kind of simple versabus, only have two signals, implement signal, realize fairly simple, like this, just can simplify the design architecture of whole verification system, make debug process more efficient and convenient, greatly reduced the debug time of timing controller, also improved the dirigibility of debugging.
According to a further aspect in the invention, also propose a kind of verification method of sequential control circuit, used field programmable gate array to build sequential control circuit to be verified and iic bus controller; Use the iic bus debugging interface receive the test instruction of input and described test instruction is transferred to described iic bus controller; By described iic bus controller, described test instruction is resolved, generated the read-write operation instruction, for described sequential control circuit, receive and carry out.
Because field programmable gate array (FPGA) is a kind of semidefinite inhibition and generation circuit, can realize combination logic function, can realize again the basic logic unit module of sequential logic function.Being stored in the value in register in logical block has determined between the logic function of this logical block and each module or the connecting mode between module and I/O, and final decision the function that realizes of FPGA, therefore, can adopt FPGA to build sequential control circuit and iic bus controller (IIC controller), like this, the sequential control circuit of building and iic bus controller just consist of hardware fully, and the iic bus controller of building does not need internal processor, do not need corresponding support software yet, at the chip checking initial stage, reach the purpose that upper computer software can the fast debugging sequential control circuit, the i2c debugging interface by host computer obtains data, do not need the CPU executive software, when debugging module changes, only need arrange and carry out slight variations at the host computer interface, do not need change debugging software, therefore reduced the complexity of debugging, with jtag interface and UART interface, compare, simple and fast more.Secondly, iic bus is a kind of simple versabus, only have two signals, implement signal, realize fairly simple, like this, just can simplify the design architecture of whole verification system, make debug process more efficient and convenient, greatly reduced the debug time of timing controller, also improved the dirigibility of debugging.
The accompanying drawing explanation
Fig. 1 shows the schematic diagram of the verification system of sequential control circuit according to an embodiment of the invention;
Fig. 2 shows the circuit diagram that the FPGA in Fig. 1 builds;
Fig. 3 shows the process flow diagram of the verification method of sequential control circuit according to an embodiment of the invention.
Embodiment
In order more clearly to understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, in the situation that do not conflict, the application's embodiment and the feature in embodiment can combine mutually.
A lot of details have been set forth in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not subject to the restriction of following public specific embodiment.
Describe the verification system of sequential control circuit according to an embodiment of the invention in detail below in conjunction with Fig. 1 and Fig. 2.Fig. 1 shows the schematic diagram of the verification system of sequential control circuit according to an embodiment of the invention, and Fig. 2 shows the circuit diagram that the FPGA in Fig. 1 builds.
As shown in Figure 1, the verification system of sequential control circuit according to an embodiment of the invention, can comprise the two large divisions, field programmable gate array 102 and proof scheme interface (also can be described as TCON proof scheme expansion board) 104, iic
bus debugging interface1042 is arranged in proof scheme interface 104, wherein
Field programmable gate array 102, for building sequential control circuit 1024 and iic bus controller 1022(referring to Fig. 2), sequential control circuit 1024 is connected to iic bus controller 1022, for receiving the read-write operation instruction from iic bus controller 1022, and carry out this read-write operation instruction, this iic bus controller 1022, for receiving from the test instruction of iic
bus debugging interface1042 and this test instruction being resolved, is sent to sequential control circuit 1024 by resolving the read-write operation instruction generated; Iic
bus debugging interface1042, be connected to above-mentioned field programmable gate array 102, to be sent to the iic bus controller 1022 that field programmable gate array 102 is built by the test instruction of
host computer10 inputs, for example, and the execution result of the sequential control circuit 1024 that field programmable gate array 102 is built transfers to authentication unit (display screen 12), whether correct to determine the sequential control circuit 1024 that field programmable gate array 102 builds.
Due to field programmable gate array (FPGA) the 102nd, a kind of semidefinite inhibition and generation circuit, can realize combination logic function, can realize again the basic logic unit module of sequential logic function.Being stored in the value in register in logical block has determined between the logic function of this logical block and each module or the connecting mode between module and I/O, and final decision the function that realizes of FPGA, therefore, can adopt FPGA to build sequential control circuit 1024 and iic bus controller (IIC controller) 1022, like this, the sequential control circuit 1024 of building and iic bus controller 1022 just consist of hardware fully, and the iic bus controller 1022 of building does not need internal processor, do not need corresponding support software yet, therefore with jtag interface and UART interface, compare, simple and fast more.Like this, just can simplify the design architecture of whole verification system, make debug process more efficient and convenient, greatly reduce the debug time of timing controller, also improve the dirigibility of debugging.
As can be known from Fig. 1, proof scheme interface 104 can also comprise power module (being the POWER module) 1048, is used to display screen 12,104 power supplies of proof scheme interface.In addition, proof scheme interface 104 can also comprise: Low Voltage Differential Signal input interface 1044 and Low Voltage Differential Signal output interface are (for example, the Mini-LVDS output interface) 1046, be connected between iic bus controller 1022 and
display screen12, by this Low Voltage Differential Signal input interface 1044, the viewdata signal of input is transferred to sequential control circuit 1024 and process, the driving display of sequential control circuit 1024 being processed to output by this Miniature low voltage differential
signal output interface1046 transfers to display screen 12.When viewdata signal is inputed to sequential control circuit, can the value to the register in the functional module of sequential control circuit be configured by the iic bus debugging interface, thereby change the image processing method formula of sequential control circuit, for example, one two field picture is divided into to left and right half screen image and exchanges demonstration, perhaps the image of odd column and even column is changed to demonstration, like this, just can realize the integrity authentication scheme of TCON function.In other words, after tentatively putting up sequential control circuit and iic bus controller, when the driveability to sequential control circuit is debugged, but input image data signal, and by debugging interface input test instruction, after
host computer10 input test instructions (comprising the instruction that register is configured), if the display effect of display screen also falls flat, can on-the-spot adjust the sequential control circuit that FPGA builds and (adjust test instruction, register in FPGA is reconfigured), until produce a desired effect, the sequential control circuit that so just the energy fast verification is built also obtains desirable sequential control circuit.
Concrete, with reference to figure 1, in order to increase the bright degree of liquid crystal TV set display, apparent color, need to carry out gamma correction to the brightness of liquid crystal TV set display better.These, all need by the liquid crystal TV set display being carried out to the physical attribute of Gamma(display) proofreaied and correct, so proof scheme interface 104 can also comprise: gamma correction circuit 10410, for the brightness to display screen, proofreaied and correct.
With reference to figure 2, the sequential control circuit 1024 that field programmable gate array 102 is built has a plurality of functional modules, video processing module for example, random access memory controller module etc., wherein video processing module can comprise again the module of overdriving (OverDrive), scaler (Scaler), the functional modules such as Compress and decompress of the data, therefore the iic bus controller 1022 that field programmable gate array 102 is built is also for being sent to the functional module of sequential control circuit corresponding to the appointed function module's address by described read-write operation instruction, with complete in the corresponding function module corresponding to the configuration of the register of specifying register address, wherein, appointed function module's address and appointment register address are resolved described test instruction and are obtained.
Described iic bus controller 1022 is also for being sent to the read-write operation instruction functional module of described sequential control circuit corresponding to the appointed function module's address, read in described functional module the value corresponding to the register of specifying register address, and export the value of this register by the iic bus debugging interface, to obtain the work state information of described functional module.
Wherein, each functional module in the sequential control circuit 1024 that field programmable gate array 102 is built for example, is connected to iic bus controller 1022 by system bus (, APB bus).
In other words, the Tcon chip internal comprises a lot of functional modules, as " video processing module " in Fig. 2, " random access memory controller module ", " module n " etc., each module has one group of corresponding register, can realize by configuring these registers the change of functions of modules, also can read the feedback information that some status registers wherein obtain the module duty.
From above-described embodiment, can find out, the present invention adopts logical block few in FPGA to realize a kind of IIC Controller(IIC bus controller of hardware), this module can receive the IIC data stream that host computer sends by debugging acid, and parsing of the data stream is out carried out to the read-write operation to certain functional module in sequential control circuit 1024, each functional module has different address spaces, for example, during video processing module is corresponding address A1, address corresponding to random access memory controller module is A2.
It should be noted that, the IIC universal serial bus generally has two signal wires, and one is two-way data line SDA, and another root is clock line SCL.Serial data line SDA on all each equipment of receiving iic bus all receives on the SDA of bus, the clock line SCL of each equipment receives on the SCL of bus, for example in sequential control circuit 1024, the data line of each functional module all is connected to the data line in iic bus, and the clock of each functional module all is connected to the clock line SCL of the data line in iic bus.Each functional module in sequential control circuit 1024 and iic bus controller 1022 for example, by system bus, APB(Advanced Peripheral Bus) bus links together, as shown in Figure 2.The APB bus is a kind of of the AMBA bus specification released by ARM company, has become structure on a kind of popular industrial standard sheet.Iic bus controller 1022 is connected with each module in sequential control circuit 1024 by existing APB bus, also is based on the consideration of simplified design, can accelerate the debugging progress simultaneously.
When work, the test instruction that IIC Controller sends over host computer is resolved, and translates into the read-write operation that meets the APB bus timing, thereby completes the configuration to the register of each functional module in sequential control circuit 1024.Concerning
host computer10, by this iic bus controller (IIC Controller), just can regard each functional module as different Slave Device, each functional module is distributed different Device Address, functional module internal distribution Register Address.Device Address and Register Address that IIC Controller sends
host computer10 translate into the address in the APB bus address space, read-write operation are translated as to read-write in the APB bus simultaneously and control sequential.
For example, communicate by letter with the IIC Controller of FPGA inside by iic bus in host computer debugging interface, the read write command of the register that IIC Controller sends over host computer parses, find the corresponding function module in sequential control circuit according to Device Address, find the corresponding register in this corresponding function module according to Register Address, thereby corresponding registers is configured.
So-called Master Device refer to log-on data transmission (sending enabling signal), send clock signal and transmit the equipment that sends stop signal while finishing, in the present embodiment, host computer is Master Device.The equipment of being looked for by Master Device is called Slave Device.
Therefore, if only certain functional module in sequential control circuit 1024 is verified, the functional module that test instruction after resolving is sent to assigned address gets final product, if need a plurality of functional modules to be verified simultaneously, need provide the address of the plurality of functional module simultaneously.Like this, just can realize the debugging of individual feature module and the combined debugging of a plurality of functional modules, and unlike UART interface debugging mode, when verifying certain functional module separately, need internal processor, also to write the UART drive software, clearly accelerate debugging speed, and reduce the debugging complexity.
Therefore, before the flow of TCON chip, by assisting based on the FPGA platform, realize the hardware integration bus control module in FPGA inside, add verification system of the present invention, can be more truly, all sidedly the TCON function is verified, and iic bus is a kind of simple versabus, only have two signals, implement fairly simple.
Next in conjunction with Fig. 3, the verification method according to sequential control circuit of the present invention is described.
As shown in Figure 3, the verification method of sequential control circuit according to an embodiment of the invention can comprise the following steps:
step302, and use field programmable gate array to build sequential control circuit and iic bus controller;
Step304, used the iic bus debugging interface receive the test instruction of input and test instruction is transferred to the iic bus controller;
Step306, by the iic bus controller, test instruction is resolved, generate the read-write operation instruction, receive and carry out for sequential control circuit, can the execution result of sequential control circuit be transferred to authentication unit by the iic bus debugging interface, whether correct to determine the sequential control circuit that field programmable gate array builds.
Because field programmable gate array (FPGA) is a kind of semidefinite inhibition and generation circuit, can realize combination logic function, can realize again the basic logic unit module of sequential logic function.Being stored in the value in register in logical block has determined between the logic function of this logical block and each module or the connecting mode between module and I/O, and final decision the function that realizes of FPGA, therefore, can adopt FPGA to build sequential control circuit and iic bus controller (IIC controller), like this, the sequential control circuit of building and iic bus controller just consist of hardware fully, and the iic bus controller of building does not need internal processor, do not need corresponding support software yet, at the chip checking initial stage, reach the purpose that upper computer software can the fast debugging sequential control circuit, the i2c debugging interface by host computer obtains data, do not need the CPU executive software, when debugging module changes, only need arrange and carry out slight variations at the host computer interface, do not need change debugging software, therefore reduced the complexity of debugging, with jtag interface and UART interface, compare, simple and fast more.Secondly, iic bus is a kind of simple versabus, only have two signals, implement signal, realize fairly simple, like this, just can simplify the design architecture of whole verification system, make debug process more efficient and convenient, greatly reduced the debug time of timing controller, also improved the dirigibility of debugging.
After tentatively putting up sequential control circuit and iic bus controller, when the driveability to sequential control circuit is debugged, but input image data signal, and by debugging interface input test instruction, after
host computer10 input test instructions (comprising the instruction that register is configured), if the display effect of display screen also falls flat, can on-the-spot adjust the sequential control circuit that FPGA builds and (adjust test instruction, register in FPGA is reconfigured), until produce a desired effect, the sequential control circuit that so just the energy fast verification is built also obtains desirable sequential control circuit.
In above-mentioned arbitrary technical scheme, preferably, by described iic bus controller, described read-write operation instruction is sent in described sequential control circuit to the functional module corresponding to the appointed function module's address, with complete in described functional module corresponding to the configuration of the register of specifying register address, wherein, described sequential control circuit is comprised of n functional module, described n is more than or equal to 1 integer, and described appointed function module's address and described appointment register address are resolved described test instruction and obtained.Each functional module has corresponding address space, and can be convenient to locate each functional module and the register in each functional module is configured, but the independent debugging of practical function module or the combined debugging of a plurality of functional modules.
In above-mentioned arbitrary technical scheme, preferably, by described iic bus controller, described read-write operation instruction is sent in described sequential control circuit to the functional module corresponding to the appointed function module's address, to read in described functional module the value corresponding to the register of specifying register address; Export the value of described register by described iic bus debugging interface, to obtain the work state information of described functional module.
In above-mentioned arbitrary technical scheme, preferred, use system bus that a described n functional module is connected to described iic bus controller.
In above-mentioned arbitrary technical scheme, preferably, by the Low Voltage Differential Signal input interface in described proof scheme interface, the viewdata signal of input is transferred to described sequential control circuit and process, the driving display of described sequential control circuit being processed to output by the Miniature low voltage differential signal output interface in described proof scheme interface transfers to display screen.When the checking sequential control circuit, can be by viewdata signal to sequential control circuit, the display screen that outputs signal to by sequential control circuit, can judge that by the display effect of observing display screen whether the current sequential control circuit of building is correct, if incorrect, can be configured the register in the logical block of field programmable gate array by the iic bus debugging interface, thereby change function, complete the debugging to sequential control circuit.
In an embodiment according to the present invention, the iic bus controller is realized by hardware fully, do not need software support, do not need the built-in with CPU module, simplified adjustment method, simplify the design of FPGA verification system, made the combined debugging of the debugging of individual module and a plurality of modules more smooth, reduced debug time.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the verification system of a sequential control circuit, comprise field programmable gate array, for building sequential control circuit to be verified, it is characterized in that, described on-the-spot logic gate array is also for building the iic bus controller, described iic bus controller is connected to described sequential control circuit, for receiving from the test instruction of iic bus debugging interface and described test instruction being resolved, by resolving the read-write operation instruction generated, is sent to described sequential control circuit;
Described sequential control circuit is for receiving and carry out described read-write operation instruction;
Described verification system also comprises: described iic bus debugging interface, be connected to described iic bus controller, and receive the described test instruction of input and described test instruction is transferred to described iic bus controller.
2. the verification system of sequential control circuit according to claim 1, it is characterized in that, described sequential control circuit is comprised of n functional module, described iic bus controller is sent in described sequential control circuit the functional module corresponding to the appointed function module's address by described read-write operation instruction, with complete in described functional module corresponding to the configuration of the register of specifying register address, wherein, described n is more than or equal to 1 integer, and described appointed function module's address and described appointment register address are resolved described test instruction and obtained.
3. the verification system of sequential control circuit according to claim 1 and 2, it is characterized in that, described IIC controller is also for described read-write operation instruction is sent to the functional module of described sequential control circuit corresponding to the appointed function module's address, to read in described functional module the value corresponding to the register of specifying register address;
Described iic bus debugging interface is also for exporting the value of described register.
4. the verification system of sequential control circuit according to claim 2, is characterized in that, a described n functional module is connected to described iic bus controller by system bus.
5. the verification system of sequential control circuit according to claim 1, is characterized in that, also comprises:
Low Voltage Differential Signal input interface and Low Voltage Differential Signal output interface, be connected between described iic bus controller and display screen, by described Low Voltage Differential Signal input interface, the viewdata signal of input is transferred to described sequential control circuit and process, the driving display of described sequential control circuit being processed to output by described Low Voltage Differential Signal output interface transfers to described display screen.
6. the verification method of a sequential control circuit, is characterized in that, comprising:
Use field programmable gate array to build sequential control circuit to be verified and iic bus controller;
Use the iic bus debugging interface receive the test instruction of input and described test instruction is transferred to described iic bus controller;
By described iic bus controller, described test instruction is resolved, generated the read-write operation instruction, for described sequential control circuit, receive and carry out.
7. the verification method of sequential control circuit according to claim 6, it is characterized in that, by described iic bus controller, described read-write operation instruction is sent in described sequential control circuit to the functional module corresponding to the appointed function module's address, with complete in described functional module corresponding to the configuration of the register of specifying register address
Wherein, described sequential control circuit is comprised of n functional module, and described n is more than or equal to 1 integer, and described appointed function module's address and described appointment register address are resolved described test instruction and obtained.
8. according to the verification method of claim 6 or 7 described sequential control circuits, it is characterized in that, by described iic bus controller, described read-write operation instruction is sent in described sequential control circuit to the functional module corresponding to the appointed function module's address, to read in described functional module the value corresponding to the register of specifying register address;
Export the value of described register by described iic bus debugging interface.
9. the verification method of sequential control circuit according to claim 7, is characterized in that, uses system bus that a described n functional module is connected to described iic bus controller.
10. the verification method of sequential control circuit according to claim 1, it is characterized in that, when debugging, by the Low Voltage Differential Signal input interface in described proof scheme interface, the viewdata signal of input is transferred to described sequential control circuit and process, the driving display of described sequential control circuit being processed to output by the Miniature low voltage differential signal output interface in described proof scheme interface transfers to display screen.
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