CN103472878B - Reference current source - Google Patents

本发明涉及集成电路技术，具体的说是涉及一种基准电流源。本发明所述的一种基准电流源，其特征在于，包括相连接的基准电流产生电路和启动偏置电路，所述基准电流产生电路包括第一至第三PMOS管、第一至第四三极管、第六三极管、第一至第二电阻，所述启动偏置电路包括第五三极管和第三至第四电阻。本发明的有益效果为，具有结构简单、启动电压低以及易于集成的优点，同时还具有较高的精度和较低的启动电压，并降低了生产成本。本发明尤其适用于基准电流源。

The invention relates to integrated circuit technology, in particular to a reference current source. A reference current source according to the present invention is characterized in that it includes a connected reference current generating circuit and a start-up bias circuit, and the reference current generating circuit includes first to third PMOS transistors, first to fourth three pole tube, sixth triode, first to second resistors, the startup bias circuit includes fifth triode and third to fourth resistors. The beneficial effect of the invention is that it has the advantages of simple structure, low start-up voltage and easy integration, and also has higher precision and lower start-up voltage, and reduces production cost. The invention is particularly applicable to reference current sources.

一种基准电流源A reference current source

技术领域technical field

本发明涉及集成电路技术，具体的说是涉及一种基准电流源。The invention relates to integrated circuit technology, in particular to a reference current source.

背景技术Background technique

在集成电路领域中，电流基准是一类非常重要的电路。随着集成电路规模的不断扩大，对芯片的性能要求也随之提高，这对电流基准源提供的电流精度要求越来越高。传统的电流基准的做法是产生一个精准带隙基准电压源Vref，再用带隙基准电压源Vref除以电阻得到所需要的电流值。带隙基准电压源Vref的产生的原理为：具有负温系数的Vbe和具有正温系数的ΔVbe按照一定的比例消除温度系数的一阶项。然而这种做法需要一个运放保证两节点电压相等，因而增加了电路复杂度，并加大了芯片的面积和增加了成本，同时这种基准源的启动电压高。In the field of integrated circuits, current references are a very important class of circuits. With the continuous expansion of the scale of integrated circuits, the performance requirements of the chip are also increased, which requires higher and higher accuracy of the current provided by the current reference source. The traditional current reference method is to generate a precise bandgap reference voltage source Vref, and then divide the bandgap reference voltage source Vref by the resistance to obtain the required current value. The generation principle of the bandgap reference voltage source Vref is: Vbe with a negative temperature coefficient and ΔVbe with a positive temperature coefficient eliminate the first-order term of the temperature coefficient according to a certain ratio. However, this method requires an operational amplifier to ensure that the voltages of the two nodes are equal, thus increasing the complexity of the circuit, increasing the area of the chip and increasing the cost. At the same time, the starting voltage of this reference source is high.

发明内容Contents of the invention

本发明所要解决的技术问题，就是针对上述问题，提出一种基准电流源。The technical problem to be solved by the present invention is to propose a reference current source aiming at the above problems.

本发明解决上述技术问题所采用的技术方案是：一种基准电流源，其特征在于，包括相连接的基准电流产生电路和启动偏置电路，所述基准电流产生电路包括第一PMOS管M1、第二PMOS管M2、第三PMOS管M3、第一三极管Q1、第二三极管Q2、第三三极管Q3、第四三极管Q4、第六三极管Q6、第一电阻R1、第二电阻R2，所述启动偏置电路包括第五三极管Q5和第三电阻R3、第四电阻R4；The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a reference current source, which is characterized in that it includes a connected reference current generating circuit and a start-up bias circuit, and the reference current generating circuit includes a first PMOS transistor M1, The second PMOS transistor M2, the third PMOS transistor M3, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the sixth transistor Q6, the first resistor R1, a second resistor R2, the startup bias circuit includes a fifth triode Q5, a third resistor R3, and a fourth resistor R4;

第一PMOS管M1、第二PMOS管M2和第三PMOS管M3的源极、第一三极管Q1和第二三极管Q2的发射极以及第五三极管Q5的发射极均接电源VDD；The sources of the first PMOS transistor M1, the second PMOS transistor M2 and the third PMOS transistor M3, the emitters of the first triode Q1 and the second triode Q2, and the emitters of the fifth triode Q5 are all connected to the power supply VDD;

第一PMOS管M1、第二PMOS管M2和第三PMOS管M3的栅极互连，其连接点接第一PMOS管M1的漏极和第六三极管Q6的集电极的连接点；The gates of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are interconnected, and the connection point is connected to the connection point between the drain of the first PMOS transistor M1 and the collector of the sixth transistor Q6;

第二PMOS管M2的漏极与第一电阻R1的一端、第六三极管Q6的发射极和第三三极管Q3的发射极连接；The drain of the second PMOS transistor M2 is connected to one end of the first resistor R1, the emitter of the sixth transistor Q6, and the emitter of the third transistor Q3;

第三PMOS管M3的漏极为基准电流源的输出端Iref；The drain of the third PMOS transistor M3 is the output terminal Iref of the reference current source;

第一三极管Q1的集电极与第三三极管Q3的集电极和基极、第四三极管Q4的基极连接；The collector of the first transistor Q1 is connected to the collector and base of the third transistor Q3, and the base of the fourth transistor Q4;

第一三极管Q1的基极与第二三极管Q2的基极、第五三极管Q5的集电极和第三电阻R3的一端连接；The base of the first transistor Q1 is connected to the base of the second transistor Q2, the collector of the fifth transistor Q5 and one end of the third resistor R3;

第二三极管Q2的集电极与第六三极管Q6的基极、第四三极管Q4的集电极连接；The collector of the second transistor Q2 is connected to the base of the sixth transistor Q6 and the collector of the fourth transistor Q4;

第四三极管Q4的发射极与第二电阻R2的一端连接；The emitter of the fourth triode Q4 is connected to one end of the second resistor R2;

第五三极管Q5的基极连接第三电阻R3的另一端和第四电阻R4的一端；The base of the fifth triode Q5 is connected to the other end of the third resistor R3 and one end of the fourth resistor R4;

第一电阻R1的另一端、第二电阻R2的另一端和第四电阻R4的另一端均接地。The other end of the first resistor R1, the other end of the second resistor R2 and the other end of the fourth resistor R4 are all grounded.

具体的，所述第三三极管Q3和第四三极管Q4的发射极面积之比为8:1。Specifically, the ratio of the emitter areas of the third transistor Q3 and the fourth transistor Q4 is 8:1.

本发明的有益效果为，具有结构简单、启动电压低以及易于集成的优点，同时还具有较高的精度和较低的启动电压，并降低了生产成本。The beneficial effect of the invention is that it has the advantages of simple structure, low start-up voltage and easy integration, and also has higher precision and lower start-up voltage, and reduces production cost.

附图说明Description of drawings

图1是本发明的基准电流源电路结构示意图；Fig. 1 is a schematic structural diagram of a reference current source circuit of the present invention;

图2是本发明的基准电流源工作原理示意图。FIG. 2 is a schematic diagram of the working principle of the reference current source of the present invention.

具体实施方式Detailed ways

下面结合附图，详细描述本发明的技术方案：Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

本发明所述的基准电流源，其特征在于，包括相连接的基准电流产生电路和启动偏置电路，所述基准电流产生电路包括第一PMOS管M1、第二PMOS管M2、第三PMOS管M3、第一三极管Q1、第二三极管Q2、第三三极管Q3、第四三极管Q4、第六三极管Q6、第一电阻R1、第二电阻R2，所述启动偏置电路包括第五三极管Q5和第三电阻R3、第四电阻R4；The reference current source of the present invention is characterized in that it includes a connected reference current generating circuit and a start-up bias circuit, and the reference current generating circuit includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the sixth transistor Q6, the first resistor R1, the second resistor R2, the starting The bias circuit includes a fifth transistor Q5, a third resistor R3, and a fourth resistor R4;

第一PMOS管M1、第二PMOS管M2和第三PMOS管M3的源极、第一三极管Q1和第二三极管Q2的发射极以及第五三极管Q5的发射极均接电源VDD；The sources of the first PMOS transistor M1, the second PMOS transistor M2 and the third PMOS transistor M3, the emitters of the first triode Q1 and the second triode Q2, and the emitters of the fifth triode Q5 are all connected to the power supply VDD;

第一PMOS管M1、第二PMOS管M2和第三PMOS管M3的栅极互连，其连接点接第一PMOS管M1的漏极和第六三极管Q6的集电极的连接点；The gates of the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are interconnected, and the connection point is connected to the connection point between the drain of the first PMOS transistor M1 and the collector of the sixth transistor Q6;

第二PMOS管M2的漏极与第一电阻R1的一端、第六三极管Q6的发射极和第三三极管Q3的发射极连接；The drain of the second PMOS transistor M2 is connected to one end of the first resistor R1, the emitter of the sixth transistor Q6, and the emitter of the third transistor Q3;

第三PMOS管M3的漏极为基准电流源的输出端Iref；The drain of the third PMOS transistor M3 is the output terminal Iref of the reference current source;

第一三极管Q1的集电极与第三三极管Q3的集电极和基极、第四三极管Q4的基极连接；The collector of the first transistor Q1 is connected to the collector and base of the third transistor Q3, and the base of the fourth transistor Q4;

第一三极管Q1的基极与第二三极管Q2的基极、第五三极管Q5的集电极和第三电阻R3的一端连接；The base of the first transistor Q1 is connected to the base of the second transistor Q2, the collector of the fifth transistor Q5 and one end of the third resistor R3;

第二三极管Q2的集电极与第六三极管Q6的基极、第四三极管Q4的集电极连接；The collector of the second transistor Q2 is connected to the base of the sixth transistor Q6 and the collector of the fourth transistor Q4;

第四三极管Q4的发射极与第二电阻R2的一端连接；The emitter of the fourth triode Q4 is connected to one end of the second resistor R2;

第五三极管Q5的基极连接第三电阻R3的另一端和第四电阻R4的一端；The base of the fifth triode Q5 is connected to the other end of the third resistor R3 and one end of the fourth resistor R4;

第一电阻R1的另一端、第二电阻R2的另一端和第四电阻R4的另一端均接地。The other end of the first resistor R1, the other end of the second resistor R2 and the other end of the fourth resistor R4 are all grounded.

为了方便叙述，第一至第三PMOS管分别依次用M1、M2、M3代替，第一至第六三极管分别依次用Q1、Q2、Q3、Q4、Q5、Q6代替，第一至第四电阻分别依次用R1、R2、R3、R4代替，如图1所示，For the convenience of description, the first to third PMOS transistors are respectively replaced by M1, M2 and M3 in sequence, and the first to sixth triodes are respectively replaced by Q1, Q2, Q3, Q4, Q5 and Q6 in sequence. The resistors are replaced by R1, R2, R3, and R4 in turn, as shown in Figure 1.

本发明的基准电流源包括启动偏置电路和基准电流产生电路，电源电压VDD、接地端GND、基准电流输出端Iref；其中，The reference current source of the present invention includes a starting bias circuit and a reference current generating circuit, a power supply voltage VDD, a ground terminal GND, and a reference current output terminal Iref; wherein,

基准电流产生电路：M1、M2、M3的源极与电源电压VDD连接，M1、M2、M3三管的栅极连接在一起并且M1为二极管连接方式，M3的漏极为基准电流的输出I_ref，M2的漏极、R1、Q6的发射极、Q3的发射极连接，M1的漏极与Q6的集电极连接，Q1、Q2的发射极与电源电压VDD连接，Q1、Q2的基极连接且与启动偏置电压电路中的Q5的集电极连接，Q1的集电极与二极管连接方式的Q3集电极连接，Q3、Q4的基极连接在一起，Q4的集电极、Q6的基极、Q2的集电极连接，Q4的发射极与电阻R2连接，R1、R2的另外一端与地连接。Reference current generation circuit: the sources of M1, M2, and M3 are connected to the power supply voltage VDD, the gates of M1, M2, and M3 are connected together and M1 is a diode connection, and the drain of M3 is the output I _ref of the reference current. The drain of M2, the emitter of R1, Q6, and the emitter of Q3 are connected, the drain of M1 is connected to the collector of Q6, the emitters of Q1 and Q2 are connected to the power supply voltage VDD, the bases of Q1 and Q2 are connected and connected to The collector of Q5 in the startup bias voltage circuit is connected, the collector of Q1 is connected to the collector of Q3 in diode connection, the bases of Q3 and Q4 are connected together, the collector of Q4, the base of Q6, and the collector of Q2 The electrodes are connected, the emitter of Q4 is connected to the resistor R2, and the other end of R1 and R2 is connected to the ground.

启动偏置电路：Q5的发射极与电源电压VDD连接，Q5的集电极、R3、基准电流产生电路中的Q1、Q2的基极连接，Q5的基极与R3、R4连接，R4的另外一端与地连接。Start-up bias circuit: the emitter of Q5 is connected to the power supply voltage VDD, the collector of Q5, R3, and the base of Q1 and Q2 in the reference current generation circuit are connected, the base of Q5 is connected to R3 and R4, and the other end of R4 Connect to ground.

本发明的工作原理为：Working principle of the present invention is:

如图2所示，当VDD有一个很低的电压时启动偏置电路工作Q5导通，在B点产生一个电压引起Q1、Q2、Q3、Q4导通，从而整个基准电流产生电路正常工作。R3，R4是为了限制电流的作用。当电路正常工作后，Q1、Q2的基极电压相等，故I_c1＝I_c2。由电路电气特性可得：I_c2＝I_c4+I_b6，I_c1＝I_c3+I_b，根据I_c1＝I_c2可得I_c4+I_b6＝I_c3+I_b，I_b为二倍的基极电流，由于I_c＝βI_b而β很大，故I_c3≈I_c4，Q6的作用就是减小了I_c3与I_c4的误差。As shown in Figure 2, when VDD has a very low voltage, the bias circuit starts to work and Q5 is turned on, and a voltage is generated at point B to cause Q1, Q2, Q3, and Q4 to be turned on, so that the entire reference current generating circuit works normally. R3 and R4 are used to limit the current. When the circuit works normally, the base voltages of Q1 and Q2 are equal, so I _c1 =I _c2 . _It can be obtained from the electrical characteristics of the circuit: I _c2 = I _c4 + I _b6 , I _c1 = I _c3 + I _b , according to I c1 = I c2, I _c4 + _{I b6} = I _c3 + I _b , and I _b is twice base current, because I _c = βI _b and β is very large, so I _c3 ≈ I _c4 , the function of Q6 is to reduce the error between I _c3 and I _c4 .

Q3与Q4的发射极面积之比为8：1关系，则有：The ratio of the emitter area of Q3 to Q4 is 8:1, then:

II 11 == VV aa -- VV bebe 33 RR 11 ;;

II 22 == VV aa -- VV bebe 44 RR 22 ;;

当R1与R2相等且为温度系数为正温系数时：When R1 and R2 are equal and the temperature coefficient is When the temperature coefficient is positive:

II 11 -- II 22 == VV bebe 44 -- VV bebe 33 RR 11 == ΔΔ VV bebe RR 11 ;;

由于I_c3≈I_c4,故：Since I _c3 ≈ I _c4 , so:

II 11 -- II 22 == II 33 ++ II 44 == ΔΔ VV bebe RR 11 ;;

假设M3的W/L为M2、M3的W/L的两倍，M2、M3是镜像的M1，则：Assuming that the W/L of M3 is twice the W/L of M2 and M3, and M2 and M3 are mirror images of M1, then:

II refref == ΔΔ VV bebe RR 11 ,,

并由：and by:

II cc == II sthe s expexp (( qq VV bebe kTkT )) ,,

可得：Available:

VV bebe == kTkT qq lnln (( II CC II SS )) ;;

其中I_S为BJT反向饱和电流，则有：Where I _S is the BJT reverse saturation current, then:

ΔΔ VV bebe == VV bebe 44 -- VV bebe 33 == kTkT qq lnln (( II CC 44 II SS )) -- kTkT qq lnln (( 88 II CC 44 II SS )) == -- kTkT qq lnln 88 ..

综上所述采用R1、R2具有合适的正温系数工艺，使基准电流源I_ref具有很好的精度，是一种结构简单、启动电压低的非常实用的基准电流源电路。In summary Adopting R1 and R2 with suitable positive temperature coefficient technology makes the reference current source I _ref have good precision, and it is a very practical reference current source circuit with simple structure and low starting voltage.