CN103472882B - Low dropout regulator of integrated slew rate enhancement circuit - Google Patents

The invention relates to the field of power management technology. The invention discloses a low dropout regulator of an integrated slew rate enhancement circuit. The technical scheme of the invention comprises a slew rate enhancement circuit, an operational amplifier, a compensating pipe, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor. According to the low dropout regulator of the integrated slew rate enhancement circuit, due to the adoption of the slew rate enhancement circuit, when output voltage rushes up or down, the slew rate enhancement circuit can output driving current which is not restricted by a bias current source and quickly adjusts the grid changes of the compensating pipe, so as to compensate the changes of the load current, greatly solve the problem that the slew rate and bandwidth of an error amplifier are restricted in a low power consumption mode, and reduce the peak of the output voltage. An on-chip integration technology is adopted, no high off-chip load capacitance is needed, and the system cost is reduced.

集成摆率增强电路的低压差线性稳压器Low Dropout Linear Regulator with Integrated Slew Rate Enhancement Circuit

技术领域technical field

本发明涉及电源管理技术，特别涉及一种可应用于SOC(System on Chip)芯片中的无输出电容型低压差线性稳压器(Low Dropout Regulator，LDO)的设计。The invention relates to power management technology, in particular to the design of a non-output capacitor type low dropout linear regulator (Low Dropout Regulator, LDO) applicable to SOC (System on Chip) chips.

背景技术Background technique

随着SOC技术的发展，要求越来越多的功能模块集成于同一IC里边以提高其系统集成度。其中，LDO以其电路简单且占用面积小的优点成为了SOC系统中重要的不可或缺的供电模块。With the development of SOC technology, more and more functional modules are required to be integrated in the same IC to improve its system integration. Among them, the LDO has become an important and indispensable power supply module in the SOC system due to its advantages of simple circuit and small footprint.

为了减小片外元件数和引脚数，因此无片外大电容LDO有很大发展空间。传统的LDO架构如图1所示，图中，电阻RA和电阻RB构成输出电压VOUT的采样电路，电阻ROUT为负载电阻，电容COUT为滤波电容。运算放大器OTA根据参考电压VREF和反馈电压VFB的大小，输出驱动电压控制调整管MP1的开启和关断，实现输出电压VOUT的调整。由于误差放大器OTA在低功耗模式下摆率和带宽受限，无片外大电容LDO与传统的LDO相比存在着较大缺陷，面临着轻载稳定性变差和瞬态响应变差的双重压力。In order to reduce the number of off-chip components and pins, there is a lot of room for development of LDOs without off-chip large capacitors. The traditional LDO architecture is shown in Figure 1. In the figure, the resistor RA and the resistor RB constitute the sampling circuit of the output voltage VOUT, the resistor ROUT is the load resistor, and the capacitor COUT is the filter capacitor. According to the reference voltage VREF and the feedback voltage VFB, the operational amplifier OTA outputs a drive voltage to control the turn-on and turn-off of the adjustment transistor MP1 to realize the adjustment of the output voltage VOUT. Due to the limited slew rate and bandwidth of the error amplifier OTA in low power consumption mode, LDO without off-chip large capacitance has larger defects compared with traditional LDO, facing the dual problems of poor light load stability and poor transient response pressure.

发明内容Contents of the invention

本发明的目的是为了解决现有的无片外大电容低压差线性稳压器存在的瞬态响应问题，提出了一种可应用于SOC中的无输出大电容型LDO，兼顾瞬态响应、输出电压精度、小芯片面积和低功耗。The purpose of the present invention is to solve the transient response problem existing in the existing non-chip large capacitor low dropout linear regulator, and propose a non-output large capacitor type LDO that can be applied to SOC, taking into account the transient response, Output voltage accuracy, small die area, and low power consumption.

本发明解决所述技术问题，采用的技术方案是，集成摆率增强电路的低压差线性稳压器，其特征在于，包括摆率增强电路、运算放大器、调整管、第一电阻、第二电阻、第三电阻、第四电阻、第一电容；其中，运算放大器的反向输入端连接第二基准电压，同相输入端连接第二电阻的一端和第三电阻的一端，输出端连接调整管的控制极和摆率增强电路的输出端以及第一电容的一端；调整管的输入端连接电源电压，调整管的输出端与第一电阻的一端和第四电阻的一端相连作为所述低压差线性稳压器的输出端并连接摆率增强电路的第一输入端，第四电阻的另一端连接第一电容的另一端；第一电阻的另一端与第二电阻的另一端相连并连接摆率增强电路的第二输入端；摆率增强电路的第三输入端连接第一基准电压；第三电阻的另一端连接地电位。The present invention solves the above-mentioned technical problem, and adopts the technical solution as a low-dropout linear regulator integrating a slew rate enhancement circuit, which is characterized in that it includes a slew rate enhancement circuit, an operational amplifier, an adjustment tube, a first resistor, and a second resistor , the third resistor, the fourth resistor, and the first capacitor; wherein, the inverting input terminal of the operational amplifier is connected to the second reference voltage, the non-inverting input terminal is connected to one end of the second resistor and one end of the third resistor, and the output terminal is connected to the adjusting tube The output end of the control pole and the slew rate enhancement circuit and one end of the first capacitor; the input end of the adjustment tube is connected to the power supply voltage, and the output end of the adjustment tube is connected to one end of the first resistor and one end of the fourth resistor as the low dropout linear The output end of the voltage regulator is connected to the first input end of the slew rate enhancement circuit, the other end of the fourth resistor is connected to the other end of the first capacitor; the other end of the first resistor is connected to the other end of the second resistor and connected to the slew rate The second input end of the enhancement circuit; the third input end of the slew rate enhancement circuit is connected to the first reference voltage; the other end of the third resistor is connected to the ground potential.

进一步的，所述摆率增强电路包括，PMOS管：M1、M4、M6、M7、M8、M14、M15、M16、M17和NMOS管：M2、M3、M5、M9、M10、M11、M12、M13、M18及电阻R21和电容C21，其中PMOS管M1、M6和M16的栅极均连接第一偏置电压Vb1，源极连接电源电压，M4、M17源极连接电源电压，M1漏极分别连接M2的栅极和漏极，M16的漏极连接到M14和M15的源极；M14的栅极为摆率增强电路的第三输入端，漏极分别连接M11和M12的栅极和M11的漏极；M15的栅极为摆率增强电路的第二输入端，M15的漏极分别连接M12和M13的漏极和M13和M18的栅极；M18的漏极连接到M17、M4的栅极和M17的漏极；M7、M8的栅极均连接到M7的漏极，源极均连接电源电压，M7的漏极连接到M5和M6的漏极，M8的漏极连接M10的漏极作为摆率增强电路的输出端；NMOS管M2、M3、M5、M11、M12、M13、M18的源极均连接地，M2的漏极连接M1漏极和M2的栅极及R21的一端，电阻R21的另一端连接NMOS管M3的栅极和NMOS管M5的栅极，M3、M5的漏极分别连接M4、M6的漏极，M2的栅极连接M2和M1的漏极；NMOS管M9、M10的源极均接地，M9的漏极和M9及M10的栅极相连又连接到M3和M4的漏极；电容C21的一端连接M3的栅极，另一端作为摆率增强电路的第一输入端。Further, the slew rate enhancement circuit includes, PMOS transistors: M1, M4, M6, M7, M8, M14, M15, M16, M17 and NMOS transistors: M2, M3, M5, M9, M10, M11, M12, M13 , M18, resistor R21 and capacitor C21, wherein the gates of PMOS transistors M1, M6 and M16 are all connected to the first bias voltage Vb1, the source is connected to the power supply voltage, the source of M4 and M17 is connected to the power supply voltage, and the drain of M1 is respectively connected to M2 The gate and drain of M16 are connected to the sources of M14 and M15; the gate of M14 is the third input terminal of the slew rate enhancement circuit, and the drain is respectively connected to the gates of M11 and M12 and the drain of M11; The gate of M15 is the second input terminal of the slew rate enhancement circuit, and the drain of M15 is respectively connected to the drains of M12 and M13 and the gates of M13 and M18; the drain of M18 is connected to the gates of M17, M4 and the drain of M17 The gates of M7 and M8 are connected to the drain of M7, the source is connected to the power supply voltage, the drain of M7 is connected to the drains of M5 and M6, and the drain of M8 is connected to the drain of M10 as a slew rate enhancement circuit The output terminals of the NMOS transistors M2, M3, M5, M11, M12, M13, and M18 are all connected to the ground, the drain of M2 is connected to the drain of M1, the gate of M2 and one end of R21, and the other end of the resistor R21 is connected to The gate of NMOS transistor M3 and the gate of NMOS transistor M5, the drains of M3 and M5 are respectively connected to the drains of M4 and M6, the gate of M2 is connected to the drains of M2 and M1; the sources of NMOS transistors M9 and M10 are connected Grounded, the drain of M9 is connected to the gates of M9 and M10 and then connected to the drains of M3 and M4; one end of the capacitor C21 is connected to the gate of M3, and the other end is used as the first input end of the slew rate enhancement circuit.

优选的，所述调整管为PMOS管，所述调整管控制极为PMOS管的栅极，所述调整管输入端为PMOS管的源极，所述调整管输出端为PMOS管的漏极。Preferably, the adjustment transistor is a PMOS transistor, the control pole of the adjustment transistor is the gate of the PMOS transistor, the input end of the adjustment transistor is the source of the PMOS transistor, and the output end of the adjustment transistor is the drain of the PMOS transistor.

本发明的有益效果是，由于采用本发明所提出的摆率增强电路，在输出电压发生上冲或下冲时，摆率增强电路都能够输出不受限于偏置电流源大小的驱动电流，快速调整调整管的栅极变化，以补偿负载电流的变化，极大的克服了误差放大器在低功耗模式下摆率和带宽受限的问题，减小了输出电压尖峰。同时，本发明采用片上集成技术，不再需要大的片外负载电容，减小了系统成本。The beneficial effect of the present invention is that, due to the adoption of the slew rate enhancement circuit proposed by the present invention, when the output voltage overshoots or undershoots, the slew rate enhancement circuit can output a driving current that is not limited to the size of the bias current source, Quickly adjust the gate change of the pass transistor to compensate for changes in the load current, which greatly overcomes the problem of limited slew rate and bandwidth of the error amplifier in low power consumption mode, and reduces the output voltage spike. At the same time, the present invention adopts the on-chip integration technology, which no longer needs a large off-chip load capacitance and reduces the system cost.

附图说明Description of drawings

图1现有的LDO电路的拓扑结构图；The topological structure diagram of the existing LDO circuit of Fig. 1;

图2本发明的低压差线性稳压器电路拓扑结构图；Fig. 2 low-dropout linear regulator circuit topology diagram of the present invention;

图3本发明的摆率增强电路的电路图；The circuit diagram of the slew rate enhancing circuit of Fig. 3 of the present invention;

图4本发明低压差线性稳压器轻载跳重载时频率响应波特图；Fig. 4 frequency response Bode diagram when the low-dropout linear regulator of the present invention jumps from light load to heavy load;

图5本发明低压差线性稳压器重载跳轻载时频率响应波特图；Figure 5 is a Bode diagram of the frequency response when the low-dropout linear voltage regulator of the present invention is heavy-loaded and light-loaded;

图6本发明低压差线性稳压器不同负载条件下的瞬态仿真结果。Fig. 6 is the transient simulation results of the low dropout linear regulator of the present invention under different load conditions.

具体实施方式Detailed ways

下面结合附图及具体实施方式，详细描述本发明的技术方案。The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

本发明低压差线性稳压器如图2所示，包括：摆率增强电路SRE、运算放大器OTA、调整管M0、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第一电容C1。其中，运算放大器的反向输入端连接第二基准电压VREF2，输出端连接调整管M0的栅极和摆率增强电路的输出端。调整管M0的源极连接电源电压VDD，调整管M0的漏极作为低压差线性稳压器的输出端VOUT。摆率增强电路的第一输入端in1连接低压差线性稳压器的输出端VOUT，摆率增强电路的第二输入端in2连接到第一电阻R1及第二电阻R2的公共端VFB1，摆率增强电路的第三输入端in3连接第一基准电压VREF1。第一电阻R1的另一端连接低压差线性稳压器的输出端VOUT，第二电阻R2的另一端连接运算放大器的同相输入端。第二电阻R2一端连接运算放大器的同向输入端VFB和第三电阻R3的一端，第三电阻R3的另一端连接地。第一电容C1的一端连接运算放大器的输出端，另一端连接第四电阻R4的一端，第四电阻R4的另一端连接至低压差线性稳压器的输出端VOUT。图2中电阻RL为负载电阻。The low dropout linear voltage regulator of the present invention is shown in Figure 2, comprising: a slew rate enhancement circuit SRE, an operational amplifier OTA, an adjustment tube M0, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, The first capacitor C1. Wherein, the inverting input terminal of the operational amplifier is connected to the second reference voltage VREF2, and the output terminal is connected to the gate of the adjustment transistor M0 and the output terminal of the slew rate enhancement circuit. The source of the adjustment transistor M0 is connected to the power supply voltage VDD, and the drain of the adjustment transistor M0 is used as the output terminal VOUT of the low dropout linear regulator. The first input terminal in1 of the slew rate enhancement circuit is connected to the output terminal VOUT of the low dropout linear regulator, the second input terminal in2 of the slew rate enhancement circuit is connected to the common terminal VFB1 of the first resistor R1 and the second resistor R2, and the slew rate The third input terminal in3 of the enhancement circuit is connected to the first reference voltage VREF1. The other end of the first resistor R1 is connected to the output terminal VOUT of the low dropout linear regulator, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the operational amplifier. One end of the second resistor R2 is connected to the non-inverting input terminal VFB of the operational amplifier and one end of the third resistor R3, and the other end of the third resistor R3 is connected to the ground. One end of the first capacitor C1 is connected to the output end of the operational amplifier, the other end is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the output end VOUT of the low dropout linear regulator. Resistance RL in Fig. 2 is load resistance.

本发明的摆率增强电路如图3所示，包括，PMOS管：M1、M4、M6、M7、M8、M14、M15、M16、M17和NMOS管：M2、M3、M5、M9、M10、M11、M12、M13、M18及电阻R21和电容C21。其中PMOS管M1、M6和M16的栅极均连接偏置电压Vb1，源极连接电源电压VDD，M4、M17源极连接电源电压。M1、M6漏极分别连接M2、M5的漏极，M16的漏极连接到M14和M15的源极。PMOS管M14的栅极连接摆率增强电路的第三输入端in3(第一参考电压VREF1)，漏极分别连接M11和M12的栅极和M11的漏极。PMOS管M15的栅极连接摆率增强电路的第二输入端in2(VFB1端)，漏极分别连接M12和M13的漏极和M13和M18的栅极。PMOS管M18的漏极连接到PMOS管M17和PMOS管M4的栅极和M17的漏极。PMOS管M7、M8的栅极均连接到M7的漏极，源极均连接电源电压VDD，M7的漏极连接到M5和M6的漏极，M8的漏极连接M10的漏极作为摆率增强电路的输出端VG。NMOS管M2、M3、M5、M11、M12、M13、M18的源极均连接地，M2的漏极连接M1漏极和M2的栅极及R21的一端，电阻R21的另一端连接NMOS管M3的栅极和NMOS管M5的栅极，M3、M5的漏极分别连接M4、M6的漏极，M2的栅极连接M2和M1的漏极。NMOS管M9、M10的源极均接地，M9的漏极和M9及M10的栅极相连又连接到M3和M4的漏极。电容C1的一端连接NMOS管M3的栅极，另一端作为摆率增强电路的输入端VFB。The slew rate enhancement circuit of the present invention is shown in Figure 3, including PMOS tubes: M1, M4, M6, M7, M8, M14, M15, M16, M17 and NMOS tubes: M2, M3, M5, M9, M10, M11 , M12, M13, M18, resistor R21 and capacitor C21. The gates of the PMOS transistors M1 , M6 and M16 are all connected to the bias voltage Vb1 , the sources are connected to the power supply voltage VDD, and the sources of M4 and M17 are connected to the power supply voltage. The drains of M1 and M6 are respectively connected to the drains of M2 and M5, and the drain of M16 is connected to the sources of M14 and M15. The gate of the PMOS transistor M14 is connected to the third input terminal in3 (the first reference voltage VREF1 ) of the slew rate enhancement circuit, and the drain is connected to the gates of M11 and M12 and the drain of M11 respectively. The gate of the PMOS transistor M15 is connected to the second input terminal in2 (VFB1 terminal) of the slew rate enhancement circuit, and the drains are respectively connected to the drains of M12 and M13 and the gates of M13 and M18. The drain of the PMOS transistor M18 is connected to the gates of the PMOS transistor M17 and the PMOS transistor M4 and the drain of the M17. The gates of PMOS transistors M7 and M8 are connected to the drain of M7, the source is connected to the power supply voltage VDD, the drain of M7 is connected to the drains of M5 and M6, and the drain of M8 is connected to the drain of M10 as a slew rate enhancement The output terminal VG of the circuit. The sources of the NMOS transistors M2, M3, M5, M11, M12, M13, and M18 are all connected to the ground, the drain of M2 is connected to the drain of M1, the gate of M2 and one end of R21, and the other end of the resistor R21 is connected to the NMOS transistor M3. The gate and the gate of the NMOS transistor M5, the drains of M3 and M5 are respectively connected to the drains of M4 and M6, and the gate of M2 is connected to the drains of M2 and M1. The sources of the NMOS transistors M9 and M10 are both grounded, and the drain of M9 is connected to the gates of M9 and M10 and then connected to the drains of M3 and M4. One end of the capacitor C1 is connected to the gate of the NMOS transistor M3, and the other end is used as the input end VFB of the slew rate enhancement circuit.

这里，M11、M12、M13、M14、M15和M16构成跨导放大器，M3、M4组成第一电流减法器，M5、M6组成第二电流减法器，M7、M8组成上冲电流镜模块，M9、M10组成下冲电流镜模块。Here, M11, M12, M13, M14, M15, and M16 form a transconductance amplifier, M3, M4 form a first current subtractor, M5, M6 form a second current subtractor, M7, M8 form an overshoot current mirror module, M9, M10 forms an undershoot current mirror module.

摆率增强电路的作用是在负载电流变化时，能够快速的改变调整管的栅极电压，从而在极短的时间内调整输出电压稳定到确定值。为便于分析，假设M1的漏极电流为I，M11、M12和M13的宽长比比例为(m+1)：m:1。在稳定情况下，在跨导放大器中，M16的电流为2I，M11的电流为I，M12的电流为M13的电流为设计时第一电流减法器中M3的镜像电流要大于M4的电流，则此时M3管工作在线性区，该电流减法器输出为低电平，所以晶体管M9、M10均不工作；同理，第二电流减法器中M6工作在线性区，晶体管M7、M8也不工作。所以在稳定状态下摆率增强电路对LDO静态工作状态和环路稳定性不产生影响。The function of the slew rate enhancement circuit is to quickly change the gate voltage of the regulator tube when the load current changes, so as to adjust the output voltage to a stable value in a very short time. For the convenience of analysis, it is assumed that the drain current of M1 is I, and the aspect ratio ratio of M11, M12 and M13 is (m+1):m:1. In the steady state, in the transconductance amplifier, the current of M16 is 2I, the current of M11 is I, and the current of M12 is The current of M13 is When designing, the mirror current of M3 in the first current subtractor is greater than the current of M4, then the M3 tube works in the linear region at this time, and the output of the current subtractor is low level, so transistors M9 and M10 do not work; similarly, M6 in the second current subtractor works in the linear region, and transistors M7 and M8 do not work either. Therefore, the slew rate enhancement circuit has no influence on the static working state of the LDO and the loop stability in a steady state.

当输出负载电流突然变小时，输出电压会有较大的向上脉冲，该脉冲电压高于电容C21和电阻R21形成的高通滤波器的截止频率时开始耦合到晶体管M3、M5的栅极，从而使得M3、M5的漏极获得很大的电流，同时该脉冲电压通过跨导放大器作用减小M4的动态电流；对于M3、M4组成的电流减法器，M3将继续工作在线性区，输出仍为低电平，则M9、M10仍然不工作，而对于M5、M6组成的电流减法器，由于M5的漏极电流的突然增大，使M7、M8有电流输出，为调整管M0栅极充电，从而M0的栅极电压迅速的增大，减小了调整管输出电流的大小。当输出负载电流突然变大时，输出电压会有一个很高的向下脉冲，该脉冲电压通过电容C21耦合到晶体管M3、M5的栅极，从而使得M3、M5的漏极电流变小。对于M5、M6组成的电流减法器，M6将继续工作在线性区，输出仍为高电平，则M7、M8则不能工作；对于M3、M4组成的电流减法器，该脉冲电压通过跨导放大器作用使得M13的输出电流迅速上升，则M4电流变的很大；对于M3、M4组成的电流减法器，由于M4漏极电流的突然增大，M3电流的突然减小，使得M9和M10迅速的产生电流，为调整管M0的栅极放电，从而迅速拉低M0栅极电压，最终使得LDO的输出电压迅速调整至确定值。When the output load current suddenly becomes smaller, the output voltage will have a larger upward pulse, and when the pulse voltage is higher than the cut-off frequency of the high-pass filter formed by the capacitor C21 and the resistor R21, it will start to couple to the gates of the transistors M3 and M5, thus making The drains of M3 and M5 obtain a large current, and at the same time, the pulse voltage reduces the dynamic current of M4 through the action of the transconductance amplifier; for the current subtractor composed of M3 and M4, M3 will continue to work in the linear region, and the output is still low level, M9 and M10 still do not work, and for the current subtractor composed of M5 and M6, due to the sudden increase of the drain current of M5, M7 and M8 have current output to charge the gate of the adjustment tube M0, thereby The grid voltage of M0 increases rapidly, which reduces the size of the output current of the adjustment tube. When the output load current suddenly increases, the output voltage will have a very high downward pulse, and the pulse voltage is coupled to the gates of transistors M3 and M5 through the capacitor C21, so that the drain currents of M3 and M5 become smaller. For the current subtractor composed of M5 and M6, M6 will continue to work in the linear region, and the output is still high, then M7 and M8 cannot work; for the current subtractor composed of M3 and M4, the pulse voltage passes through the transconductance amplifier The effect makes the output current of M13 rise rapidly, and the current of M4 becomes very large; for the current subtractor composed of M3 and M4, due to the sudden increase of the drain current of M4 and the sudden decrease of the current of M3, M9 and M10 rapidly decrease. A current is generated to discharge the gate of the adjustment transistor M0, thereby rapidly pulling down the gate voltage of M0, and finally the output voltage of the LDO is quickly adjusted to a certain value.

可以看到在上述摆率增强电路中，上冲发生时，通过R21C21D的耦合作用，使M5产生大的电流为调整管的栅极充电，并且该电流是随上冲电压增大而增大的，因此摆率增强电路栅极充电电流不受限；下冲发生时，VFB1电压会降低，此时M13的电流会迅速增大，由于M12的存在，M13电流最大可以变为原来的m+1倍，从而极大的增大了M4的电流，因此该摆率增强电路下冲放电电流也基本不受限制。因此该摆率增强电路极大的优化了上冲和下冲效果。另外，为了使跨导放大器输入端最大程度的提取输出电压的变化量，因此在选取参考电压时，未选用和EA相同的基准电压，而是选择保证跨导放大器的共模输入范围的最大电压。It can be seen that in the above-mentioned slew rate enhancement circuit, when the overshoot occurs, M5 generates a large current to charge the gate of the adjustment tube through the coupling effect of R21C21D, and the current increases with the increase of the overshoot voltage. , so the gate charging current of the slew rate enhancement circuit is not limited; when the undershoot occurs, the voltage of VFB1 will decrease, and the current of M13 will increase rapidly at this time. Due to the existence of M12, the maximum current of M13 can be changed to the original m+1 times, thereby greatly increasing the current of M4, so the undershoot discharge current of the slew rate enhancement circuit is basically unlimited. Therefore, the slew rate enhancement circuit greatly optimizes the overshoot and undershoot effects. In addition, in order to make the input terminal of the transconductance amplifier extract the variation of the output voltage to the greatest extent, when selecting the reference voltage, the reference voltage that is the same as EA is not selected, but the maximum voltage that guarantees the common-mode input range of the transconductance amplifier is selected. .

针对于摆率增强电路，在输出电压发生跳变时，RC高通滤波器仅在高频时有作用；而跨导放大器在低频和高频时均会有作用，且在R21C21高通滤波器或者跨导放大器有作用时，LDO环路跨导增大，因此对于电路稳定性的分析是必不可少的。对于无片外电容的LDO，其主极点位置在调整管栅极，次极点位置位于LDO输出端，主极点和次极点分别为For the slew rate enhancement circuit, when the output voltage jumps, the RC high-pass filter only works at high frequencies; while the transconductance amplifier works at both low and high frequencies, and the R21C21 high-pass filter or transconductance When the conductance amplifier works, the transconductance of the LDO loop increases, so it is essential to analyze the stability of the circuit. For an LDO without an off-chip capacitor, its main pole is located at the gate of the pass transistor, and its secondary pole is located at the output of the LDO. The main pole and the secondary pole are respectively

PP 11 == 11 RR OUTOTAOUTOTA ** (( CC parpar ++ CC Mm )) PP 22 == 11 RR ALLALL ** CC LL

其中ROUTOTA为OTA输出端电阻；Cpar为调整管栅极寄生电容；C_M＝g_m0R_ALLC₁为米勒电容在调整管栅极等效的电容；R_ALL＝R_L//(R₁+R₂+R₃)//r_omp0为LDO输出等效电阻；Cl为输出寄生电容，其值小于100pF。在摆率增强电路开始工作时，会使ROUTOTA变小，此时动态的主极点位置会增大，摆率增强电路中的跨导放大器在负载跳变时均起作用。在轻载跳重载时，频率响应波特图如图4所示，其中虚线上翘处为高通滤波器起作用时，由于RL很小，次极点位置比较高，在摆率增强电路工作时，稳定性没有问题，因此此时可以使RC高通滤波器与跨导放大器均起作用；但在重载跳轻载时，频率响应波特图如图5所示，其中虚线上翘处为高通滤波器起作用时，RL较大，次极点位置较低，摆率增强电路如果在低频时即开始工作，会使环路不稳定，由于上冲电流随输出电压变化幅度的增大而增大，没有摆率的限制，所以跨导放大器不需要参与调节，保证更好的环路稳定性。因此未将M6管的栅极连接到M17的栅极，这样可以保证重载跳变轻载时系统的稳定性。另外，在负载跳变时，为了保证系统的稳定及快的响应速度，跳变时次极点位置应设置在带宽GBW的2.2倍左右。Among them, ROUTOTA is the OTA output terminal resistance; Cpar is the parasitic capacitance of the adjustment tube gate; C _M =g _m0 R _ALL C ₁ is the equivalent capacitance of the Miller capacitor on the adjustment tube gate; R _ALL =R _L //(R ₁ +R ₂ +R ₃ )//r _omp0 is the LDO output equivalent resistance; Cl is the output parasitic capacitance, and its value is less than 100pF. When the slew rate enhancement circuit starts to work, it will make ROUTOTA smaller, and the dynamic main pole position will increase at this time, and the transconductance amplifier in the slew rate enhancement circuit will work when the load jumps. When jumping from light load to heavy load, the frequency response Bode diagram is shown in Figure 4, where the dotted line shows that when the high-pass filter works, because RL is small, the position of the second pole is relatively high, and when the slew rate enhancement circuit is working , there is no problem with the stability, so both the RC high-pass filter and the transconductance amplifier can work at this time; but when the heavy load jumps to light load, the frequency response Bode diagram is shown in Figure 5, where the dotted line is high-pass When the filter works, RL is large, and the position of the secondary pole is low. If the slew rate enhancement circuit starts to work at low frequency, the loop will be unstable, because the overshoot current increases with the increase of the output voltage change range. , there is no limitation on the slew rate, so the transconductance amplifier does not need to participate in the adjustment, ensuring better loop stability. Therefore, the gate of the M6 tube is not connected to the gate of the M17, which can ensure the stability of the system when the heavy load jumps to light load. In addition, when the load jumps, in order to ensure the stability and fast response speed of the system, the position of the secondary pole during the jump should be set at about 2.2 times the bandwidth GBW.

本发明中的摆率增强电路也可应用于其它LDO电路设计中，通过摆率增强电路输出的调整电流，可以减小传统LDO电路中调整管栅极电压变化缓慢的影响，大大提高了LDO的摆率，并有效的减小了输出电压尖峰，利用该设计可以得到一个高摆率的LDO，负载电流在100uA到100mA间跳变，上升下降沿为0.5u时，其输入波形如图6所示，上冲180mV，下冲120mV。The slew rate enhancement circuit in the present invention can also be applied to other LDO circuit designs. The adjustment current output by the slew rate enhancement circuit can reduce the influence of the slow change of the gate voltage of the adjustment tube in the traditional LDO circuit, and greatly improve the LDO. Slew rate, and effectively reduce the output voltage peak, using this design can get a high slew rate LDO, the load current jumps between 100uA to 100mA, when the rising and falling edges are 0.5u, the input waveform is shown in Figure 6 Shown, the overshoot is 180mV, and the undershoot is 120mV.

由于该发明为片上集成LDO，采用片内补偿技术，因此不再需要大的片外电容。Since the invention is an on-chip integrated LDO and uses on-chip compensation technology, a large off-chip capacitor is no longer needed.