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CN103474466B - A kind of high tension apparatus and manufacture method thereof - Google Patents

  • ️Wed Jun 08 2016

CN103474466B - A kind of high tension apparatus and manufacture method thereof - Google Patents

A kind of high tension apparatus and manufacture method thereof Download PDF

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Publication number
CN103474466B
CN103474466B CN201310418088.4A CN201310418088A CN103474466B CN 103474466 B CN103474466 B CN 103474466B CN 201310418088 A CN201310418088 A CN 201310418088A CN 103474466 B CN103474466 B CN 103474466B Authority
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type semiconductor
conductivity type
conductive type
semiconductor
region
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2013-09-13
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CN103474466A (en
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乔明
李燕妃
蔡林希
吴文杰
许琬
陈涛
胡利志
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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2013-12-25 Publication of CN103474466A publication Critical patent/CN103474466A/en
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2016-06-08 Publication of CN103474466B publication Critical patent/CN103474466B/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109Reduced surface field [RESURF] PN junction structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156Drain regions of DMOS transistors
    • H10D62/157Impurity concentrations or distributions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及半导体技术,具体的说是涉及一种高压器件及其制造方法。本发明的高压器件集成在第一种导电类型半导体衬底上,包括第二种导电类型半导体漂移区、第二种导电类型半导体源区、第二种导电类型半导体漏区、第二种导电类型半导体重掺杂层、第一种导电类型半导体体区、第一种导电类型半导体体接触区、第一种导电类型半导体降场层、栅氧化层、场氧化层、金属前介质、多晶硅栅电极、源极金属、漏极金属,第二种导电类型半导体重掺杂层设置在场氧化层和第一种导电类型半导体降场层之间。本发明的有益效果为,在相同的导通能力的情况下具有更小的芯片面积,优化器件的表面电场,并且制备方法简单,工艺难度较低。本发明尤其适用于高压器件。

The invention relates to semiconductor technology, in particular to a high-voltage device and a manufacturing method thereof. The high-voltage device of the present invention is integrated on the semiconductor substrate of the first conductivity type, including the drift region of the semiconductor of the second conductivity type, the source region of the semiconductor of the second conductivity type, the drain region of the semiconductor of the second conductivity type, the second conductivity type semiconductor Semiconductor heavily doped layer, first conductivity type semiconductor body region, first conductivity type semiconductor body contact region, first conductivity type semiconductor field drop layer, gate oxide layer, field oxide layer, pre-metal dielectric, polysilicon gate electrode , the source metal, the drain metal, the heavily doped layer of the semiconductor of the second conductivity type is arranged between the field oxide layer and the field drop layer of the semiconductor of the first conductivity type. The invention has the beneficial effects of having a smaller chip area under the same conduction capability, optimizing the surface electric field of the device, and having a simple preparation method and low process difficulty. The invention is particularly applicable to high voltage devices.

Description

一种高压器件及其制造方法A kind of high-voltage device and its manufacturing method

技术领域technical field

本发明涉及半导体技术,具体的说是涉及一种高压器件及其制造方法。The invention relates to semiconductor technology, in particular to a high-voltage device and a manufacturing method thereof.

背景技术Background technique

高压器件是高压功率集成电路发展必不可少的部分,高压功率器件要求具有高的击穿电压,低的导通电阻和低的开关损耗。在功率LDMOS(LatralDouble-diffusedMOSFET)器件设计中,比导通电阻和击穿电压存在矛盾关系,随着击穿电压的提高,器件的比导通电阻急剧上升,从而限制了高压LDMOS器件在高压功率集成电路中的应用,尤其是在要求低导通损耗和小芯片面积的电路中。为了克服高导通电阻的问题,J.A.APPLES等人提出了RESURF(ReducedSURfaceField)降低表面场技术,被广泛应用于高压器件的设计中,其中,tripleRESURF是迄今为止,用于实际AC/DC等产品中的近乎最优良的结构,在此基础上进一步改善高压器件的比导通电阻与耐压是业界的需求,同时tripleRESURF结构的源端电场过高,影响器件可靠性。High-voltage devices are an essential part of the development of high-voltage power integrated circuits. High-voltage power devices require high breakdown voltage, low on-resistance and low switching loss. In the design of power LDMOS (LatralDouble-diffused MOSFET) devices, there is a contradictory relationship between specific on-resistance and breakdown voltage. Applications in integrated circuits, especially in circuits requiring low conduction loss and small chip area. In order to overcome the problem of high on-resistance, J.A. APPLES and others proposed RESURF (ReducedSURfaceField) to reduce the surface field technology, which is widely used in the design of high-voltage devices. Among them, tripleRESURF is so far used in actual AC/DC and other products. The near-best structure of the tripleRESURF structure, further improving the specific on-resistance and withstand voltage of high-voltage devices is the demand of the industry. At the same time, the electric field at the source of the tripleRESURF structure is too high, which affects the reliability of the device.

发明内容Contents of the invention

本发明所要解决的技术问题,就是针对上述问题,提出一种新型高压器件及其制备方法。The technical problem to be solved by the present invention is to propose a novel high-voltage device and its preparation method for the above problems.

本发明解决上述技术问题所采用的技术方案是:一种高压器件,其元胞结构包括第一种导电类型半导体衬底1、第二种导电类型半导体漂移区21、第二种导电类型半导体源区22、第二种导电类型半导体漏区23、第一种导电类型半导体体区31、第一种导电类型半导体体接触区32、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、栅氧化层41、场氧化层42、金属前介质43、多晶硅栅电极51、源极金属52和漏极金属53,所述第二种导电类型半导体漂移区21、第一种导电类型半导体体区31和第一种导电类型半导体体区埋层33设置在第一种导电类型半导体衬底1中,所述第一种导电类型半导体体区埋层33设置在第一种导电类型半导体体区31的下表面,所述第一种导电类型半导体降场层34和第二种导电类型半导体漏区23设置在第二种导电类型半导体漂移区21中,所述第二种导电类型半导体源区22和第一种导电类型半导体体接触区32设置在第一种导电类型半导体体区31中并相互独立,所述场氧化层42设置在第二种导电类型半导体漂移区21的上表面,所述栅氧化层41设置在部分第二种导电类型半导体源区22的上表面、第一种导电类型半导体体区31的上表面和第二种导电类型半导体漂移区21的上表面并与场氧化层42连接,所述多晶硅栅电极51设置在栅氧化层41的上表面和部分场氧化层42的上表面,所述源极金属52设置在第一种导电类型半导体体接触区32的上表面、部分第二种导电类型半导体源区22的上表面,所述漏极金属53设置在部分第二种导电类型半导体漏区23的上表面,所述金属前介质43填充在源极金属52和漏极金属53之间,源极金属52和漏极金属53在金属前介质43上表面延伸形成场板,其特征在于,还包括第二种导电类型半导体重掺杂层,所述第二种导电类型半导体重掺杂层由分为多段的第二种导电类型半导体区域构成并设置在第一种导电类型半导体降场层34和场氧化层42之间。The technical solution adopted by the present invention to solve the above technical problems is: a high-voltage device whose cellular structure includes a semiconductor substrate 1 of the first conductivity type, a semiconductor drift region 21 of the second conductivity type, a semiconductor source of the second conductivity type Region 22, the second conductivity type semiconductor drain region 23, the first conductivity type semiconductor body region 31, the first conductivity type semiconductor body contact region 32, the first conductivity type semiconductor body region buried layer 33, the first conductivity type semiconductor body region Type semiconductor drop field layer 34, gate oxide layer 41, field oxide layer 42, pre-metal dielectric 43, polysilicon gate electrode 51, source metal 52 and drain metal 53, the second conductivity type semiconductor drift region 21, the first One conductivity type semiconductor body region 31 and the first conductivity type semiconductor body region buried layer 33 are arranged in the first conductivity type semiconductor substrate 1, and the first conductivity type semiconductor body region buried layer 33 is arranged on the first The lower surface of the semiconductor body region 31 of the first conductivity type, the field drop layer 34 of the semiconductor of the first conductivity type and the drain region 23 of the semiconductor of the second conductivity type are arranged in the drift region 21 of the semiconductor of the second conductivity type, the second The first conductivity type semiconductor source region 22 and the first conductivity type semiconductor body contact region 32 are arranged in the first conductivity type semiconductor body region 31 and are independent of each other, and the field oxide layer 42 is arranged in the second conductivity type semiconductor drift region 21, the gate oxide layer 41 is provided on the upper surface of part of the second conductivity type semiconductor source region 22, the upper surface of the first conductivity type semiconductor body region 31 and the second conductivity type semiconductor drift region 21 The upper surface is connected to the field oxide layer 42, the polysilicon gate electrode 51 is arranged on the upper surface of the gate oxide layer 41 and part of the upper surface of the field oxide layer 42, and the source metal 52 is arranged on the first conductivity type semiconductor body The upper surface of the contact region 32 and the upper surface of part of the semiconductor source region 22 of the second conductivity type, the drain metal 53 is arranged on the upper surface of the drain region 23 of a part of the second conductivity type semiconductor, and the pre-metal dielectric 43 fills Between the source metal 52 and the drain metal 53, the source metal 52 and the drain metal 53 extend on the upper surface of the pre-metal dielectric 43 to form a field plate, which is characterized in that it also includes a second conductivity type semiconductor heavily doped layer The heavily doped layer of the semiconductor of the second conductivity type is composed of semiconductor regions of the semiconductor of the second conductivity type divided into multiple sections, and is arranged between the field drop layer 34 of the semiconductor of the first conductivity type and the field oxide layer 42 .

其中,第二种导电类型半导体重掺杂层分为61~6i多段,多个第二种导电类型半导体重掺杂层61~6i的分段区域大小可以相同或不同,区域间距随着向第二种导电类型半导体漏区23靠近而逐渐减小,分段区域的间距可以相同或不相同,区域大小随着向第二种导电类型半导体漏区23靠近而逐渐增大。Among them, the heavily doped semiconductor layer of the second conductivity type is divided into multiple sections 6 1 to 6 i , and the size of the segmented regions of the heavily doped semiconductor layers 6 1 to 6 i of the second conductivity type can be the same or different, and the area spacing The spacing of the segmented regions may be the same or different, and the size of the region gradually increases as it approaches the drain region 23 of the semiconductor of the second conductivity type.

具体的,还包括第二种导电类型半导体埋层24,所述第二种导电类型半导体埋层24设置在第二种导电类型半导体漂移区21中并位于第一种导电类型半导体降场层34的下表面。Specifically, it also includes a second conductivity type semiconductor buried layer 24, the second conductivity type semiconductor buried layer 24 is disposed in the second conductivity type semiconductor drift region 21 and is located in the first conductivity type semiconductor drop field layer 34 the lower surface.

本方案的优点在于为器件提供另一条低阻的导电通道。The advantage of this solution is to provide another low-resistance conductive channel for the device.

具体的,所述第一种导电类型半导体体区31和第一种导电类型半导体体区埋层33设置在第二种导电类型半导体漂移区21中。Specifically, the semiconductor body region 31 of the first conductivity type and the buried layer 33 of the semiconductor body region of the first conductivity type are disposed in the semiconductor drift region 21 of the second conductivity type.

具体的,所述第二种导电类型半导体漂移区21设置在第一种导电类型半导体衬底1的上表面。Specifically, the semiconductor drift region 21 of the second conductivity type is disposed on the upper surface of the semiconductor substrate 1 of the first conductivity type.

具体的,还包括SOI衬底2,所述SOI衬底2设置在第一种导电类型半导体衬底1和第二种导电类型半导体漂移区21之间并分别与第一种导电类型半导体衬底1和第二种导电类型半导体漂移区21连接。Specifically, an SOI substrate 2 is also included, and the SOI substrate 2 is arranged between the semiconductor substrate 1 of the first conductivity type and the semiconductor drift region 21 of the second conductivity type and is connected to the semiconductor substrate of the first conductivity type respectively. 1 is connected to the drift region 21 of the semiconductor of the second conductivity type.

一种高压器件的制造方法,其特征在于,包括以下步骤:A method for manufacturing a high-voltage device, comprising the following steps:

第一步:采用光刻和离子注入工艺,在第一种导电类型半导体衬底1中注入第二种导电类型半导体杂质,退火扩散形成第二种导电类型半导体漂移区21,所述第一种导电类型半导体衬底1的电阻率为10~200欧姆·厘米,第二种导电类型半导体漂移区21的注入剂量为1E12cm-2~2E13cm-2The first step: using photolithography and ion implantation process, implanting semiconductor impurities of the second conductivity type into the semiconductor substrate 1 of the first conductivity type, and annealing and diffusing to form the semiconductor drift region 21 of the second conductivity type. The resistivity of the conductive type semiconductor substrate 1 is 10-200 ohm·cm, and the implantation dose of the second conductive type semiconductor drift region 21 is 1E12cm -2 -2E13cm -2 ;

第二步:采用光刻和离子注入工艺,在第一种导电类型半导体衬底1中注入第一种导电类型半导体杂质,退火扩散形成第一种导电类型半导体体区31,所述第一种导电类型半导体体区31的注入剂量为1E12cm-2~5E13cm-2Step 2: Using photolithography and ion implantation techniques, implanting semiconductor impurities of the first conductivity type into the semiconductor substrate 1 of the first conductivity type, and annealing and diffusing to form the semiconductor body region 31 of the first conductivity type. The implantation dose of the conductivity type semiconductor body region 31 is 1E12cm -2 ~ 5E13cm -2 ;

第三步:在第二种导电类型半导体漂移区21上表面形成场氧化层42;Step 3: Forming a field oxide layer 42 on the upper surface of the semiconductor drift region 21 of the second conductivity type;

第四步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中注入第一种导电类型半导体杂质,形成第一种导电类型半导体体区埋层33和第一种导电类型半导体降场层34,所述第一种导电类型半导体杂质的注入剂量为1E11cm-2~2E13cm-2Step 4: Using photolithography and ion implantation process, implant semiconductor impurities of the first conductivity type into the drift region 21 of the semiconductor of the second conductivity type to form the buried layer 33 of the semiconductor body region of the first conductivity type and the first conductivity type semiconductor The semiconductor drop-off layer 34, the implantation dose of the semiconductor impurity of the first conductivity type is 1E11cm -2 ~ 2E13cm -2 ;

第五步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中注入第二种导电类型半导体杂质,快速热退火形成分段的第二种导电类型半导体重掺杂层,所述第二种导电类型半导体重掺杂层的注入剂量为1E11cm-2~2E13cm-2Step 5: using photolithography and ion implantation processes, implanting second conductivity type semiconductor impurities into the second conductivity type semiconductor drift region 21, rapid thermal annealing to form segmented second conductivity type semiconductor heavily doped layers, The implant dose of the heavily doped semiconductor layer of the second conductivity type is 1E11cm -2 ~ 2E13cm -2 ;

第六步:在部分第二种导电类型半导体源区22的上表面、第一种导电类型半导体体区31的上表面和第二种导电类型半导体漂移区21的上表面形成栅氧化层41,所述栅氧化层41的厚度为7nm~100nm;Step 6: Form a gate oxide layer 41 on the upper surface of part of the second conductivity type semiconductor source region 22, the upper surface of the first conductivity type semiconductor body region 31 and the upper surface of the second conductivity type semiconductor drift region 21, The thickness of the gate oxide layer 41 is 7nm-100nm;

第七步:在栅氧化层41的上表面和部分场氧化层42的上表面形成多晶硅栅电极51,所述多晶硅栅极51的方块电阻值为10~40欧姆/方块;Step 7: Forming a polysilicon gate electrode 51 on the upper surface of the gate oxide layer 41 and the upper surface of the partial field oxide layer 42, the square resistance value of the polysilicon gate 51 is 10-40 ohms/square;

第八步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中形成第二种导电类型半导体漏区23,在第一种导电类型半导体体区31中形成相互独立的第二种导电类型半导体源区22、第一种导电类型半导体体接触区32,所述第二种导电类型半导体漏区23、第二种导电类型半导体源22、第一种导电类型半导体体接触区32的注入剂量为1E13cm-2~2E16cm-2Step 8: Form the second conductivity type semiconductor drain region 23 in the second conductivity type semiconductor drift region 21 by using photolithography and ion implantation technology, and form mutually independent first conductivity type semiconductor body regions 31 The second conductivity type semiconductor source region 22, the first conductivity type semiconductor body contact region 32, the second conductivity type semiconductor drain region 23, the second conductivity type semiconductor source 22, the first conductivity type semiconductor body contact region The injection dose of 32 is 1E13cm -2 ~ 2E16cm -2 ;

第九步:在部分第二种导电类型半导体源22的上表面、多晶硅栅极51的上表面、氧化层42的上表面和部分第二种导电类型半导体漏区23的上表面淀积形成金属前介质43;Step 9: Deposit and form metal on the upper surface of part of the second conductivity type semiconductor source 22 , the upper surface of the polysilicon gate 51 , the upper surface of the oxide layer 42 and the upper surface of part of the second conductivity type semiconductor drain region 23 pre-medium 43;

第十步:在第一种导电类型半导体体接触区32的上表面和第二种导电类型半导体源22的上表面形成源极金属52,在第二种导电类型半导体漏区23的上表面形成漏极金属53,源极金属52和漏极金属53与金属前介质43连接并在金属前介质43的上表面延伸形成场板。Step 10: Form the source metal 52 on the upper surface of the first conductivity type semiconductor body contact region 32 and the upper surface of the second conductivity type semiconductor source 22, and form the upper surface of the second conductivity type semiconductor drain region 23 The drain metal 53 , the source metal 52 and the drain metal 53 are connected to the pre-metal dielectric 43 and extend on the upper surface of the pre-metal dielectric 43 to form a field plate.

具体的,所述第一种导电类型半导体体区埋层33可以防止寄生三极管导通,提高器件的性能,第四步也可以不形成第一种导电类型半导体体区埋层33。Specifically, the buried layer 33 of the semiconductor body region of the first conductivity type can prevent the conduction of the parasitic transistor and improve the performance of the device. In the fourth step, the buried layer 33 of the semiconductor body region of the first conductivity type may not be formed.

具体的,所述第五步中,分段的第二种导电类型半导体重掺杂层61~6i通过快速热退火工艺形成,其注入窗口大小相同或不同,窗口间距随着向第二种导电类型半导体漏区23靠近而逐渐减小,注入窗口的间距相同或不相同,窗口大小随着向第二种导电类型半导体漏区23靠近而逐渐增大。Specifically, in the fifth step, the segmented heavily doped layers 6 1 to 6 i of semiconductors of the second conductivity type are formed by a rapid thermal annealing process, and their implantation windows have the same or different sizes, and the window spacing increases with the second The semiconductor drain region 23 of the second conductivity type approaches and gradually decreases, the distances of the injection windows are the same or different, and the size of the window gradually increases as it approaches the drain region 23 of the second conductivity type semiconductor.

进一步的,还可以通过外延工艺形成第二种导电类型半导体漂移区21,或在SOI衬底材料上形成第二种导电类型半导体漂移区21,第二种导电类型半导体重掺杂层61~6i采用分段掺杂,耐压时引入多个表面场尖峰,优化器件表面电场,同时避免源端电场过大,防止强场效应。Further, the second conductivity type semiconductor drift region 21 can also be formed by epitaxial process, or the second conductivity type semiconductor drift region 21 can be formed on the SOI substrate material, and the second conductivity type semiconductor heavily doped layer 6 1 ~ 6i adopts segmental doping, and introduces multiple surface field peaks when withstand voltage, optimizes the surface electric field of the device, and at the same time avoids excessive electric field at the source end to prevent strong field effects.

本发明的有益效果为,在保持高的击穿耐压的情况下,可以大大的降低器件比导通电阻,同时减小高压器件源端的电场峰值,避免强场效应,提高器件的击穿电压,与传统高压器件相比,本发明提供的高压器件在相同芯片面积的情况下具有更小的导通电阻,在相同的导通能力的情况下具有更小的芯片面积,并很好地优化器件的表面电场,同时,本发明提供的制备方法简单,工艺难度较低。The beneficial effect of the present invention is that, in the case of maintaining a high breakdown withstand voltage, the specific on-resistance of the device can be greatly reduced, and at the same time, the peak value of the electric field at the source end of the high-voltage device can be reduced, the strong field effect can be avoided, and the breakdown voltage of the device can be improved. , compared with traditional high-voltage devices, the high-voltage device provided by the present invention has smaller on-resistance under the same chip area, has smaller chip area under the same conduction capability, and is well optimized The surface electric field of the device, at the same time, the preparation method provided by the invention is simple and the process difficulty is low.

附图说明Description of drawings

图1是传统高压器件的剖面示意图;Figure 1 is a schematic cross-sectional view of a conventional high-voltage device;

图2是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,第二种导电类型半导体漂移区21通过离子注入和推结工艺形成,集成在第一种导电类型半导体衬底1上;FIG. 2 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The spacing is gradually reduced, and the semiconductor drift region 21 of the second conductivity type is formed by ion implantation and junction pushing process, and integrated on the semiconductor substrate 1 of the first conductivity type;

图3是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,第二种导电类型半导体漂移区2为通过离子注入和推结工艺形成,集成在第一种导电类型半导体衬底1上;FIG. 3 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The width gradually increases, and the semiconductor drift region 2 of the second conductivity type is formed by ion implantation and junction pushing process, and is integrated on the semiconductor substrate 1 of the first conductivity type;

图4是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,第二种导电类型半导体漂移区21通过外延工艺形成,集成在第一种导电类型半导体衬底1上;FIG. 4 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The spacing is gradually reduced, and the semiconductor drift region 21 of the second conductivity type is formed by an epitaxial process and integrated on the semiconductor substrate 1 of the first conductivity type;

图5是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,第二种导电类型半导体漂移区21为通过外延工艺形成,集成在第一种导电类型半导体衬底1上;FIG. 5 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The width gradually increases, and the semiconductor drift region 21 of the second conductivity type is formed by an epitaxial process and integrated on the semiconductor substrate 1 of the first conductivity type;

图6是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,第二种导电类型半导体漂移区21通过外延工艺形成,集成在SOI衬底上;FIG. 6 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The spacing is gradually reduced, and the second conductivity type semiconductor drift region 21 is formed by an epitaxial process and integrated on the SOI substrate;

图7是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,第二种导电类型半导体漂移区21通过外延工艺形成,集成在SOI衬底上;FIG. 7 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The width gradually increases, and the second conductivity type semiconductor drift region 21 is formed by an epitaxial process and integrated on the SOI substrate;

图8是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,第二种导电类型半导体埋层24设置在第二种导电类型半导体漂移区21中,位于第一种导电类型半导体降场层34下方;Fig. 8 is a schematic cross-sectional view of a high-voltage device of the present invention, as the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 - 6 i The spacing gradually decreases, and the buried layer 24 of the semiconductor of the second conductivity type is disposed in the drift region 21 of the semiconductor of the second conductivity type, and is located below the field drop layer 34 of the semiconductor of the first conductivity type;

图9是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,第二种导电类型半导体埋层24设置在第二种导电类型半导体漂移区21中,位于第一种导电类型半导体降场层34下方;Fig. 9 is a schematic cross-sectional view of a high-voltage device of the present invention, as the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 - 6 i The width gradually increases, and the buried layer 24 of the semiconductor of the second conductivity type is disposed in the drift region 21 of the semiconductor of the second conductivity type, and is located under the field drop layer 34 of the semiconductor of the first conductivity type;

图10是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,所有高压器件结构都设置在第二种导电类型半导体漂移区21中;FIG. 10 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The spacing is gradually reduced, and all high-voltage device structures are arranged in the second conductivity type semiconductor drift region 21;

图11是本发明的一种高压器件的剖面示意图,随着向第二种导电类型半导体漏极重掺杂区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,,所有高压器件结构都设置在第二种导电类型半导体漂移区21中;FIG. 11 is a schematic cross-sectional view of a high-voltage device of the present invention. As the second conductivity type semiconductor heavily doped region 23 approaches, the segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i The width gradually increases, and all high-voltage device structures are arranged in the second conductivity type semiconductor drift region 21;

图12是实施例1中第二种导电类型半导体重掺杂层61~6i的多个注入窗口结构示意图;Fig. 12 is a schematic diagram of the structure of multiple injection windows of the heavily doped semiconductor layers 6 1 - 6 i of the second conductivity type in Embodiment 1;

图13是实施例1注入形成分段的第二种导电类型半导体重掺杂层61~6i示意图;Fig. 13 is a schematic diagram of segmented heavily doped semiconductor layers 6 1 - 6 i of the second conductivity type formed by implantation in Embodiment 1;

图14是实施例2中第二种导电类型半导体重掺杂层61~6i的多个注入窗口结构示意图;Fig. 14 is a schematic diagram of the structure of multiple injection windows of the heavily doped semiconductor layers 6 1 - 6 i of the second conductivity type in Embodiment 2;

图15是实施例2注入形成分段的第二种导电类型半导体重掺杂层61~6i示意图。FIG. 15 is a schematic diagram of segmented heavily doped semiconductor layers 6 1 -6 i of the second conductivity type formed by implantation in Embodiment 2. FIG.

具体实施方式detailed description

下面结合附图和实施例,详细描述本发明的技术方案:Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

如图1所示,为传统的高压器件结构剖面图,高压器件集成在第一种导电类型半导体衬底1上,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32;第一种导电类型半导体降场层34通过离子注入工艺实现、被第二种导电类型半导体漂移区21包围;第一种导电类型半导体体区埋层33位于第一种导电类型体区31和第一种导电类型半导体衬底1之间;源极金属52位于第一种导电类型半导体体区31上侧、与第二种导电类型半导体源区22和第一种导电类型半导体体接触区32相连,漏极金属53与第二种导电类型半导体漏区23相连;多晶硅栅电极51位于栅氧化层41上方,场氧化层43位于第二种导电类型半导体漂移区21上方;多晶硅栅电极51、源极金属52和漏极金属53之间通过金属前介质43相互隔离。As shown in FIG. 1 , it is a cross-sectional view of a traditional high-voltage device structure. The high-voltage device is integrated on a semiconductor substrate 1 of the first conductivity type, including a semiconductor drift region 21 of the second conductivity type and a semiconductor body region 31 of the first conductivity type. , the buried layer 33 of the semiconductor body region of the first conductivity type, the field drop layer 34 of the semiconductor of the first conductivity type, the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the drain region 23 of the semiconductor of the second conductivity type, the second The second conductivity type semiconductor source region 22, the first conductivity type semiconductor body contact region 32; the first conductivity type semiconductor drop field layer 34 is realized by ion implantation technology, surrounded by the second conductivity type semiconductor drift region 21; the first conductivity type semiconductor drift region 21 The semiconductor body region buried layer 33 of the first conductivity type is located between the body region 31 of the first conductivity type and the semiconductor substrate 1 of the first conductivity type; the source metal 52 is located on the upper side of the semiconductor body region 31 of the first conductivity type, and The second conductivity type semiconductor source region 22 is connected to the first conductivity type semiconductor body contact region 32, and the drain metal 53 is connected to the second conductivity type semiconductor drain region 23; the polysilicon gate electrode 51 is located above the gate oxide layer 41, and the field oxidation The layer 43 is located above the drift region 21 of the semiconductor of the second conductivity type; the polysilicon gate electrode 51 , the source metal 52 and the drain metal 53 are isolated from each other by the pre-metal dielectric 43 .

如图2所示,为本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53;其特征在于,所述高压半导体器件还包括第一种导电类型半导体降场层34和第二种导电类型半导体重掺杂层61~6i,所述第二种导电类型半导体重掺杂层61~6i位于场氧化层42和第一种导电类型半导体降场层34之间。其中,第一种导电类型半导体降场层34通过离子注入和推结工艺实现,第二种导电类型半导体重掺杂层61~6i通过离子注入和快速热退火工艺实现,随着向第一种导电类型半导体漏区23靠近,分段的第二种导电类型半导体重掺杂区61~6i间距逐渐减小,该结构不仅降低器件的比导通电阻,还降低器件源端电场分布,避免强场效应,优化器件表面电场,从而提高器件击穿电压,缓解耐压和比导通电阻的矛盾关系。As shown in FIG. 2 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductivity type semiconductor drop field layer 34, the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductivity type semiconductor drain region 23, the second conductivity type semiconductor source region 22, the first Conduction type semiconductor body contact region 32, metal pre-dielectric 43, source metal 52, drain metal 53; it is characterized in that, the high-voltage semiconductor device also includes the first conductivity type semiconductor drop field layer 34 and the second conductivity type Type semiconductor heavily doped layers 6 1 to 6 i , the second conductive type semiconductor heavily doped layers 6 1 to 6 i are located between the field oxide layer 42 and the first conductive type semiconductor field drop layer 34 . Among them, the first conductive type semiconductor field drop layer 34 is realized by ion implantation and push junction technology, and the second conductive type semiconductor heavily doped layers 6 1 ~ 6 i are realized by ion implantation and rapid thermal annealing technology. One conductivity type semiconductor drain region 23 is close, and the interval between segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i is gradually reduced. This structure not only reduces the specific on-resistance of the device, but also reduces the electric field at the source end of the device. distribution, avoid strong field effects, optimize the electric field on the surface of the device, thereby increasing the breakdown voltage of the device, and alleviating the contradictory relationship between withstand voltage and specific on-resistance.

如图3所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。其中,第一种导电类型半导体降场层34通过离子注入和推结工艺实现,第二种导电类型半导体重掺杂层61~6i通过离子注入和快速热退火工艺实现,随着向第一种导电类型半导体漏区23靠近,分段的第二种导电类型半导体重掺杂区61~6i宽度逐渐增大,其工作原理与图2相似,降低器件源端电场分布,避免强场效应,提高器件击穿电压,同时为电流提供低阻通道,降低器件比导通电阻,缓解比导通电阻和耐压的矛盾关系。As shown in FIG. 3 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductive type semiconductor field drop layer 34, the second conductive type semiconductor heavily doped layers 6 1 to 6 i , the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductive type semiconductor The drain region 23 , the second conductivity type semiconductor source region 22 , the first conductivity type semiconductor body contact region 32 , the pre-metal dielectric 43 , the source metal 52 , and the drain metal 53 . Among them, the first conductive type semiconductor field drop layer 34 is realized by ion implantation and push junction technology, and the second conductive type semiconductor heavily doped layers 6 1 ~ 6 i are realized by ion implantation and rapid thermal annealing technology. One conductivity type semiconductor drain region 23 is close, and the width of segmented second conductivity type semiconductor heavily doped regions 6 1 to 6 i gradually increases. Its working principle is similar to that in FIG. The field effect increases the breakdown voltage of the device, and at the same time provides a low-impedance channel for the current, reduces the specific on-resistance of the device, and eases the contradictory relationship between the specific on-resistance and the withstand voltage.

如图4所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。其中,器件集成在第一种导电类型半导体衬底1上,第二种导电类型半导体漂移区21通过外延工艺实现,其他工艺过程和工作原理参见对图2的说明。As shown in FIG. 4 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductive type semiconductor field drop layer 34, the second conductive type semiconductor heavily doped layers 6 1 to 6 i , the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductive type semiconductor The drain region 23 , the second conductivity type semiconductor source region 22 , the first conductivity type semiconductor body contact region 32 , the pre-metal dielectric 43 , the source metal 52 , and the drain metal 53 . Wherein, the device is integrated on the semiconductor substrate 1 of the first conductivity type, and the drift region 21 of the semiconductor of the second conductivity type is realized through an epitaxial process. For other processes and working principles, refer to the description of FIG. 2 .

如图5所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。其中,器件集成在第一种导电类型半导体衬底1上,第二种导电类型半导体漂移区21通过外延工艺实现,其他工艺过程和工作原理参见对图3的说明。As shown in FIG. 5 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductive type semiconductor field drop layer 34, the second conductive type semiconductor heavily doped layers 6 1 to 6 i , the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductive type semiconductor The drain region 23 , the second conductivity type semiconductor source region 22 , the first conductivity type semiconductor body contact region 32 , the pre-metal dielectric 43 , the source metal 52 , and the drain metal 53 . Wherein, the device is integrated on the semiconductor substrate 1 of the first conductivity type, and the drift region 21 of the semiconductor of the second conductivity type is realized through an epitaxial process. For other processes and working principles, refer to the description of FIG. 3 .

如图6所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。其中,器件集成在SOI衬底材料上,第二种导电类型半导体漂移区21通过外延工艺实现,其他工艺过程和工作原理参见对图2的说明。As shown in FIG. 6 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductive type semiconductor field drop layer 34, the second conductive type semiconductor heavily doped layers 6 1 to 6 i , the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductive type semiconductor The drain region 23 , the second conductivity type semiconductor source region 22 , the first conductivity type semiconductor body contact region 32 , the pre-metal dielectric 43 , the source metal 52 , and the drain metal 53 . Wherein, the device is integrated on the SOI substrate material, and the drift region 21 of the semiconductor of the second conductivity type is realized through an epitaxial process. For other processes and working principles, refer to the description of FIG. 2 .

如图7所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。其中,器件集成在SOI衬底材料上,第二种导电类型半导体漂移区21通过外延工艺实现,其他工艺过程和工作原理参见对图3的说明。As shown in FIG. 7 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductive type semiconductor field drop layer 34, the second conductive type semiconductor heavily doped layers 6 1 to 6 i , the field oxide layer 42, the gate oxide layer 41, the polysilicon gate electrode 51, the second conductive type semiconductor The drain region 23 , the second conductivity type semiconductor source region 22 , the first conductivity type semiconductor body contact region 32 , the pre-metal dielectric 43 , the source metal 52 , and the drain metal 53 . Wherein, the device is integrated on the SOI substrate material, and the drift region 21 of the semiconductor of the second conductivity type is realized through an epitaxial process. For other processes and working principles, refer to the description of FIG. 3 .

如图8所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、第二种导电类型半导体埋层24、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。第二种导电类型半导体埋层24设置在第二种导电类型半导体漂移区21中,其上表面与第一种导电类型半导体降场层34相连,第二种导电类型半导体埋层24为高压器件提高了另一条低阻通道,进一步降低比导通电阻。其他工艺过程和工作原理参见对图2的说明。As shown in FIG. 8 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductivity type semiconductor field drop layer 34, the second conductivity type semiconductor heavily doped layers 6 1 to 6 i , the second conductivity type semiconductor buried layer 24, the field oxide layer 42, the gate oxide layer 41, polysilicon Gate electrode 51 , second conductivity type semiconductor drain region 23 , second conductivity type semiconductor source region 22 , first conductivity type semiconductor body contact region 32 , pre-metal dielectric 43 , source metal 52 , drain metal 53 . The second conductivity type semiconductor buried layer 24 is disposed in the second conductivity type semiconductor drift region 21, and its upper surface is connected to the first conductivity type semiconductor drop field layer 34, and the second conductivity type semiconductor buried layer 24 is a high voltage device Another low-impedance channel is improved to further reduce the specific on-resistance. For other technological processes and working principles, refer to the description of FIG. 2 .

如图9所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、第二种导电类型半导体埋层24、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。第二种导电类型半导体埋层24设置在第二种导电类型半导体漂移区21中,其上表面与第一种导电类型半导体降场层34相连,第二种导电类型半导体埋层24为高压器件提高了另一条低阻通道,进一步降低比导通电阻。其他工艺过程和工作原理参见对图3的说明。As shown in FIG. 9 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductivity type semiconductor field drop layer 34, the second conductivity type semiconductor heavily doped layers 6 1 to 6 i , the second conductivity type semiconductor buried layer 24, the field oxide layer 42, the gate oxide layer 41, polysilicon Gate electrode 51 , second conductivity type semiconductor drain region 23 , second conductivity type semiconductor source region 22 , first conductivity type semiconductor body contact region 32 , pre-metal dielectric 43 , source metal 52 , drain metal 53 . The second conductivity type semiconductor buried layer 24 is disposed in the second conductivity type semiconductor drift region 21, and its upper surface is connected to the first conductivity type semiconductor drop field layer 34, and the second conductivity type semiconductor buried layer 24 is a high voltage device Another low-impedance channel is improved to further reduce the specific on-resistance. For other technological processes and working principles, refer to the description of FIG. 3 .

如图10所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、第二种导电类型半导体埋层24、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。高压器件所有结构都设置在第二种导电类型半导体漂移区21中,第一种导电类型半导体体区和第二种导电类型半导体漂移区21实现自隔离。其他工艺过程和工作原理参见对图2的说明。As shown in FIG. 10 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductivity type semiconductor field drop layer 34, the second conductivity type semiconductor heavily doped layers 6 1 to 6 i , the second conductivity type semiconductor buried layer 24, the field oxide layer 42, the gate oxide layer 41, polysilicon Gate electrode 51 , second conductivity type semiconductor drain region 23 , second conductivity type semiconductor source region 22 , first conductivity type semiconductor body contact region 32 , pre-metal dielectric 43 , source metal 52 , drain metal 53 . All structures of the high-voltage device are arranged in the drift region 21 of the semiconductor of the second conductivity type, and the body region of the semiconductor of the first conductivity type and the drift region 21 of the semiconductor of the second conductivity type realize self-isolation. For other technological processes and working principles, refer to the description of FIG. 2 .

如图11所示,是本发明提供的一种高压器件结构剖面图,包括第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体体区埋层33、第一种导电类型半导体降场层34、第二种导电类型半导体重掺杂层61~6i、第二种导电类型半导体埋层24、场氧化层42、栅氧化层41、多晶硅栅电极51、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32、金属前介质43、源极金属52、漏极金属53。高压器件所有结构都设置在第二种导电类型半导体漂移区21中,第一种导电类型半导体体区和第二种导电类型半导体漂移区21实现自隔离。其他工艺过程和工作原理参见对图3的说明。As shown in FIG. 11 , it is a cross-sectional view of a high-voltage device structure provided by the present invention, including a semiconductor drift region 21 of the second conductivity type, a semiconductor body region 31 of the first conductivity type, and a buried layer of the semiconductor body region of the first conductivity type. 33. The first conductivity type semiconductor field drop layer 34, the second conductivity type semiconductor heavily doped layers 6 1 to 6 i , the second conductivity type semiconductor buried layer 24, the field oxide layer 42, the gate oxide layer 41, polysilicon Gate electrode 51 , second conductivity type semiconductor drain region 23 , second conductivity type semiconductor source region 22 , first conductivity type semiconductor body contact region 32 , pre-metal dielectric 43 , source metal 52 , drain metal 53 . All structures of the high-voltage device are arranged in the drift region 21 of the semiconductor of the second conductivity type, and the body region of the semiconductor of the first conductivity type and the drift region 21 of the semiconductor of the second conductivity type realize self-isolation. For other technological processes and working principles, refer to the description of FIG. 3 .

本发明的工作原理为:Working principle of the present invention is:

本发明的工作原理与传统的高压器件类似,都是应用电荷平衡原理来提高器件的击穿电压,但本发明提供的横向高压器件导通损耗低于传统横向高压器件。图1为传统的高压器件,包括第一种导电类型半导体衬底1、第二种导电类型半导体漂移区21、第一种导电类型半导体体区31、第一种导电类型半导体降场层34、场氧化层42、栅氧化层41、多晶硅栅极51、金属前介质43、第二种导电类型半导体漏区23、第二种导电类型半导体源区22、第一种导电类型半导体体接触区32。器件导通时,电流从第二种导电类型半导体漏区23区经第二种导电类型半导体漂移区21流到第二种导电类型半导体源区22,由于第二种导电类型半导体漂移区21的浓度较低,器件的导通电阻很大,导通损耗增加。如图2所示,为本发明提供的高压器件,与传统横向高压器件相比,本发明提供的高压器件通过离子注入工艺在第二种导电类型半导体漂移区21中形成第一种导电类型半导体降场层34,并通过离子注入和推结工艺在第二种导电类型半导体漂移区21表面形成分段的第二种导电类型半导体重掺杂层61~6i。开态时,高浓度的重掺杂层61~6i为高压器件提供了大量的多数载流子,在器件表面形成一个低阻的导电通道,可以极大地减小器件导通电阻,从而大大的降低工艺成本。关态时,漏极金属53加高压,第一种导电类型半导体降场层34和第一种导电类型半导体衬底1辅助耗尽第二种导电类型半导体漂移区21和第二种导电类型半导体重掺杂层61~6i,使得器件获得较大的击穿电压。同时,分段的第二种导电类型半导体重掺杂61~6i降低器件的源端电场,避免强场效应,在表面引入多个电场尖峰,调制漂移区21的表面电场,提高器件的耐压,从而缓解了横向高压功率器件中比导通电阻和耐压的矛盾关系。因此,在功率集成电路应用中,同样输出电流能力的条件下,高压半导体器件的面积得以降低。The working principle of the present invention is similar to that of traditional high-voltage devices, which use the principle of charge balance to increase the breakdown voltage of the device, but the conduction loss of the lateral high-voltage device provided by the present invention is lower than that of traditional lateral high-voltage devices. 1 is a traditional high-voltage device, including a first conductivity type semiconductor substrate 1, a second conductivity type semiconductor drift region 21, a first conductivity type semiconductor body region 31, a first conductivity type semiconductor drop field layer 34, Field oxide layer 42, gate oxide layer 41, polysilicon gate 51, pre-metal dielectric 43, second conductivity type semiconductor drain region 23, second conductivity type semiconductor source region 22, first conductivity type semiconductor body contact region 32 . When the device is turned on, the current flows from the second conductivity type semiconductor drain region 23 to the second conductivity type semiconductor drift region 21 to the second conductivity type semiconductor source region 22, due to the second conductivity type semiconductor drift region 21 When the concentration is low, the on-resistance of the device is very large, and the conduction loss increases. As shown in Figure 2, for the high-voltage device provided by the present invention, compared with the traditional lateral high-voltage device, the high-voltage device provided by the present invention forms the first conductive type semiconductor in the second conductive type semiconductor drift region 21 by ion implantation process drop field layer 34 , and form segmented second conductive type semiconductor heavily doped layers 6 1 -6 i on the surface of the second conductive type semiconductor drift region 21 by ion implantation and push-junction processes. In the on state, the high-concentration heavily doped layers 6 1 ~ 6 i provide a large number of majority carriers for the high-voltage device, forming a low-resistance conduction channel on the device surface, which can greatly reduce the on-resistance of the device, thereby Greatly reduce the process cost. In the off state, a high voltage is applied to the drain metal 53, and the first conductivity type semiconductor drop layer 34 and the first conductivity type semiconductor substrate 1 assist in depleting the second conductivity type semiconductor drift region 21 and the second conductivity type semiconductor The heavily doped layers 6 1 -6 i enable the device to obtain a larger breakdown voltage. At the same time, the segmented semiconductors of the second conductivity type are heavily doped 6 1 ~ 6 i to reduce the source electric field of the device, avoid strong field effects, introduce multiple electric field peaks on the surface, modulate the surface electric field of the drift region 21, and improve the device's withstand voltage, thereby alleviating the contradictory relationship between specific on-resistance and withstand voltage in lateral high-voltage power devices. Therefore, in the application of power integrated circuits, under the condition of the same output current capability, the area of the high-voltage semiconductor device can be reduced.

本发明提供的一种高压器件的制备方法步骤如下:A kind of preparation method step of high-voltage device provided by the present invention is as follows:

第一步:采用光刻和离子注入工艺,在第一种导电类型半导体衬底1中注入第二种导电类型半导体杂质,退火扩散形成第二种导电类型半导体漂移区21,所述第一种导电类型半导体衬底1的电阻率为10~200欧姆·厘米,第二种导电类型半导体漂移区21的注入剂量为1E12cm-2~2E13cm-2The first step: using photolithography and ion implantation process, implanting semiconductor impurities of the second conductivity type into the semiconductor substrate 1 of the first conductivity type, and annealing and diffusing to form the semiconductor drift region 21 of the second conductivity type. The resistivity of the conductive type semiconductor substrate 1 is 10-200 ohm·cm, and the implantation dose of the second conductive type semiconductor drift region 21 is 1E12cm -2 -2E13cm -2 ;

第二步:采用光刻和离子注入工艺,在第一种导电类型半导体衬底1中注入第一种导电类型半导体杂质,退火扩散形成第一种导电类型半导体体区31,所述第一种导电类型半导体体区31的注入剂量为1E12cm-2~5E13cm-2Step 2: Using photolithography and ion implantation techniques, implanting semiconductor impurities of the first conductivity type into the semiconductor substrate 1 of the first conductivity type, and annealing and diffusing to form the semiconductor body region 31 of the first conductivity type. The implantation dose of the conductivity type semiconductor body region 31 is 1E12cm -2 ~ 5E13cm -2 ;

第三步:在第二种导电类型半导体漂移区21上表面形成场氧化层42;Step 3: Forming a field oxide layer 42 on the upper surface of the semiconductor drift region 21 of the second conductivity type;

第四步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中注入第一种导电类型半导体杂质,形成第一种导电类型半导体体区埋层33和第一种导电类型半导体降场层34,所述第一种导电类型半导体杂质的注入剂量为1E11cm-2~2E13cm-2Step 4: Using photolithography and ion implantation process, implant semiconductor impurities of the first conductivity type into the drift region 21 of the semiconductor of the second conductivity type to form the buried layer 33 of the semiconductor body region of the first conductivity type and the first conductivity type semiconductor The semiconductor drop-off layer 34, the implantation dose of the semiconductor impurity of the first conductivity type is 1E11cm -2 ~ 2E13cm -2 ;

第五步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中注入第二种导电类型半导体杂质,快速热退火形成分段的第二种导电类型半导体重掺杂层,所述第二种导电类型半导体重掺杂层的注入剂量为1E11cm-2~2E13cm-2Step 5: using photolithography and ion implantation processes, implanting second conductivity type semiconductor impurities into the second conductivity type semiconductor drift region 21, rapid thermal annealing to form segmented second conductivity type semiconductor heavily doped layers, The implant dose of the heavily doped semiconductor layer of the second conductivity type is 1E11cm -2 ~ 2E13cm -2 ;

第六步:在部分第二种导电类型半导体源区22的上表面、第一种导电类型半导体体区31的上表面和第二种导电类型半导体漂移区21的上表面形成栅氧化层41,所述栅氧化层41的厚度为7nm~100nm;Step 6: Form a gate oxide layer 41 on the upper surface of part of the second conductivity type semiconductor source region 22, the upper surface of the first conductivity type semiconductor body region 31 and the upper surface of the second conductivity type semiconductor drift region 21, The thickness of the gate oxide layer 41 is 7nm-100nm;

第七步:在栅氧化层41的上表面和部分场氧化层42的上表面形成多晶硅栅电极51,所述多晶硅栅极51的方块电阻值为10~40欧姆/方块;Step 7: Forming a polysilicon gate electrode 51 on the upper surface of the gate oxide layer 41 and the upper surface of the partial field oxide layer 42, the square resistance value of the polysilicon gate 51 is 10-40 ohms/square;

第八步:采用光刻和离子注入工艺,在第二种导电类型半导体漂移区21中形成第二种导电类型半导体漏区23,在第一种导电类型半导体体区31中形成相互独立的第二种导电类型半导体源区22、第一种导电类型半导体体接触区32,所述第二种导电类型半导体漏区23、第二种导电类型半导体源22、第一种导电类型半导体体接触区32的注入剂量为1E13cm-2~2E16cm-2Step 8: Form the second conductivity type semiconductor drain region 23 in the second conductivity type semiconductor drift region 21 by using photolithography and ion implantation technology, and form mutually independent first conductivity type semiconductor body regions 31 The second conductivity type semiconductor source region 22, the first conductivity type semiconductor body contact region 32, the second conductivity type semiconductor drain region 23, the second conductivity type semiconductor source 22, the first conductivity type semiconductor body contact region The injection dose of 32 is 1E13cm -2 ~ 2E16cm -2 ;

第九步:在部分第二种导电类型半导体源22的上表面、多晶硅栅极51的上表面、氧化层42的上表面和部分第二种导电类型半导体漏区23的上表面淀积形成金属前介质43;Step 9: Deposit and form metal on the upper surface of part of the second conductivity type semiconductor source 22 , the upper surface of the polysilicon gate 51 , the upper surface of the oxide layer 42 and the upper surface of part of the second conductivity type semiconductor drain region 23 pre-medium 43;

第十步:在第一种导电类型半导体体接触区32的上表面和第二种导电类型半导体源22的上表面形成源极金属52,在第二种导电类型半导体漏区23的上表面形成漏极金属53,源极金属52和漏极金属53与金属前介质43连接并在金属前介质43的上表面延伸形成场板。Step 10: Form the source metal 52 on the upper surface of the first conductivity type semiconductor body contact region 32 and the upper surface of the second conductivity type semiconductor source 22, and form the upper surface of the second conductivity type semiconductor drain region 23 The drain metal 53 , the source metal 52 and the drain metal 53 are connected to the pre-metal dielectric 43 and extend on the upper surface of the pre-metal dielectric 43 to form a field plate.

其中,第二种导电类型半导体漂移区21还可以通过外延工艺形成;场氧化层42还可以在第一种导电类型半导体降场层34之后形成,可以利用场氧化层42的退火过程,对第一种导电类型半导体降场层34进行退火处理,同时器件可以集成在SOI衬底上。Wherein, the drift region 21 of the semiconductor of the second conductivity type can also be formed by an epitaxial process; the field oxide layer 42 can also be formed after the field drop layer 34 of the semiconductor of the first conductivity type, and the annealing process of the field oxide layer 42 can be used to The field drop layer 34 of a conductivity type semiconductor is annealed, and the device can be integrated on the SOI substrate at the same time.

本发明通过离子注入工艺在第二种导电类型半导体漂移区中形成第一种导电类型半导体降场层,并通过离子注入工艺在第一种导电类型半导体降场层上方形成第二种导电类型半导体重掺杂层。开态时,第二种导电类型半导体重掺杂层为器件提供一个低阻的表面导电通道,降低了器件的导通电阻和功耗。同时,分段的第二种导电类型半导体重掺杂层降低器件源端电场,避免强场效应,在器件表面引入多个电场尖峰,优化器件表面电场,从而提高器件的击穿电压。与传统横向高压功率器件相比,本发明提供的高压器件在相同芯片面积的情况下具有更小的导通电阻(或在相同的导通能力的情况下具有更小的芯片面积)。而且,本发明还提供了一种高压器件的制造技术,其工艺较为简单,成本较低。In the present invention, an ion implantation process is used to form a first conductive type semiconductor drop field layer in the second conductive type semiconductor drift region, and an ion implantation process is used to form a second conductive type semiconductor above the first conductive type semiconductor drop field layer. heavily doped layer. In the on-state, the heavily doped layer of the second conductivity type semiconductor provides a low-resistance surface conduction channel for the device, reducing the on-resistance and power consumption of the device. At the same time, the segmented second conductivity type semiconductor heavily doped layer reduces the electric field at the source end of the device, avoids strong field effects, introduces multiple electric field peaks on the device surface, optimizes the device surface electric field, and thereby increases the breakdown voltage of the device. Compared with traditional lateral high-voltage power devices, the high-voltage device provided by the present invention has smaller on-resistance (or smaller chip area under the same conduction capability) under the same chip area. Moreover, the invention also provides a manufacturing technology of a high-voltage device, the process of which is relatively simple and the cost is low.

本发明提供的方法中,第四步和第五步为关键特征步骤。In the method provided by the present invention, the fourth step and the fifth step are key characteristic steps.

实施例1:Example 1:

本例的采用工艺为,第二种导电类型半导体重掺杂层61~6i具有多个离子注入窗口,窗口的大小相同,而窗口的间距不同,随着向第二种导电类型半导体漏区23靠近,注入窗口间距逐渐减小,如图12所示。图13为第二种导电类型半导体杂质注入后的器件结构剖面图,图中第二种导电类型半导体杂质注入后形成分段的第二种导电类型半导体重掺杂层61~6i。同时,场氧化层42在第一种导电类型半导体降场层34的离子注入工艺之前形成,先形成场氧化层42,场氧化层42的退火过程不会影响后面的离子注入。分段的第二种导电类型半导体重掺杂层61~6i,开态时为高压器件提供一个低阻的表面,降低器件的比导通电阻,关态时降低器件的源端电场,避免器件提前发生击穿,提高器件的击穿电压。The process adopted in this example is that the heavily doped layers 6 1 to 6 i of the semiconductor of the second conductivity type have a plurality of ion implantation windows, the sizes of the windows are the same, and the intervals of the windows are different. As the region 23 approaches, the distance between the injection windows decreases gradually, as shown in FIG. 12 . FIG. 13 is a cross-sectional view of the device structure after impurity implantation of the semiconductor of the second conductivity type. In the figure, heavily doped layers 6 1 to 6 i of the semiconductor of the second conductivity type are formed after the impurity implantation of the semiconductor of the second conductivity type. At the same time, the field oxide layer 42 is formed before the ion implantation process of the first conductivity type semiconductor field drop layer 34 , the field oxide layer 42 is formed first, and the annealing process of the field oxide layer 42 will not affect the subsequent ion implantation. The segmented second conductivity type semiconductor heavily doped layers 6 1 to 6 i provide a low-resistance surface for the high-voltage device in the on state, reduce the specific on-resistance of the device, and reduce the source end electric field of the device in the off state, Avoid premature breakdown of the device and increase the breakdown voltage of the device.

实施例2:Example 2:

本例的采用工艺为,第二种导电类型半导体重掺杂层61~6i具有多个离子注入窗口,窗口的大小不同,而窗口的间距相同,随着向第二种导电类型半导体漏区23靠近,注入窗口大小逐渐增大,如图14所示。图15为第二种导电类型半导体杂质注入后的器件结构剖面图,图中第二种导电类型半导体杂质注入后形成分段的第二种导电类型半导体重掺杂层61~6i。同时,场氧化层42在第一种导电类型半导体降场层34的离子注入工艺之前形成,先形成场氧化层42,场氧化层42的退火过程不会影响后面的离子注入。分段的第二种导电类型半导体重掺杂层61~6i,开态时为高压器件提供一个低阻的表面,降低器件的比导通电阻,关态时降低器件的源端电场,避免器件提前发生击穿,提高器件的击穿电压。本例工艺流程形成的高压器件,其工作原理与实施例1相同。The process used in this example is that the heavily doped layers 6 1 to 6 i of the semiconductor of the second conductivity type have multiple ion implantation windows with different sizes and the same spacing between the windows. As the region 23 approaches, the size of the injection window gradually increases, as shown in FIG. 14 . 15 is a cross-sectional view of the device structure after implantation of semiconductor impurities of the second conductivity type. In the figure, heavily doped layers 6 1 - 6 i of the second conductivity type semiconductors are formed after the implantation of semiconductor impurities of the second conductivity type. At the same time, the field oxide layer 42 is formed before the ion implantation process of the first conductivity type semiconductor field drop layer 34 , the field oxide layer 42 is formed first, and the annealing process of the field oxide layer 42 will not affect the subsequent ion implantation. The segmented second conductivity type semiconductor heavily doped layers 6 1 to 6 i provide a low-resistance surface for the high-voltage device in the on state, reduce the specific on-resistance of the device, and reduce the source end electric field of the device in the off state, Avoid premature breakdown of the device and increase the breakdown voltage of the device. The working principle of the high-voltage device formed by the process flow of this example is the same as that of Example 1.

由上述说明可得,本发明通过光刻和离子注入工艺在第二种导电类型半导体漂移区21中形成第一种导电类型半导体降场层34,通过光刻和离子注入工艺,在第二种导电类型半导体漂移区21的表面形成的第二种导电类型半导体重掺杂层61~6i。开态时,第二种导电类型半导体重掺杂层61~6i为器件提供一个表面低阻导电通道,减小了器件表面的电阻率,从而极大地降低了器件的导通电阻。关态时,线性掺杂的第二种导电类型半导体重掺杂层61~6i优化器件的表面电场,避免源端电场过大,防止强场效应导致器件提前击穿,使得新型高压器件具有较高的击穿电压。因此,与传统高压器件相比,本发明提供的高压器件在相同芯片面积的情况下具有更小的导通电阻(或在相同的导通能力的情况下具有更小的芯片面积)。It can be obtained from the above description that the present invention forms the first conductivity type semiconductor drop field layer 34 in the second conductivity type semiconductor drift region 21 through photolithography and ion implantation processes, and forms the second conductivity type semiconductor drop layer 34 through photolithography and ion implantation processes The second conductive type semiconductor heavily doped layers 6 1 -6 i are formed on the surface of the conductive type semiconductor drift region 21 . In the on state, the heavily doped layers 6 1 - 6 i of the second conductivity type semiconductor provide a surface low-resistance conduction channel for the device, which reduces the resistivity of the device surface, thereby greatly reducing the on-resistance of the device. In the off state, the linearly doped second conductivity type semiconductor heavily doped layer 6 1 ~ 6 i optimizes the surface electric field of the device, avoids the excessive electric field at the source end, prevents the strong field effect from causing the device to break down early, and makes the new high-voltage device Has a higher breakdown voltage. Therefore, compared with traditional high-voltage devices, the high-voltage device provided by the present invention has smaller on-resistance (or smaller chip area under the same conduction capability) in the case of the same chip area.

Claims (3)

1. a high tension apparatus, its structure cell comprises the first conductive type semiconductor substrate (1), the second conduction type halfConductor drift region (21), the second conductive type semiconductor source region (22), the second conductive type semiconductor drain region (23),One conductive type semiconductor tagma (31), the first conductive type semiconductor body contact zone (32), the first conduction type halfConductor tagma buried regions (33), the first conductive type semiconductor fall layer (34), a gate oxide (41), field oxide (42),Medium (43), polygate electrodes (51), source metal (52) and drain metal (53) before metal, described the second conductionType semiconductor drift region (21), described the first conductive type semiconductor tagma buried regions (33) is arranged on the first conduction typeThe lower surface of semiconductor body (31), a layer (34) and the second conduction type half fall in described the first conductive type semiconductorConductor drain region (23) is arranged in the second conductive type semiconductor drift region (21), described the second conductive type semiconductorSource region (22) and the first conductive type semiconductor body contact zone (32) are arranged on the first conductive type semiconductor tagma (31)In and separate, described field oxide (42) is arranged on the upper surface of the second conductive type semiconductor drift region (21),Described gate oxide (41) is arranged on upper surface, the first conduction class in part the second conductive type semiconductor source region (22)The upper surface of the upper surface of type semiconductor body (31) and the second conductive type semiconductor drift region (21) and field oxide(42) connect, described polygate electrodes (51) is arranged on upper surface and the part field oxide (42) of gate oxide (41)Upper surface, described source metal (52) is arranged on upper surface, the portion of the first conductive type semiconductor body contact zone (32)Divide the upper surface in the second conductive type semiconductor source region (22), described drain metal (53) is arranged on part the second conductionThe upper surface in type semiconductor drain region (23), before described metal, medium (43) is filled in source metal (52) and drain metal(53), between, source metal (52) and drain metal (53) medium (43) upper surface before metal extends to form field plate,It is characterized in that, also comprise the second conductive type semiconductor heavily doped layer, described the second conductive type semiconductor heavily doped layerForm and be arranged on the first conductive type semiconductor by the second conductiving type semiconductor area that is divided into multistage and fall a layer (34)And between field oxide (42); Also comprise the second conductive type semiconductor buried regions (24), described the second conduction type is partly ledBody buried regions (24) is arranged in the second conductive type semiconductor drift region (21) and is positioned at the first conductive type semiconductor and fallsThe lower surface of field layer (34); Described the first conductive type semiconductor tagma (31) and the first conductive type semiconductor tagmaBuried regions (33) is arranged in the second conductive type semiconductor drift region (21).

2. a kind of high tension apparatus according to claim 1, is characterized in that, described the second conductive type semiconductor driftDistrict (21) is arranged on the upper surface of the first conductive type semiconductor substrate (1).

3. a kind of high tension apparatus according to claim 2, is characterized in that, also comprises SOI substrate (2), described SOISubstrate (2) be arranged on the first conductive type semiconductor substrate (1) and the second conductive type semiconductor drift region (21) itBetween and be connected with the first conductive type semiconductor substrate (1) and the second conductive type semiconductor drift region (21) respectively.

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