CN103514103B - Data protection method, memory controller and memory storage device - Google Patents
- ️Wed Sep 28 2016
CN103514103B - Data protection method, memory controller and memory storage device - Google Patents
Data protection method, memory controller and memory storage device Download PDFInfo
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- CN103514103B CN103514103B CN201210212251.7A CN201210212251A CN103514103B CN 103514103 B CN103514103 B CN 103514103B CN 201210212251 A CN201210212251 A CN 201210212251A CN 103514103 B CN103514103 B CN 103514103B Authority
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Abstract
A data protection method is used for a rewritable nonvolatile memory module with a plurality of physical blocks. The data protection method comprises the following steps: when the rewritable nonvolatile memory module is powered on, acquiring the power-off time from last power-off to the current power-on; when the power-off time is larger than a time critical value, judging whether the physical block meets the updating condition or not according to the block information; and executing an updating program on the physical blocks meeting the updating condition. The updating procedure is used for reading the data stored in the physical blocks and rewriting the data into one of the physical blocks. Therefore, the method can prevent the data in the physical block from being lost easily, and further prolong the service life of the rewritable nonvolatile memory module.
Description
技术领域 technical field
本发明是有关于一种数据保护方法，且特别是有关于一种应用于可复写式非易失性存储器的数据保护方法，以及使用此方法的存储器控制器与存储器储存装置。The present invention relates to a data protection method, and in particular to a data protection method applied to a rewritable non-volatile memory, as well as a memory controller and a memory storage device using the method.
背景技术 Background technique
数字相机、移动电话与MP3播放器在这几年来的成长十分迅速，使得消费者对储存媒体的需求也急速增加。由于可复写式非易失性存储器模块(例如，闪存)具有数据非易失性、省电、体积小，以及无机械结构等特性，所以非常适合内建于上述所举例的各种可携式多媒体装置中。Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (such as flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable devices such as the above examples. in the multimedia device.
一般来说，一个可复写式非易失性存储器模块会包括多个物理区块。而每个物理区块会有一个抹除次数的上限，若超过此上限，则表示此物理区块所储存的数据容易遗失，或者是无法保证此物理区块所储存的数据能保存很久的时间。当储存在物理区块中的数据无法被保存时，便表示可复写式非易失性存储器模块的使用寿命快要结束。因此，如何保护抹除次数已超过上限的物理区块所储存的数据以增加使用寿命，为本领域技术人员所关心的议题。Generally, a rewritable non-volatile memory module includes multiple physical blocks. And each physical block has an upper limit of erasing times. If the upper limit is exceeded, it means that the data stored in this physical block is easily lost, or it cannot be guaranteed that the data stored in this physical block can be stored for a long time . When the data stored in the physical block cannot be saved, it means that the service life of the rewritable non-volatile memory module is about to end. Therefore, how to protect the data stored in the physical blocks whose erasing times have exceeded the upper limit so as to increase the service life is an issue concerned by those skilled in the art.
发明内容 Contents of the invention
本发明提供一种数据保护方法，以及使用此方法的存储器控制器与存储器储存装置，其可以增加可复写式非易失性存储器模块的使用寿命。The invention provides a data protection method, a memory controller and a memory storage device using the method, which can increase the service life of the rewritable non-volatile memory module.
本发明一范例实施例提出一种数据保护方法，用于控制一可复写式非易失性存储器模块，而此可复写式非易失性存储器模块包括多个物理区块。此数据保护方法包括：当可复写式非易失性存储器模块被给电时，取得距离可复写式非易失性存储器模块上一次断电的第一时间到目前被给电的第二时间之间的断电时间；以及，当此断电时间大于第一时间临界值时，根据每一个物理区块的区块信息来判断各物理区块是否符合更新条件；对符合更新条件的物理区块执行一更新程序。上述的更新程序是用以读取被执行更新程序的物理区块所储存的第一数据并将第一数据重新写入至上述多个物理区块的其中之一。An exemplary embodiment of the present invention provides a data protection method for controlling a rewritable nonvolatile memory module, and the rewritable nonvolatile memory module includes a plurality of physical blocks. The data protection method includes: when the rewritable non-volatile memory module is powered on, obtaining the time between the first time when the rewritable non-volatile memory module was powered off last time and the second time when it is currently powered on and, when the power-off time is greater than the first time critical value, judge whether each physical block meets the update condition according to the block information of each physical block; for the physical block that meets the update condition Execute an update procedure. The above update program is used to read the first data stored in the physical block on which the update program is executed and rewrite the first data to one of the above multiple physical blocks.
在一范例实施例中，上述的区块信息为物理区块的抹除次数。上述根据每一个物理区块的区块信息来判断各物理区块是否符合更新条件的步骤包括：判断抹除次数大于一个抹除临界值的物理区块符合更新条件。In an exemplary embodiment, the above-mentioned block information is the erasure count of the physical block. The above-mentioned step of judging whether each physical block meets the update condition according to the block information of each physical block includes: judging that the physical block whose erasure times are greater than an erasure threshold meets the update condition.
在一范例实施例中，上述的数据保护方法还包括：当上述的断电时间大于第二时间临界值时，判断所有的物理区块皆符合更新条件。In an exemplary embodiment, the above-mentioned data protection method further includes: when the above-mentioned power-off time is greater than a second time threshold, judging that all the physical blocks meet the updating conditions.
在一范例实施例中，上述的区块信息为一个错误更正码。上述每一个物理区块包括多个物理页面。而每一个物理页面包括一数据位区以及一冗余位区，且冗余位区中记录有除错更正码。上述根据每一个物理区块的区块信息来判断各物理区块是否符合更新条件的步骤包括：根据数据位区所储存的数据以及错误更正码，判断对于每一个物理页面是否发生一个可还原错误，此可还原错误表示数据位区所储存的数据发生错误，但可以根据错误更正码来更正数据位区所储存的数据；以及，若发生上述的可还原错误，则判断发生可还原错误的物理页面所属的物理区块符合更新条件。In an exemplary embodiment, the above block information is an error correction code. Each of the above physical blocks includes multiple physical pages. And each physical page includes a data bit area and a redundant bit area, and the error correction code is recorded in the redundant bit area. The above-mentioned step of judging whether each physical block meets the update condition according to the block information of each physical block includes: judging whether a recoverable error occurs for each physical page according to the data stored in the data bit area and the error correction code , this recoverable error indicates that the data stored in the data bit area has an error, but the data stored in the data bit area can be corrected according to the error correction code; The physical block to which the page belongs is eligible for update.
在一范例实施例中，上述取得断电时间的步骤包括：当可复写式非易失性存储器模块被断电时，设定一计数器开始更新所记录的值；以及，当可复写式非易失性存储器模块被给电时，根据计数器所记录的值取得上述的断电时间。In an exemplary embodiment, the step of obtaining the power-off time includes: when the rewritable non-volatile memory module is powered off, setting a counter to start updating the recorded value; and, when the rewritable non-volatile memory module is powered off, When the volatile memory module is powered on, the above-mentioned power-off time is obtained according to the value recorded by the counter.
在一范例实施例中，上述取得断电时间的步骤包括：当可复写式非易失性存储器模块被给电时，从一个断电时间计算单元取得上述的断电时间。In an exemplary embodiment, the step of obtaining the power-off time includes: obtaining the above-mentioned power-off time from a power-off time calculation unit when the rewritable non-volatile memory module is powered on.
以另外一个角度来说，本发明一范例实施例提出一种存储器储存装置，包括连接器、可复写式非易失性存储器模块与存储器控制器。其中，连接器是用以电性连接至一主机系统，而可复写式非易失性存储器模块包括多个物理页面。存储器控制器则是电性连接至连接器与可复写式非易失性存储器模块。当存储器储存装置被给电时，存储器控制器会取得距离存储器储存装置上一次断电的第一时间到目前被给电的第二时间之间的一断电时间。当断电时间大于第一时间临界值时，存储器控制器用以根据每一个物理区块的区块信息来判断每一个物理区块是否符合更新条件。存储器控制器用以对符合更新条件的物理区块执行一更新程序。此更新程序是用以读取被执行更新程序的物理区块所储存的第一数据并将第一数据重新写入至上述的物理区块的其中之一。From another perspective, an exemplary embodiment of the present invention provides a memory storage device including a connector, a rewritable non-volatile memory module, and a memory controller. Wherein, the connector is used to electrically connect to a host system, and the rewritable non-volatile memory module includes multiple physical pages. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module. When the memory storage device is powered on, the memory controller obtains a power-off time between the first time when the memory storage device was powered off last time and the second time when it is currently powered on. When the power-off time is greater than the first time threshold, the memory controller is used to determine whether each physical block meets the update condition according to the block information of each physical block. The memory controller is used for executing an update program on the physical blocks meeting the update conditions. The update program is used to read the first data stored in the physical block on which the update program is executed and rewrite the first data into one of the above physical blocks.
在一范例实施例中，上述的区块信息为抹除次数。存储器控制器还用以判断抹除次数大于一个抹除临界值的物理区块符合更新条件。In an exemplary embodiment, the above block information is erasure times. The memory controller is also used for judging that the physical blocks whose erasing times are greater than an erasing threshold meet the updating conditions.
在一范例实施例中，当断电时间大于第二时间临界值时，上述的存储器控制器会判断所有的物理区块皆符合更新条件。In an exemplary embodiment, when the power-off time is greater than the second time threshold, the above-mentioned memory controller will determine that all the physical blocks meet the updating conditions.
在一范例实施例中，上述的区块信息为错误更正码。上述每一个物理区块包括多个物理页面。而每一个物理页面包括数据位区以及冗余位区，冗余位区中记录有上述的除错更正码。存储器控制器会根据数据位区所储存的数据以及错误更正码，判断每一个物理页面是否发生一可还原错误。此可还原错误表示数据位区所储存的数据发生错误，但可以根据错误更正码来更正数据位区所储存的数据。若发生可还原错误，存储器控制器会判断发生可还原错误的物理页面所属的物理区块符合更新条件。In an exemplary embodiment, the above-mentioned block information is an error correction code. Each of the above physical blocks includes multiple physical pages. And each physical page includes a data bit area and a redundant bit area, and the above-mentioned error correction code is recorded in the redundant bit area. The memory controller judges whether a recoverable error occurs in each physical page according to the data stored in the data bit area and the error correction code. The recoverable error indicates that the data stored in the data bit area is wrong, but the data stored in the data bit area can be corrected according to the error correction code. If a recoverable error occurs, the memory controller will determine that the physical block to which the physical page where the recoverable error occurs meets the update condition.
在一范例实施例中，上述的存储器储存装置还包括计数器与电池。计数器是电性连接至上述的存储器控制器。电池则提供一电源给此计数器。当存储器储存装置被断电时，存储器控制器设定计数器开始更新所记录的值。当存储器储存装置被给电时，存储器控制器根据计数器所记录的值取得上述的断电时间。In an exemplary embodiment, the above-mentioned memory storage device further includes a counter and a battery. The counter is electrically connected to the above-mentioned memory controller. The battery provides a power supply to the counter. When the memory storage device is powered off, the memory controller sets the counter to start updating the recorded value. When the memory storage device is powered on, the memory controller obtains the aforementioned power-off time according to the value recorded by the counter.
在一范例实施例中，当存储器储存装置被给电时，存储器控制器会从一个断电时间计算单元取得上述的断电时间。In an exemplary embodiment, when the memory storage device is powered on, the memory controller obtains the aforementioned power-off time from a power-off time calculation unit.
以另外一个角度来说，本发明一范例实施例提出一种存储器控制器，包括主机接口、存储器接口与存储器管理电路。其中，主机接口是用以电性连接至一主机系统。存储器接口是电性连接至一可复写式非易失性存储器模块，而此可复写式非易失性存储器模块包括多个物理区块。存储器管理电路是电性连接至上述的主机接口与存储器接口。当可复写式非易失性存储器模块被给电时，存储器管理电路会取得距离可复写式非易失性存储器模块上一次断电的第一时间到目前被给电的第二时间之间的一断电时间。当断电时间大于第一时间临界值时，存储器管理电路用以根据每一个物理区块的区块信息来判断每一个物理区块是否符合更新条件。存储器管理电用以对符合更新条件的物理区块执行一更新程序。此更新程序是用以读取被执行更新程序的物理区块所储存的第一数据并将第一数据重新写入至物理区块的其中之一。From another perspective, an exemplary embodiment of the present invention provides a memory controller including a host interface, a memory interface and a memory management circuit. Wherein, the host interface is used to electrically connect to a host system. The memory interface is electrically connected to a rewritable nonvolatile memory module, and the rewritable nonvolatile memory module includes a plurality of physical blocks. The memory management circuit is electrically connected to the above-mentioned host interface and memory interface. When the rewritable non-volatile memory module is powered on, the memory management circuit will obtain the time between the first time when the rewritable non-volatile memory module was powered off last time and the second time when it is currently powered on. A power outage time. When the power-off time is greater than the first time critical value, the memory management circuit is used for judging whether each physical block meets the update condition according to the block information of each physical block. The memory management circuit is used for executing an updating process on the physical blocks meeting the updating conditions. The update program is used for reading the first data stored in the physical block on which the update program is executed and rewriting the first data into the physical block.
在一范例实施例中，上述的区块信息为抹除次数。存储器管理电路还用以判断抹除次数大于一抹除临界值的物理区块符合更新条件。In an exemplary embodiment, the above block information is erasure times. The memory management circuit is also used for judging that the physical blocks whose erasing times are greater than an erasing threshold meet the updating conditions.
在一范例实施例中，当断电时间大于第二时间临界值时，存储器管理电路会判断所有的物理区块符合更新条件。In an exemplary embodiment, when the power-off time is greater than the second time threshold, the memory management circuit determines that all the physical blocks meet the updating conditions.
在一范例实施例中，上述的区块信息为错误更正码。每一个物理区块包括多个物理页面。而每一个物理页面包括数据位区以及冗余位区，冗余位区记录有上述的除错更正码。存储器管理电路会根据数据位区所储存的数据以及上述的错误更正码，判断每一个物理页面是否发生一可还原错误。此可还原错误表示数据位区所储存的数据发生错误，但可以根据错误更正码来更正数据位区所储存的数据。若发生可还原错误，存储器管理电路会判断发生可还原错误的物理页面所属的物理区块符合更新条件。In an exemplary embodiment, the above-mentioned block information is an error correction code. Each physical block includes multiple physical pages. And each physical page includes a data bit area and a redundant bit area, and the redundant bit area records the above-mentioned error correction code. The memory management circuit judges whether a recoverable error occurs in each physical page according to the data stored in the data bit area and the above error correction code. The recoverable error indicates that the data stored in the data bit area is wrong, but the data stored in the data bit area can be corrected according to the error correction code. If a recoverable error occurs, the memory management circuit will determine that the physical block to which the physical page where the recoverable error occurs meets the update condition.
在一范例实施例中，当可复写式非易失性存储器模块被断电时，存储器管理电路会设定一计数器开始更新所记录的值。当可复写式非易失性存储器模块被给电时，存储器管理电路会根据计数器所记录的值以取得断电时间。In an exemplary embodiment, when the rewritable non-volatile memory module is powered off, the memory management circuit sets a counter and starts to update the recorded value. When the rewritable non-volatile memory module is powered on, the memory management circuit obtains the power-off time according to the value recorded by the counter.
在一范例实施例中，当可复写式非易失性存储器模块被给电时，存储器管理电路会从一个断电时间计算单元取得上述的断电时间。In an exemplary embodiment, when the rewritable non-volatile memory module is powered on, the memory management circuit obtains the aforementioned power-off time from a power-off time calculation unit.
基于上述，本发明的范例实施例所提出的数据保护方法、存储器控制器与存储器储存装置，可以在存储器储存装置被重新供电以后，更新其中部分或全部的物理区块。如此一来，能持续地保存物理区块中所储存的数据，进而增加存储器储存装置的使用寿命。Based on the above, the data protection method, the memory controller and the memory storage device proposed by the exemplary embodiments of the present invention can update some or all of the physical blocks in the memory storage device after it is powered on again. In this way, the data stored in the physical block can be continuously saved, thereby increasing the service life of the memory storage device.
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
附图说明 Description of drawings
图1A是根据一范例实施例所绘示的主机系统与存储器储存装置。FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment.
图1B是根据一范例实施例所绘示的计算机、输入/输出装置与存储器储存装置的示意图。FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment.
图1C是根据一范例实施例所绘示的主机系统与存储器储存装置的示意图。FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.
图2是绘示图1A所示的存储器储存装置的概要方块图。FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .
图3是根据一范例实施例所绘示的存储器控制器的概要方块图。FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment.
图4与图5是根据一范例实施例说明对一物理区块执行更新程序的范例示意图。FIG. 4 and FIG. 5 are exemplary diagrams illustrating an update procedure for a physical block according to an exemplary embodiment.
图6是根据一范例实施例说明利用错误更正码来判断数据是否发生错误的范例示意图。FIG. 6 is a schematic diagram illustrating an example of using an error correction code to determine whether an error occurs in data according to an example embodiment.
图7是根据一范例实施例说明数据保护方法的流程图。FIG. 7 is a flowchart illustrating a data protection method according to an exemplary embodiment.
[主要元件标号说明][Description of main component labels]
1000：主机系统 1100：计算机1000: host system 1100: computer
1102：微处理器 1104：随机存取存储器1102: Microprocessor 1104: Random Access Memory
1106：输入/输出装置 1108：系统总线1106: Input/Output Device 1108: System Bus
1110：数据传输接口 1202：鼠标1110: Data transmission interface 1202: Mouse
1204：键盘 1206：显示器1204: keyboard 1206: monitor
1208：打印机 1212：随身盘1208: Printer 1212: Pen drive
1214：存储卡 1216：固态硬盘1214: memory card 1216: solid state drive
1310：数字相机 1312：SD卡1310: digital camera 1312: SD card
1314：MMC卡 1316：存储棒1314: MMC card 1316: memory stick
1318：CF卡 1320：嵌入式储存装置1318: CF card 1320: Embedded storage device
100：存储器储存装置 102：连接器100: memory storage device 102: connector
104：存储器控制器 106：可复写式非易失性存储器模块104: Memory controller 106: Rewritable non-volatile memory module
108：计数器 109：电池108: Counter 109: Battery
110：断电时间计算单元 304(0)～304(R)：物理区块110: Power-off time calculation unit 304(0)~304(R): Physical block
402：第一数据 602(0)～602(A)：物理页面402: First data 602(0)~602(A): Physical page
604(0)～604(A)：数据位区 606(0)～606(A)：冗余位区604(0)～604(A): Data bit area 606(0)～606(A): Redundant bit area
620：数据 640：错误更正码620: Data 640: Error Correction Code
S702、S704、S706、S708、S710、S712：数据保护方法的步骤S702, S704, S706, S708, S710, S712: steps of the data protection method
具体实施方式 detailed description
一般而言，存储器储存装置(亦称，存储器储存系统)包括可复写式非易失性存储器模块与控制器(亦称，控制电路)。通常存储器储存装置是与主机系统一起使用，以使主机系统可将数据写入至存储器储存装置或从存储器储存装置中读取数据。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.
图1A是根据一范例实施例所绘示的主机系统与存储器储存装置。FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment.
请参照图1A，主机系统1000一般包括计算机1100与输入/输出(input/out put,I/O)装置1106。计算机1100包括微处理器1102、随机存取存储器(random access memory,RAM)1104、系统总线1108与数据传输接口1110。输入/输出装置1106包括如图1B的鼠标1202、键盘1204、显示器1206与打印机1208。必须了解的是，图1B所示的装置非限制输入/输出装置1106，输入/输出装置1106可还包括其它装置。Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (input/output, I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.
在本发明实施例中，存储器储存装置100是通过数据传输接口1110与主机系统1000的其它元件电性连接。通过微处理器1102、随机存取存储器1104与输入/输出装置1106的运作可将数据写入至存储器储存装置100或从存储器储存装置100中读取数据。例如，存储器储存装置100可以是如图1B所示的随身盘1212、存储卡1214或固态硬盘(Solid State Drive,SSD)1216等的可复写式非易失性存储器储存装置。In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into the memory storage device 100 or read from the memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a pen drive 1212 , a memory card 1214 or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B .
一般而言，主机系统1000为可实质地与存储器储存装置100配合以储存数据的任意系统。虽然在本范例实施例中，主机系统1000是以计算机系统来作说明，然而，在本发明另一范例实施例中主机系统1000可以是数字相机、摄影机、通信装置、音频播放器或视频播放器等系统。例如，在主机系统为数字相机(摄影机)1310时，可复写式非易失性存储器储存装置则为其所使用的SD卡1312、MMC卡1314、存储棒(memory stick)1316、CF卡1318或嵌入式储存装置1320(如图1C所示)。嵌入式储存装置1320包括嵌入式多媒体卡(Embedded MMC,eMMC)。值得一提的是，嵌入式多媒体卡是直接电性连接于主机系统的基板上。In general, the host system 1000 is any system that can substantially cooperate with the memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is illustrated as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is an SD card 1312, an MMC card 1314, a storage stick (memory stick) 1316, a CF card 1318 or The embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.
图2是绘示图1A所示的存储器储存装置的概要方块图。FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .
请参照图2，存储器储存装置100包括连接器102、存储器控制器104、可复写式非易失性存储器模块106、以及断电时间计算单元110。Referring to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 , a rewritable non-volatile memory module 106 , and a power-off time calculation unit 110 .
在本范例实施例中，连接器102是相容于序列先进附件(Serial AdvancedTechnology Attachment,SATA)标准。然而，必须了解的是，本发明不限于此，连接器102亦可以是符合并列先进附件(Parallel Advanced TechnologyAttachment,PATA)标准、电气和电子工程师协会(Institute of Electricaland Eletronic Engineers,IEEE)1394标准、高速周边零件连接接口(Peripheral Component Interconnect Express,PCI Express)标准、通用序列总线(Universal Serial Bus,USB)标准、安全数字(Secure Digital,SD)接口标准、超高速一代(Ultra High Speed-I，UHS-I)接口标准、超高速二代(Ultra High Speed-II，UHS-II)接口标准、存储棒(Memory Stick,MS)接口标准、多媒体储存卡(Multi Media Card,MMC)接口标准、嵌入式多媒体储存卡(Embedded Multimedia Card，eMMC)接口标准、通用闪存(UniversalFlash Storage，UFS)接口标准、小型快闪(Compact Flash,CF)接口标准、集成式驱动电子接口(Integrated Device Elect ronics,IDE)标准或其它适合的标准。In this exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also be a high-speed connector conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, Secure Digital (Secure Digital, SD) interface standard, Ultra High Speed-I (UHS- I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi Media Card (MMC) interface standard, embedded multimedia Memory card (Embedded Multimedia Card, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Compact Flash (Compact Flash, CF) interface standard, Integrated Device Electronics (IDE) standard or other suitable standards.
存储器控制器104用以执行以硬件型式或固件型式实作的多个逻辑门或控制指令，并且根据主机系统1000的指令在可复写式非易失性存储器模块106中进行数据的写入、读取与抹除等运作。The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000. Fetch and erase operations.
可复写式非易失性存储器模块106是电性连接至存储器控制器104，并且用以储存主机系统1000所写入的数据。可复写式非易失性存储器模块106具有物理区块304(0)～304(R)。例如，物理区块304(0)～304(R)可属于同一个存储器晶粒(die)或者属于不同的存储器晶粒。每一物理区块分别具有多个物理页面，并且每一物理页面具有至少一物理扇区，其中属于同一个物理区块的物理页面可被独立地写入且被同时地抹除。例如，每一物理区块是由128个物理页面所组成，并且每一物理页面具有8个物理扇区(sector)。也就是说，在每一物理扇区为512字节(byte)的例子中，每一物理页面的容量为4千字节(Kilobyte,KB)。然而，必须了解的是，本发明不限于此，每一物理区块是可由64个物理页面、256个物理页面或其它任意个物理页面所组成。The rewritable non-volatile memory module 106 is electrically connected to the memory controller 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical blocks 304(0)˜304(R). For example, the physical blocks 304(0)˜304(R) may belong to the same memory die or belong to different memory dies. Each physical block has a plurality of physical pages, and each physical page has at least one physical sector, wherein the physical pages belonging to the same physical block can be written independently and erased simultaneously. For example, each physical block is composed of 128 physical pages, and each physical page has 8 physical sectors. That is to say, in an example where each physical sector is 512 bytes (byte), the capacity of each physical page is 4 kilobytes (Kilobyte, KB). However, it must be understood that the present invention is not limited thereto, and each physical block may be composed of 64 physical pages, 256 physical pages or any other number of physical pages.
更详细来说，物理区块为抹除的最小单位。亦即，每一物理区块含有最小数目的一并被抹除的存储单元。物理页面为编程的最小单元。即，物理页面为写入数据的最小单元。然而，必须了解的是，在本发明另一范例实施例中，写入数据的最小单位亦可以是物理扇区或其它大小。每一物理页面通常包括数据位区与冗余位区。数据位区用以储存使用者的数据，而冗余位区用以储存系统的数据(例如，错误检查与校正码)。In more detail, a physical block is the smallest unit of erasure. That is, each physical block contains a minimum number of memory cells that are erased together. A physical page is the smallest unit of programming. That is, a physical page is the minimum unit for writing data. However, it must be understood that, in another exemplary embodiment of the present invention, the smallest unit of writing data may also be a physical sector or other sizes. Each physical page generally includes a data bit field and a redundant bit field. The data bit area is used to store user data, and the redundant bit area is used to store system data (eg, error checking and correction code).
在本范例实施例中，可复写式非易失性存储器模块106为多阶存储单元(Multi Level Cell,MLC)NAND闪存模块，即一个存储单元中可储存至少2个位数据。然而，本发明不限于此，可复写式非易失性存储器模块106亦可是单阶存储单元(Single Level Cell,SLC)NAND闪存模块、多个阶存储单元(Trinary Level Cell,TLC)NAND型闪存模块、其它闪存模块或其它具有相同特性的存储器模块。In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (Multi Level Cell, MLC) NAND flash memory module, that is, at least 2 bits of data can be stored in one memory cell. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 can also be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module, a multi-level storage unit (Trinary Level Cell, TLC) NAND flash memory modules, other flash modules, or other memory modules with the same characteristics.
断电时间计算单元100是用提供存储器储存装置100被断电的时间。例如，断电时间计算单元110被实作为计数器108与电池109。计数器108是电性连接至存储器控制器104，其中记录有一个值。在计数器108被启动以后，计数器108会持续的更新所记录的值。例如，计数器108会在隔每一个时间单位后增加所记录的值。因此，计数器108所记录的值在经过计算以后也可以被用来表示一个时间区间。而电池109则是用以供应电源给计数器108。存储器控制器104可以通过启动计数器108以及读取计数器108等操作来取得存储器储存装置100被断电的时间。The power-off time calculation unit 100 is used to provide the time when the memory storage device 100 is powered off. For example, the power-off time calculation unit 110 is implemented as the counter 108 and the battery 109 . The counter 108 is electrically connected to the memory controller 104 and records a value therein. After the counter 108 is activated, the counter 108 will continuously update the recorded value. For example, the counter 108 increments the recorded value after every time unit. Therefore, the value recorded by the counter 108 can also be used to represent a time interval after calculation. The battery 109 is used to supply power to the counter 108 . The memory controller 104 can obtain the time when the memory storage device 100 is powered off by starting the counter 108 and reading the counter 108 .
图3是根据一范例实施例所绘示的存储器控制器的概要方块图。FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment.
请参照图3，存储器控制器104包括存储器管理电路202、主机接口204与存储器接口206。Referring to FIG. 3 , the memory controller 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .
存储器管理电路202用以控制存储器控制器104的整体运作。具体来说，存储器管理电路202具有多个控制指令，并且在存储器储存装置100运作时，此些控制指令会被执行以进行数据的写入、读取与抹除等运作。The memory management circuit 202 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 202 has a plurality of control commands, and when the memory storage device 100 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.
在本范例实施例中，存储器管理电路202的控制指令是以固件型式来实作。例如，存储器管理电路202具有微处理器单元(未绘示)与只读存储器(未绘示)，并且此些控制指令是被烧录至此只读存储器中。当存储器储存装置100运作时，此些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等运作。In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
在本发明另一范例实施例中，存储器管理电路202的控制指令亦可以程序码型式储存于可复写式非易失性存储器模块106的特定区域(例如，存储器模块中专用于存放系统数据的系统区)中。此外，存储器管理电路202具有微处理器单元(未绘示)、只读存储器(未绘示)及随机存取存储器(未绘示)。特别是，此只读存储器具有驱动码，并且当存储器控制器104被致能时，微处理器单元会先执行此驱动码段来将储存于可复写式非易失性存储器模块106中的控制指令加载至存储器管理电路202的随机存取存储器中。之后，微处理器单元会运转此些控制指令以进行数据的写入、读取与抹除等运作。In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has driver code, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to store the control code stored in the rewritable non-volatile memory module 106. The instructions are loaded into random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.
此外，在本发明另一范例实施例中，存储器管理电路202的控制指令亦可以一硬件型式来实作。例如，存储器管理电路202包括微控制器、存储器管理单元、存储器写入单元、存储器读取单元、存储器抹除单元与数据处理单元。存储器管理单元、存储器写入单元、存储器读取单元、存储器抹除单元与数据处理单元是电性连接至微控制器。其中，存储器管理单元用以管理可复写式非易失性存储器模块106的物理区块；存储器写入单元用以对可复写式非易失性存储器模块106下达写入指令以将数据写入至可复写式非易失性存储器模块106中；存储器读取单元用以对可复写式非易失性存储器模块106下达读取指令以从可复写式非易失性存储器模块106中读取数据；存储器抹除单元用以对可复写式非易失性存储器模块106下达抹除指令以将数据从可复写式非易失性存储器模块106中抹除；而数据处理单元用以处理欲写入至可复写式非易失性存储器模块106的数据以及从可复写式非易失性存储器模块106中读取的数据。In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are electrically connected to the microcontroller. Wherein, the memory management unit is used to manage the physical block of the rewritable non-volatile memory module 106; the memory writing unit is used to issue a write command to the rewritable non-volatile memory module 106 to write data into In the rewritable non-volatile memory module 106; the memory reading unit is used to issue a read instruction to the rewritable non-volatile memory module 106 to read data from the rewritable non-volatile memory module 106; The memory erase unit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106; and the data processing unit is used to process the The data of the rewritable nonvolatile memory module 106 and the data read from the rewritable nonvolatile memory module 106 .
主机接口204是电性连接至存储器管理电路202并且用以接收与识别主机系统1000所传送的指令与数据。也就是说，主机系统1000所传送的指令与数据会通过主机接口204来传送至存储器管理电路202。在本范例实施例中，主机接口204是兼容于SATA标准。然而，必须了解的是本发明不限于此，主机接口204亦可以是兼容于PATA标准、IEEE 1394标准、PCI Express标准、USB标准、SD标准、MS标准、MMC标准、CF标准、IDE标准或其它适合的数据传输标准。The host interface 204 is electrically connected to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other Appropriate data transmission standards.
存储器接口206是电性连接至存储器管理电路202并且用以存取可复写式非易失性存储器模块106。也就是说，欲写入至可复写式非易失性存储器模块106的数据会经由存储器接口206转换为可复写式非易失性存储器模块106所能接受的格式。The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .
在本发明一范例实施例中，存储器控制器104还包括缓冲存储器252、电源管理电路254与错误检查与校正电路256。In an exemplary embodiment of the present invention, the memory controller 104 further includes a buffer memory 252 , a power management circuit 254 and an error checking and correction circuit 256 .
缓冲存储器252是电性连接至存储器管理电路202并且用以暂存来自于主机系统1000的数据与指令或来自于可复写式非易失性存储器模块106的数据。The buffer memory 252 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .
电源管理电路254是电性连接至存储器管理电路202并且用以控制存储器储存装置100的电源。The power management circuit 254 is electrically connected to the memory management circuit 202 and used for controlling the power of the memory storage device 100 .
错误检查与校正电路256是电性连接至存储器管理电路202并且用以执行错误检查与校正程序以确保数据的正确性。具体来说，当存储器管理电路202从主机系统1000中接收到写入指令时，错误检查与校正电路256会为对应此写入指令的数据产生对应的错误检查与校正码(Error Checking andCorrecting Code,ECC Code)，并且存储器管理电路202会将对应此写入指令的数据与对应的错误检查与校正码写入至可复写式非易失性存储器模块106中。之后，当存储器管理电路202从可复写式非易失性存储器模块106中读取数据时会同时读取此数据对应的错误检查与校正码，并且错误检查与校正电路256会依据此错误检查与校正码对所读取的数据执行错误检查与校正程序。The error checking and correcting circuit 256 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correcting circuit 256 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECC Code), and the memory management circuit 202 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 256 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.
当存储器储存装置100电性连接至主机系统1000时，主机系统1000会供应电源给存储器储存装置100中的各个元件(例如，存储器控制器104与可复写式非易失性存储器模块106)。相反地，存储器储存装置100与主机系统1000的电性连接关系被切断时，存储器储存装置100中的各个元件便会被断电。在本范例实施例中，存储器管理电路202会计算存储器储存装置100失去电源供应的一个断电时间。若此断电时间超过一个时间临界值，则会进一步的判断所有的物理区是否符合一个更新条件。并且，存储器管理电路202会对符合更新条件的物理区块执行一个更新程序，将物理区块所储存的数据重新写入。When the memory storage device 100 is electrically connected to the host system 1000, the host system 1000 supplies power to each component in the memory storage device 100 (for example, the memory controller 104 and the rewritable non-volatile memory module 106). Conversely, when the electrical connection between the memory storage device 100 and the host system 1000 is cut off, each component in the memory storage device 100 will be powered off. In this exemplary embodiment, the memory management circuit 202 calculates a power-off time when the memory storage device 100 loses power supply. If the power-off time exceeds a time critical value, it will be further judged whether all physical areas meet an update condition. Moreover, the memory management circuit 202 executes an update program on the physical blocks meeting the update conditions, and rewrites the data stored in the physical blocks.
具体来说，当存储器储存装置100被断电时(此时亦称第一时间)，存储器管理电路202会启动计数器108。接下来，计数器108便会持续地更新其所记录的值。而在存储器储存装置100被断电的期间，由电池109供应电源给计数器108。因此，即使主机系统1000并没有供应电源给存储器储存装置100，计数器108还是可以正常的运作。Specifically, when the memory storage device 100 is powered off (also referred to as the first time at this time), the memory management circuit 202 starts the counter 108 . Next, the counter 108 will continuously update its recorded value. While the memory storage device 100 is powered off, the battery 109 supplies power to the counter 108 . Therefore, even if the host system 1000 does not supply power to the memory storage device 100, the counter 108 can still operate normally.
接下来，当存储器储存装置100重新被电性连接至主机系统1000(或是电性连接至另一个能提供电源的电子装置)时，存储器储存装置100及其中的各个元件都会被给电。此时(亦称为第二时间)，存储器管理电路202会读取计数器108所记录的值，并根据计数器108所记录的值来计算一个断电时间，此断电时间表示从第一时间到第二时间经过了多久。换句话说，存储器管理电路202可以根据计数器108所记录的值来取得距离可复写式非易失性存储器模块106上一次被断电的第一时间到目前被给电的第二时间之间的断电时间。Next, when the memory storage device 100 is electrically connected to the host system 1000 (or electrically connected to another electronic device capable of providing power), the memory storage device 100 and its components will be powered. At this time (also referred to as the second time), the memory management circuit 202 will read the value recorded by the counter 108, and calculate a power-off time according to the value recorded by the counter 108, and this power-off time represents from the first time to How long did the second time pass. In other words, the memory management circuit 202 can obtain the time between the first time when the rewritable non-volatile memory module 106 was powered off last time and the second time when it is currently powered on according to the value recorded by the counter 108 power outage time.
存储器管理电路202会判断所计算出的断电时间是否超过一个时间临界值(亦称第一时间临界值)。若断电时间超过此时间临界值，存储器管理电路202会根据物理区块的区块信息(例如抹除次数，错误更正码或是读取次数)来判断判断物理区块304(0)～304(R)是否符合更新条件。若一个物理区块符合更新条件，则表示储存在此物理区块中的数据有容易遗失，或是容易发生错误的可能。在本范例实施例中，存储器管理电路202会对符合更新条件的物理区块执行更新程序。此更新程序是用以读取一个物理区块所储存的数据并将此数据重新写入至物理区块304(0)～304(R)的其中之一。The memory management circuit 202 determines whether the calculated power-off time exceeds a time threshold (also called a first time threshold). If the power-off time exceeds the time threshold, the memory management circuit 202 will judge and judge the physical blocks 304(0)-304 according to the block information of the physical block (such as erasing times, error correction codes or reading times) (R) Whether the update condition is met. If a physical block meets the update condition, it means that the data stored in the physical block may be easily lost or error may easily occur. In this exemplary embodiment, the memory management circuit 202 executes an update program on the physical blocks meeting the update conditions. The update procedure is used to read data stored in a physical block and rewrite the data into one of the physical blocks 304(0)˜304(R).
例如，存储器管理电路202会取得每一个物理区块的抹除次数。当存储器管理电路202判断断电时间超过第一时间临界值时，会判断抹除次数超过一个抹除临界值的物理区块满足更新条件。在本范例实施例中，第一时间临界值是被设定为1个月，而抹除临界值则为一个物理区块的抹除上限(例如，10万次)。然而，在其它范例实施例中，第一时间临界值与抹除临界值也可以被设定为其它的时间与次数，本发明并不在此限。For example, the memory management circuit 202 obtains the erasing times of each physical block. When the memory management circuit 202 determines that the power-off time exceeds the first time threshold, it will determine that the physical block whose erasing times exceed an erasing threshold meets the update condition. In this exemplary embodiment, the first time threshold is set as 1 month, and the erasure threshold is set as the upper limit of erasure of a physical block (for example, 100,000 times). However, in other exemplary embodiments, the first time threshold and the erasing threshold may also be set to other times and times, and the present invention is not limited thereto.
图4与图5是根据一范例实施例说明对一物理区块执行更新程序的范例示意图。FIG. 4 and FIG. 5 are exemplary diagrams illustrating an update procedure for a physical block according to an exemplary embodiment.
请参照图4，在此假设当存储器储存装置100重新被给电时，存储器管理电路202判断断电时间已超过第一时间临界值，且物理区块304(0)的抹除次数已超过抹除临界值。也就是说，物理区块304(0)会满足更新条件。此时，存储器管理电路202会读取储存在物理区块304(0)中的第一数据402至缓冲存储器252，并会对物理区块304(0)执行抹除指令。接下来，存储器管理电路202会将第一数据402重新写入至物理区块304(0)。如此一来，便完成对物理区块304(0)执行更新程序的操作。然而，存储器管理电路202也可以将第一数据402写入至其它的物理区块，本发明并不在此限。在另一范例实施例中，如图5所示，存储器管理电路202也会将第一数据402写入至物理区块304(1)当中。Please refer to FIG. 4 , assuming that when the memory storage device 100 is powered on again, the memory management circuit 202 judges that the power-off time has exceeded the first time threshold, and the erasing times of the physical block 304 (0) have exceeded the erasing time. Except the critical value. That is, the physical block 304(0) satisfies the update condition. At this time, the memory management circuit 202 reads the first data 402 stored in the physical block 304(0) to the buffer memory 252, and executes an erase command on the physical block 304(0). Next, the memory management circuit 202 rewrites the first data 402 into the physical block 304(0). In this way, the operation of updating the physical block 304(0) is completed. However, the memory management circuit 202 may also write the first data 402 into other physical blocks, and the present invention is not limited thereto. In another exemplary embodiment, as shown in FIG. 5 , the memory management circuit 202 also writes the first data 402 into the physical block 304(1).
此外，在另一范例实施例中，存储器管理电路202会先判断断电时间是否大于一个第二时间临界值，如断电时间没超过第二时间临界值时，再判断是否超过第一时间临界值。第二时间临界值会大于第一时间临界值。在本范例实施例中，第二时间临界值是被设定为1年，当断电时间大于第二时间临界值时，表示储存在物理区块304(0)～304(R)的数据已经很久没有被更新，容易遗失或发生错误。因此，在判断断电时间大于第二时间临界值时，存储器管理电路202会判断所有的物理区块304(0)～304(R)都符合更新条件。换言之，存储器管理电路202会对所有的物理区块304(0)～304(R)都执行更新程序。然而，在其它范例实施例中，第二时间临界值也可以被设定为其它的数值，本发明并不在此限。In addition, in another exemplary embodiment, the memory management circuit 202 will first determine whether the power-off time is greater than a second time critical value, if the power-off time does not exceed the second time critical value, then determine whether the first time critical value is exceeded value. The second time threshold is greater than the first time threshold. In this exemplary embodiment, the second time threshold is set to 1 year. When the power-off time is greater than the second time threshold, it means that the data stored in the physical blocks 304(0)-304(R) have been It has not been updated for a long time, and it is easy to lose or make mistakes. Therefore, when it is determined that the power-off time is greater than the second time threshold, the memory management circuit 202 determines that all the physical blocks 304(0)-304(R) meet the updating conditions. In other words, the memory management circuit 202 executes the update procedure on all the physical blocks 304(0)˜304(R). However, in other exemplary embodiments, the second time threshold may also be set to other values, and the invention is not limited thereto.
另一方面，本范例实施例中是根据抹除次数来判断是否执行更新程序。然而，由于每一次的抹除都是为了让物理区块能够接受下一个写入操作。因此，在另一范例实施例中，也可以计算每一个物理区块的写入次数，并用写入次数来代替抹除次数，本发明并不在此限。On the other hand, in this exemplary embodiment, whether to execute the update procedure is determined according to the erasing times. However, each erasure is to allow the physical block to accept the next write operation. Therefore, in another exemplary embodiment, the writing times of each physical block may also be calculated, and the writing times may be used to replace the erasing times, and the present invention is not limited thereto.
除了根据断电时间与抹除次数来判断一个物理区块是否符合更新条件以外，在另一范例实施例中，存储器管理电路202还会根据一个物理区块中所储存的数据是否发生错误来判断此物理区块是否符合更新条件。具体来说，每一个物理区块会包括多个物理页面，每个物理页面会包括一个数据位区与一个冗余位区。数据位区是用以储存使用者的数据，而冗余位区是用以储存系统的数据。例如，冗余位区可以储存一个错误更正码(error correctioncode,ECC)，此错误更正码是对应到数据位区中的数据。存储器管理电路202可以根据冗余位区中的错误更正码来判断数据位区中的数据是否发生错误。In addition to judging whether a physical block meets the update condition according to the power-off time and erasing times, in another exemplary embodiment, the memory management circuit 202 also judges according to whether the data stored in a physical block has an error Whether this physical block is eligible for update. Specifically, each physical block includes multiple physical pages, and each physical page includes a data bit area and a redundancy bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data. For example, the redundant bit area can store an error correction code (ECC), which corresponds to the data in the data bit area. The memory management circuit 202 can determine whether an error occurs in the data in the data bit area according to the error correction code in the redundant bit area.
图6是根据一范例实施例说明利用错误更正码来判断数据是否发生错误的范例示意图。FIG. 6 is a schematic diagram illustrating an example of using an error correction code to determine whether an error occurs in data according to an example embodiment.
请参照图6，物理区块304(0)中包括了物理页面602(0)～602(A)、数据位区604(0)～604(A)与冗余位区606(0)～606(A)。例如，物理页面602(0)包括了数据位区604(0)与冗余位区606(0)，而物理页面602(1)包括了数据位区604(1)与冗余位区606(1)。在数据位区604(0)中储存了数据620，而冗余位区606(0)储存了错误更正码(ECC)640。错误更正码640是用以判断数据620是否发生了错误，并且若数据620发生错误的位个数没有超过错误更正码640能够更正的上限，错误更正码640也可以用来更正数据620所发生的错误。在本范例实施例中，存储器管理电路202会根据错误更正码640与数据620来判断是否发生了一个可还原错误。此可还原错误便表示数据620发生错误的位个数并没有超过错误更正码640能够更正的上限。由于发生可还原错误的物理页面602(0)是属于物理页面304(0)，因此存储器管理电路会判断物理区块304(0)符合更新条件并对物理区块304(0)执行更新程序。换言之，存储器管理电路202会判断发生可还原错误的物理页面所属的物理区块符合更新条件。Please refer to FIG. 6, the physical block 304(0) includes physical pages 602(0)-602(A), data bit areas 604(0)-604(A) and redundant bit areas 606(0)-606 (A). For example, physical page 602(0) includes data bit area 604(0) and redundant bit area 606(0), while physical page 602(1) includes data bit area 604(1) and redundant bit area 606( 1). Data 620 is stored in data bit field 604(0), and error correction code (ECC) 640 is stored in redundant bit field 606(0). The error correction code 640 is used to judge whether an error has occurred in the data 620, and if the number of erroneous bits in the data 620 does not exceed the upper limit that the error correction code 640 can correct, the error correction code 640 can also be used to correct the error occurred in the data 620. mistake. In this exemplary embodiment, the memory management circuit 202 determines whether a recoverable error occurs according to the error correction code 640 and the data 620 . This recoverable error means that the number of erroneous bits in the data 620 does not exceed the upper limit that the error correction code 640 can correct. Since the physical page 602(0) where the recoverable error occurs belongs to the physical page 304(0), the memory management circuit determines that the physical block 304(0) meets the update condition and performs an update procedure on the physical block 304(0). In other words, the memory management circuit 202 determines that the physical block to which the physical page where the recoverable error occurs meets the update condition.
在本范例实施例中，断电时间计算单元110是被实作为计数器108与电池109。然而，在另一范例实施例中，断电时间计算单元110也可以被实作为一定时器(图未示)。此定时器可设置于主机系统1000或于存储器储存装置100，且此定时器可以一应用程序或一硬件电路的方式来实现。举例来说，当存储器储存装置100与主机系统1000之间的电性连接关系被切断以后(此时亦称第一时间)，主机系统1000上的一个应用程序便会开始计时。等到下次存储器储存装置100重新电性连接至主机系统1000时(此时亦称第二时间)，此应用程序便会识别存储器储存装置100，并计算出第一时间到第二时间之间的断电时间。接下来，应用程序会传送一个断电时间消息给存储器管理电路202，此断电时间消息便包含了所计算出的断电时间。因此，存储器管理电路202便可以根据此断电时间消息取得断电时间。In this exemplary embodiment, the power-off time calculation unit 110 is implemented as the counter 108 and the battery 109 . However, in another exemplary embodiment, the power-off time calculation unit 110 may also be implemented as a timer (not shown). The timer can be set in the host system 1000 or in the memory storage device 100, and the timer can be implemented by an application program or a hardware circuit. For example, when the electrical connection between the memory storage device 100 and the host system 1000 is cut off (this time is also called the first time), an application program on the host system 1000 will start timing. When the memory storage device 100 is electrically connected to the host system 1000 again (this time is also called the second time), the application program will identify the memory storage device 100 and calculate the time between the first time and the second time. power outage time. Next, the application program sends a power-off time message to the memory management circuit 202, and the power-off time message includes the calculated power-off time. Therefore, the memory management circuit 202 can obtain the power-off time according to the power-off time message.
图7是根据一范例实施例说明数据保护方法的流程图。FIG. 7 is a flowchart illustrating a data protection method according to an exemplary embodiment.
请参照图7，在步骤S702中，当可复写式非易失性存储器模块被给电时，存储器管理电路202会取得距离可复写式非易失性存储器模块上一次断电的第一时间到目前被给电的第二时间之间的断电时间。Please refer to FIG. 7, in step S702, when the rewritable non-volatile memory module is powered on, the memory management circuit 202 will obtain the first time since the last power-off of the rewritable non-volatile memory module. The power-off time between the second times currently powered on.
在步骤S704中，存储器管理电路202会判断断电时间是否大于第二时间临界值。In step S704, the memory management circuit 202 determines whether the power-off time is greater than a second time threshold.
若断电时间大于第二时间临界值，在步骤S706中，存储器管理电路202会判断所有的物理区块都符合更新条件。If the power-off time is greater than the second time threshold, in step S706, the memory management circuit 202 determines that all physical blocks meet the updating conditions.
若断电时间并不大于第二时间临界值，在步骤S708中，存储器管理电路202会判断电时间是否大于第一时间临界值。If the power-off time is not greater than the second time critical value, in step S708, the memory management circuit 202 determines whether the power-off time is greater than the first time critical value.
若断电时间大于第一时间临界值，在步骤S710中，存储器管理电路202会根据每一个物理区块的区块信息来判断物理区块是否符合更新条件。相反的，若断电时间并不大于第一时间临界值，则存储器管理电路202会结束此流程。If the power-off time is greater than the first time threshold, in step S710, the memory management circuit 202 determines whether the physical block meets the update condition according to the block information of each physical block. On the contrary, if the power-off time is not greater than the first time threshold, the memory management circuit 202 ends the process.
在步骤S721中，存储器管理电路202会对符合更新条件的物理区块执行更新程序。In step S721, the memory management circuit 202 executes an update program on the physical blocks meeting the update conditions.
然而，图7中各步骤已详细说明如上，在此便不再赘述。However, each step in FIG. 7 has been described in detail above, and will not be repeated here.
综上所述，本发明范例实施例所提出的数据保护方法、存储器控制器与存储器储存装置，可以在存储器储存装置重新被给电的时候得到一个断电时间。并且，会根据断电时间的大小、物理区块的抹除次数或是否发生可还原错误来决定是否要对物理区块执行更新程序。如此一来，物理区块中所储存的数据会在存储器储存装置被给电时被重新写入。藉此，可以保护物理区块中所储存的数据不会容易遗失，进一步地增加可复写式非易失性存储器的使用寿命。To sum up, the data protection method, memory controller and memory storage device proposed by the exemplary embodiments of the present invention can obtain a power-off time when the memory storage device is powered on again. In addition, it is determined whether to perform an update program on the physical block according to the length of the power-off time, the erasing times of the physical block, or whether a recoverable error occurs. In this way, the data stored in the physical block will be rewritten when the memory storage device is powered on. In this way, the data stored in the physical block can be protected from easy loss, further increasing the service life of the rewritable non-volatile memory.
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求范围所界定者为准。Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims (18)
1. a data guard method, for controlling a reproducible nonvolatile memorizer module, this can Manifolding formula non-volatile memory module includes multiple physical blocks, and this data guard method includes:
When this reproducible nonvolatile memorizer module is powered, obtain non-easily apart from this duplicative Between one second time that one very first time of the property lost memory module last time power-off is powered up till now One power-off time；
When this power-off time is more than a very first time marginal value, according to a district of those physical blocks each Block message judges whether those physical blocks each meet a update condition, and wherein said block information is fitted Probability in the loss or mistake reflecting the data being stored in described physical blocks；
The physical blocks meeting this update condition in those physical blocks is performed a more new procedures, wherein should More new procedures is in order to one first data read stored by the physical blocks being performed this more new procedures should First data re-write one of them to those physical blocks.
Data guard method the most according to claim 1, wherein this block information is number of times of erasing, Described this block information according to those physical blocks each judges whether those physical blocks each meet this more The step of New Terms includes:
Judging in those physical blocks, this number of times of erasing meets more than this physical blocks erasing marginal value This update condition.
Data guard method the most according to claim 1, also includes:
When this power-off time is more than second time critical values, it is judged that those physical blocks all of all accord with Closing this update condition, wherein said second time critical values is more than described very first time marginal value.
Data guard method the most according to claim 1, wherein this block information is an error correction Code, those physical blocks each include that multiple physical page, those physical pages each include a data bit District and a redundancy function district, this redundancy function district in order to record this error correcting code, wherein according to each those This block information of physical blocks judges whether those physical blocks each meet the step bag of this update condition Include:
According to the data stored by this data bit district and this error correcting code, it is judged that for those things each Whether the reason page there is a reducible mistake, wherein stored by this data bit district of this reducible misrepresentation Data make a mistake, but can correct the data stored by this data bit district according to this error correcting code； And
If there is this reducible mistake, then judge being somebody's turn to do belonging to this physical page of this reducible mistake of generation Physical blocks meets this update condition.
Data guard method the most according to claim 1, wherein obtains the step bag of this power-off time Include:
When this reproducible nonvolatile memorizer module is de-energized, sets an enumerator and start to update this The value that enumerator is recorded；And
When this reproducible nonvolatile memorizer module is powered, the value recorded according to this enumerator Obtain this power-off time.
Data guard method the most according to claim 1, wherein obtains the step bag of this power-off time Include:
When this reproducible nonvolatile memorizer module is powered, by a power-off time computing unit Obtain this power-off time.
7. a memorizer memory devices, including:
A connector, is electrically connected to a host computer system；
One reproducible nonvolatile memorizer module, including multiple physical blocks；And
One Memory Controller, is electrically connected to this adapter and this type nonvolatile mould Block,
Wherein, when this memorizer memory devices is powered, this Memory Controller should in order to obtain distance Between one second time that one very first time of memorizer memory devices last time power-off is powered up till now One power-off time,
Wherein, when this power-off time is more than a very first time marginal value, this Memory Controller is in order to root Judge whether those physical blocks each meet a renewal according to a block information of those physical blocks each Condition, wherein said block information be suitable to reflect the loss of the data being stored in described physical blocks or The probability of mistake,
Wherein, this Memory Controller is in order to this physics meeting this update condition in those physical blocks Onblock executing one more new procedures, wherein this more new procedures is in order to read this physics being performed this more new procedures One first data stored by block and these first data are re-write to those physical blocks wherein it One 。
Memorizer memory devices the most according to claim 7, wherein this block information is to erase time Number, this Memory Controller is also in order to judge in those physical blocks, and this number of times of erasing is erased more than one and faced This physical blocks of dividing value meets this update condition.
Memorizer memory devices the most according to claim 7, wherein when this power-off time is more than one the During two time critical values, this Memory Controller judges that those physical blocks all of all meet this renewal bar Part, wherein said second time critical values is more than described very first time marginal value.
Memorizer memory devices the most according to claim 7, wherein this block information is a mistake More code, those physical blocks each include that multiple physical page, those physical pages each include a number According to position district and a redundancy function district, this redundancy function district in order to record this error correcting code,
This Memory Controller is according to the data stored by this data bit district and this error correcting code, it is judged that Whether those physical pages each there is a reducible mistake, wherein this this data bit of reducible misrepresentation Data stored by district make a mistake, but can correct this data bit district according to this error correcting code and be stored up The data deposited,
If there is this reducible mistake, also there is this reducible mistake in order to judging in this Memory Controller This physical blocks belonging to this physical page meets this update condition.
11. memorizer memory devices according to claim 7, also include:
One enumerator, is electrically connected to this Memory Controller；And
One battery a, it is provided that power supply gives this enumerator,
Wherein when this memorizer memory devices is de-energized, this Memory Controller sets this enumerator to start Update the value recorded,
Wherein when this memorizer memory devices is powered, this Memory Controller is remembered according to this enumerator The value of record obtains this power-off time.
12. memorizer memory devices according to claim 7, wherein when this memorizer memory devices When being powered, this Memory Controller is also in order to obtain this power-off time by a power-off time computing unit.
13. 1 kinds of Memory Controllers, including:
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to a reproducible nonvolatile memorizer module, and this can be made carbon copies Formula non-volatile memory module includes multiple physical blocks；And
One memory management circuitry, is electrically connected to this HPI and this memory interface,
Wherein, when this reproducible nonvolatile memorizer module is powered, this memory management circuitry Obtain apart from this reproducible nonvolatile memorizer module last time power-off a very first time up till now by Give the power-off time between one second time of electricity,
Wherein, when this power-off time more than the very first time marginal value time, this memory management circuitry in order to A block information according to those physical blocks each judges whether those physical blocks each meet one more New Terms, wherein said block information is suitable to reflect the loss of the data being stored in described physical blocks Or the probability of mistake,
Wherein, this memory management circuitry is in order to this thing meeting this update condition in those physical blocks Reason onblock executing one more new procedures, wherein this more new procedures is in order to read this thing being performed this more new procedures Manage one first data stored by block and these first data are re-write to those physical blocks wherein One of.
14. Memory Controllers according to claim 13, wherein this block information is to erase time Number, this memory management circuitry is also in order to judge in those physical blocks, and this number of times of erasing is erased more than one This physical blocks of marginal value meets this update condition.
15. Memory Controllers according to claim 13, wherein when this power-off time is more than one the During two time critical values, this memory management circuitry judges that those physical blocks all of all meet this renewal Condition, wherein said second time critical values is more than described very first time marginal value.
16. Memory Controllers according to claim 13, wherein this block information be a mistake more Code, those physical blocks each include that multiple physical page, those physical pages each include data A district and redundancy function district, position, this redundancy function district in order to record this error correcting code,
This memory management circuitry, according to the data stored by this data bit district and this error correcting code, is sentenced Whether disconnected those physical pages each there are a reducible mistake, wherein these these data of reducible misrepresentation Position data stored by district make a mistake, but can correct this institute of data bit district according to this error correcting code The data stored,
If there is this reducible mistake, this memory management circuitry judges to occur this thing of this reducible mistake Reason this physical blocks belonging to the page meets this update condition.
17. Memory Controllers according to claim 13, wherein non-volatile when this duplicative When memory module is de-energized, this memory management circuitry sets an enumerator and starts to update the value recorded, When this reproducible nonvolatile memorizer module is powered, this memory management circuitry is according to being somebody's turn to do The value that enumerator is recorded is to obtain this power-off time.
18. Memory Controllers according to claim 13, wherein non-volatile when this duplicative When memory module is powered, this memory management circuitry is also in order to take by a power-off time computing unit Obtain this power-off time.
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