CN103616814B - A kind of synchronized sampling closed-loop corrected method and system of clock based on FPGA - Google Patents

本发明公开了一种基于FPGA的同步采样时钟闭环校正方法和系统。该方法首先采用了对PPS脉冲信号脉冲持续时间与相邻脉冲触发周期分别进行判断，来检测其脉冲信号的正确性；然后实时接收并检测PPS判断模块发送的动作信号，以作出相应的反应；接着通过误差校正模块对本地晶振时钟的频率进行校正并根据动作信号的状态对同步重采信号的相位误差进行测量和校正；最后通过倍频计算模块生成同步重采信号，同时将输出信号反馈给误差校正模块形成了一个闭环系统，并根据校正信息校正信息对输出自动进行调整。该方法解决了在研究基于GPS采样数据同步的基础上，合并单元同步采样时钟对晶振依赖性强，以致在晶振老化、频率准确度降低的情况下，输出误差较大的问题。

The invention discloses an FPGA-based method and system for closed-loop correction of a synchronous sampling clock. The method firstly judges the pulse duration of the PPS pulse signal and the adjacent pulse trigger period to detect the correctness of the pulse signal; then receives and detects the action signal sent by the PPS judgment module in real time to make a corresponding response; Then, the frequency of the local crystal oscillator clock is corrected by the error correction module, and the phase error of the synchronous reacquisition signal is measured and corrected according to the state of the action signal; finally, the synchronous reacquisition signal is generated by the frequency multiplication calculation module, and the output signal is fed back to the The error correction module forms a closed-loop system, and automatically adjusts the output according to the correction information. This method solves the problem that the synchronous sampling clock of the merging unit has a strong dependence on the crystal oscillator on the basis of the research on the synchronization of GPS sampling data, so that the output error is relatively large when the crystal oscillator is aging and the frequency accuracy is reduced.

一种基于FPGA的同步采样时钟闭环校正方法和系统A method and system for closed-loop correction of synchronous sampling clock based on FPGA

技术领域technical field

本发明属于电工技术领域，具体涉及一种基于FPGA的同步采样时钟闭环校正方法。The invention belongs to the field of electrotechnical technology, and in particular relates to an FPGA-based closed-loop correction method for synchronous sampling clocks.

背景技术Background technique

智能变电站以全站信息数字化、通信平台网络化、信息共享标准化为基本要求，实现信息采集、测量、控制、保护、监测和计量等功能，而站域信息实时同步采集技术是实现智能变电站各种应用功能的基础，它要求电子式互感器对电网电流和电压的数据采样达到每秒数千次，一经采样便可被多个智能变电站中各个智能电子设备(IED)共享。但无论控制、保护，还是监测、计量的计算处理都要求采样数据应在同一个时间点上采集，以免相位和幅值产生误差。The smart substation takes the digitalization of the whole station information, the networking of the communication platform, and the standardization of information sharing as the basic requirements, and realizes the functions of information collection, measurement, control, protection, monitoring and metering. The basis of the application function, it requires the electronic transformer to sample the data of the grid current and voltage thousands of times per second, and once sampled, it can be shared by various intelligent electronic devices (IEDs) in multiple smart substations. However, regardless of the calculation and processing of control, protection, or monitoring and measurement, the sampling data should be collected at the same time point to avoid phase and amplitude errors.

对于过电流保护等保护，因为电子式互感器合并单元本地晶振时钟的短期稳定性非常高，不会对保护的动作精度造成影响。但对于差动保护和计量，由于合并单元本地晶振时钟并不十分准确，经过长时间的误差累积，会造成跨间隔间不同合并单元的相位误差和幅值误差的逐渐扩大，导致差动保护的误动作和计量的严重误差。For protection such as overcurrent protection, because the short-term stability of the local crystal oscillator clock of the electronic transformer merging unit is very high, it will not affect the operation accuracy of the protection. However, for differential protection and metering, since the local crystal oscillator clock of the merging unit is not very accurate, after a long period of error accumulation, the phase error and amplitude error of different merging units across intervals will gradually expand, resulting in the failure of differential protection. Misoperation and serious errors of measurement.

因此，发明一种性能更为优越、应用范围更为广泛的同步采样时钟闭环校正的新方法成为亟需解决的课题。Therefore, inventing a new method for synchronous sampling clock closed-loop correction with better performance and wider application range has become an urgent problem to be solved.

发明内容Contents of the invention

针对上述问题，本发明提出了一种电子式互感器合并单元中同步采样时钟的设计，致力于解决合并单元同步采样时钟对晶振依赖性强，在晶振老化，频率准确度降低的情况下，输出误差较大的不足。In view of the above problems, the present invention proposes a design of the synchronous sampling clock in the merging unit of the electronic transformer, which is dedicated to solving the strong dependence of the synchronous sampling clock of the merging unit on the crystal oscillator. When the crystal oscillator is aging and the frequency accuracy is reduced, the output Insufficient large error.

为达到上述目的，本发明采取的技术方案为：In order to achieve the above object, the technical scheme that the present invention takes is:

一种电子式互感器合并单元中同步采样时钟的设计，包括如下步骤：A design of a synchronous sampling clock in an electronic transformer merging unit, comprising the following steps:

1）通过PPS判断模块对PPS脉冲信号脉冲持续时间与相邻脉冲触发周期分别进行判断，来检测其脉冲信号的正确性；1) Through the PPS judgment module, the pulse duration of the PPS pulse signal and the adjacent pulse trigger cycle are respectively judged to detect the correctness of the pulse signal;

2）通过错误处理模块实时接收并检测PPS判断模块发送的动作信号，以作出相应的反应；2) Receive and detect the action signal sent by the PPS judgment module in real time through the error processing module to make corresponding responses;

3）通过误差校正模块对本地晶振时钟的频率进行校正并根据动作信号的状态对同步重采信号的频率误差和相位误差进行测量和校正；3) Use the error correction module to correct the frequency of the local crystal oscillator clock and measure and correct the frequency error and phase error of the synchronous reacquisition signal according to the state of the action signal;

4）通过倍频计算模块生成80点/周波的同步重采信号，同时将输出信号反馈给误差校正模块形成了一个闭环系统，根据误差校正模块发送来的校正信息对输出自动进行调整。4) The 80 points/cycle synchronous reacquisition signal is generated by the frequency multiplication calculation module, and the output signal is fed back to the error correction module to form a closed-loop system, and the output is automatically adjusted according to the correction information sent by the error correction module.

步骤一中采用PPS判断模块对PPS脉冲信号脉冲持续时间与相邻脉冲触发周期分别进行判断，来检测脉冲信号的正确性，即当合并单元系统启动后，FPGA就开始不断循环读取PPS脉冲信号输入引脚信号，直到检测到脉冲信号上升沿到来后同时触发两个计数器开始计数，通过本地时钟源对PPS脉冲信号进行检测。然后进行两个计数器数值的判断来判断脉冲信号的有效性。In step 1, the PPS judgment module is used to judge the pulse duration of the PPS pulse signal and the adjacent pulse trigger cycle to detect the correctness of the pulse signal, that is, when the merging unit system is started, the FPGA starts to read the PPS pulse signal continuously Input the pin signal until the rising edge of the pulse signal is detected and trigger the two counters to start counting at the same time, and detect the PPS pulse signal through the local clock source. Then judge the value of the two counters to judge the validity of the pulse signal.

步骤三中采用累计法测量4000个同步重采脉冲信号的间隔T_c，并通过倍频计算模块保证T_c=T_p，以避免了即使在晶振误差最大化的情况下，其两次同步重采信号间隔误差也只有0.25Hz，很难检测出的问题。In step 3, the cumulative method is used to measure the interval T _c of 4000 synchronous re-acquisition pulse signals, and the frequency multiplication calculation module is used to ensure that T _c =T _p , so as to avoid the two synchronous re-acquisition pulses even when the crystal oscillator error is maximized. The signal sampling interval error is only 0.25Hz, which is difficult to detect.

步骤四中采用了一种通过累加器实现的倍频方法，在FPGA中可以定义一个位宽W的reg寄存器型累加器Baund_acc与累加值变量Baund_inc。累加器Baund_acc容量2^w表示同步重采信号周期的数字量化值，累加值Baund_inc表示晶振周期的数字量化值。因此有：In step 4, a frequency doubling method implemented by an accumulator is adopted. A reg register type accumulator Baund_acc with a bit width W and an accumulated value variable Baund_inc can be defined in the FPGA. The accumulator Baund_acc capacity 2 ^w represents the digital quantization value of the synchronous reacquisition signal cycle, and the accumulated value Baund_inc represents the digital quantization value of the crystal oscillator cycle. So there are:

F_cry/F_res=2^w/Baund_incF _cry /F _res =2 ^w /Baund_inc

考虑到F_res=4000Hz，可求得considering F _res =4000Hz, can be obtained

BaundBaund __ incinc == 40004000 ·&Center Dot; 22 ww // Mm ‾‾

在每个晶振周期到来时，累加器Baund_acc都会加上Baund_inc，进行一次累加计算，则累加器的最高位输出即为占空比为50%的同步重采信号。此方法为实现同步重采信号的零时刻输出误差校正需要最长时间为When each crystal oscillator cycle comes, the accumulator Baund_acc will add Baund_inc to perform an accumulation calculation, and the highest bit output of the accumulator is a synchronous reacquisition signal with a duty cycle of 50%. This method requires a maximum time of

t_s=F_cry/(500·F_res)=25st _s =F _cry /(500·F _res )=25s

当PPS脉冲信号接入后，加上3s的PPS判断时间，最多需要28s，即可完全实现重采信号的同步输出。此方法克服了在本地晶振频率偏差较大时，同步重采信号的误差较大，不能实现同步重采信号的等间隔输出，对晶振的精度等级要求较高，且不利于对同步重采信号的零时刻输出误差进行校正的问题。When the PPS pulse signal is connected, plus the PPS judgment time of 3s, it takes up to 28s to fully realize the synchronous output of the re-acquisition signal. This method overcomes the large error of the synchronous re-acquisition signal when the frequency deviation of the local crystal oscillator is large, and cannot realize the equal interval output of the synchronous re-acquisition signal. The problem of correcting the zero-time output error.

相对于现有技术，本发明的有益效果主要有：该方法在提高输出精度的同时，降低了晶振频率误差对同步采样时钟的影响，节约了生产成本，保证了同步采样时钟的长期稳定运行。同时该方法也可应用于其他IED设备中同步时钟的实现，为智能变电站实现信息实时同步采集奠定了基础。Compared with the prior art, the beneficial effects of the present invention mainly include: while improving the output precision, the method reduces the influence of the frequency error of the crystal oscillator on the synchronous sampling clock, saves the production cost, and ensures the long-term stable operation of the synchronous sampling clock. At the same time, this method can also be applied to the realization of synchronous clocks in other IED equipment, which lays the foundation for the real-time synchronous collection of information in smart substations.

附图说明Description of drawings

图1本发明的流程框图；Fig. 1 block flow diagram of the present invention;

图2 PPS脉冲输入波形图；Figure 2 PPS pulse input waveform diagram;

图3 PPS脉冲检测流程图；Figure 3 PPS pulse detection flow chart;

图4误差校正原理图；Fig. 4 error correction principle diagram;

图5倍频计算模块运行流程图；Figure 5 is a flow chart of the operation of the multiplier calculation module;

图6同步采样时钟时序仿真图；Figure 6 Synchronous sampling clock timing simulation diagram;

图7（a）实验误差角差测试图；Figure 7(a) Experimental error angle difference test chart;

图7（b）实验误差比差测试图。Figure 7(b) Experimental error ratio difference test chart.

具体实施方式detailed description

以下结合附图和实施例对本发明作进一步说明。The present invention will be further described below in conjunction with drawings and embodiments.

如图1所示，一种电子式互感器合并单元中同步采样时钟的设计，包括如下步骤：As shown in Figure 1, the design of a synchronous sampling clock in an electronic transformer merging unit includes the following steps:

1）PPS判断。PPS脉冲信号触发特性如图2所示，当光强上升达到幅值的50%时触发时刻到来，其脉冲持续时间t_h>10μs，脉冲间隔时间t_I>500ms，相邻脉冲触发周期T_p=1s。因此可以通过对其脉冲持续时间与相邻脉冲触发周期分别进行判断，来检测PPS脉冲信号的正确性，PPS判断模块检测流程图如图3所示。1) PPS judgment. The trigger characteristics of the PPS pulse signal are shown in Figure 2. When the light intensity rises to 50% of the amplitude, the trigger moment arrives. The pulse duration t _h >10μs, the pulse interval time t _I >500ms, and the adjacent pulse trigger period T _p =1s. Therefore, the correctness of the PPS pulse signal can be detected by judging its pulse duration and the adjacent pulse trigger period respectively. The detection flow chart of the PPS judging module is shown in Figure 3.

当合并单元系统启动后，FPGA就开始不断循环读取PPS脉冲信号输入引脚信号，直到检测到脉冲信号上升沿到来后同时触发两个计数器开始计数，通过本地时钟源对PPS脉冲信号进行检测。本文选用精度为20ppm的50MHz普通石英晶振作为本地时钟源，则晶振实际每秒振动次数在5×10⁷±1000之间。启动计数器1，对PPS脉冲信号高电平持续时间内本地晶振振动次数进行累加计算，当下降沿到来时计数器1的计数值N₁被锁存，然后执行判断1，判断N₁是否大于500，即t_h>10μs。但若N₁计数到25×10⁶还在计数，即t_h>500ms，则自动停止计数，执行判断1出错。启动计数器2，对PPS脉冲信号相邻脉冲触发周期内本地晶振振动次数进行累加计算，当检测到下一个脉冲信号上升沿到来后计数器2的计数值N₂被锁存，然后执行判断2，判断N₂是否大于4.9999×10⁷，即T_p≈1s。但若N2计数到5.0001×10⁷还在计数，即T_p>1s，则自动停止计数，执行判断2出错。当判断1或判断2出错时，则自动进入出错处理程序，将PPS判断模块所有寄存器清零，回到等待PPS脉冲信号上升沿的初始状态。若判断1和判断2能同时满足则进入判断3，需要经过连续三次判断正确则认为PPS脉冲信号有效，输出同步标志信号syn=1，同时无论判断正确与否将计数器1和计数器2的值清零。When the merging unit system is started, the FPGA starts to continuously read the PPS pulse signal input pin signal continuously until the rising edge of the pulse signal is detected and triggers two counters to start counting at the same time, and detects the PPS pulse signal through the local clock source. In this paper, a 50MHz ordinary quartz crystal oscillator with an accuracy of 20ppm is selected as the local clock source, and the actual number of vibrations per second of the crystal oscillator is between 5×10 ⁷ ±1000. Start the counter 1, and calculate the number of vibrations of the local crystal oscillator within the duration of the high level of the PPS pulse signal. When the falling edge arrives, the count value N ₁ of the counter 1 is latched, and then executes judgment 1 to judge whether N ₁ is greater than 500. That is, t _h >10 μs. However, if N ₁ counts to 25×10 ⁶ and is still counting, that is, t _h >500ms, the counting will automatically stop, and judgment 1 will be executed to make an error. Start the counter 2, and calculate the number of vibrations of the local crystal oscillator in the adjacent pulse trigger period of the PPS pulse signal. When the rising edge of the next pulse signal is detected, the count value N ₂ of the counter 2 is latched, and then the judgment 2 is executed. Whether N ₂ is greater than 4.9999×10 ⁷ , that is, T _p ≈1s. However, if N2 counts to 5.0001×10 ⁷ and is still counting, that is, T _p >1s, it will automatically stop counting and execute judgment 2 to make an error. When Judgment 1 or Judgment 2 is wrong, it will automatically enter the error handling program, clear all registers of the PPS judgment module, and return to the initial state of waiting for the rising edge of the PPS pulse signal. If Judgment 1 and Judgment 2 can be satisfied at the same time, enter Judgment 3. After three consecutive judgments are correct, the PPS pulse signal is considered valid, and the synchronization flag signal syn=1 is output. At the same time, the values of Counter 1 and Counter 2 are cleared regardless of whether the judgment is correct or not. zero.

2）错误处理。错误处理模块实时接收并检测PPS判断模块发送的syn信号，若其值为0，则向外发送同步异常亮灯告警信号，同步采样时钟进行异步守时输出，直到PPS脉冲信号重新正确接入并连续三秒判断有效，syn信号值为1，将错误处理模块重置。2) Error handling. The error processing module receives and detects the syn signal sent by the PPS judgment module in real time. If the value is 0, it sends out a synchronous abnormal light alarm signal, and the synchronous sampling clock is output asynchronously and punctually until the PPS pulse signal is correctly connected again and The judgment is valid for three consecutive seconds, the syn signal value is 1, and the error handling module is reset.

3）误差校正。误差校正示意图如图4所示。IEC61850-9-2LE标准要求合并单元采样率为80点/周波或256点/周波（50Hz），本文以经常使用的80点/周波为例，即要求同步重采信号输出速率固定为4000点/秒。由于相邻同步重采信号之间的时间间隔很短，因此即使在晶振误差最大化的情况下，其两次同步重采信号间隔误差也只有0.25Hz，很难检测出。所以可以采用累积法，测量4000个同步重采脉冲信号的间隔T_c，并通过倍频计算模块保证T_c=T_p。当误差校正模块检测到syn信号值为1时，在PPS判断模块中判断2条件满足后，对计数器2中的前三次计数值N₂进行均值计算得到平均值并将其作为晶振的实际振动频率发送给倍频计算模块进行校正处理。当误差校正模块检测到syn信号值为0时，则将失去同步前计算出的值发送给倍频计算模块，进入异步守时状态。3) Error correction. The schematic diagram of error correction is shown in Fig. 4. The IEC61850-9-2LE standard requires the sampling rate of the merging unit to be 80 points/cycle or 256 points/cycle (50Hz). This article takes the frequently used 80 points/cycle as an example, which requires that the synchronous resampling signal output rate is fixed at 4000 points/cycle Second. Since the time interval between adjacent synchronous re-acquisition signals is very short, even if the error of the crystal oscillator is maximized, the error of the interval between two synchronous re-acquisition signals is only 0.25Hz, which is difficult to detect. Therefore, the accumulation method can be used to measure the interval T _c of 4000 synchronous resampling pulse signals, and the frequency multiplication calculation module can be used to ensure that T _c =T _p . When the error correction module detects that the syn signal value is 1, after judging that the 2 conditions are satisfied in the PPS judgment module, the average value calculation of the first three count values N in the counter ₂ is carried out to obtain the average value And send it as the actual vibration frequency of the crystal oscillator to the multiplier calculation module for correction processing. When the error correction module detects that the value of the syn signal is 0, the calculated value before the synchronization will be lost The value is sent to the multiplier calculation module and enters the asynchronous punctual state.

当PPS脉冲信号到来，上升沿触发时，误差校正模块开始计时。同时定义在这之后或此刻倍频模块输出的第一个同步重采信号为0号，当0号重采信号到来后误差校正模块停止计时，测量出PPS脉冲信号与0号同步重采信号之间的时间差t₀，即t₀时间内晶振振动次数K，并将K发送给倍频计算模块进行修正处理，以此来保证同步重采信号的输出无相位偏差。当误差校正模块检测到syn信号值为0时，则将K值清零，进入异步守时状态。When the PPS pulse signal arrives and is triggered by the rising edge, the error correction module starts timing. At the same time, it is defined that the first synchronous re-acquisition signal output by the frequency multiplier module after this or at this moment is No. 0. When the No. 0 re-acquisition signal arrives, the error correction module stops timing and measures the difference between the PPS pulse signal and the No. 0 synchronous re-acquisition signal. The time difference between t ₀ , that is, the number of crystal oscillator vibrations K within t ₀ , and K is sent to the multiplication calculation module for correction processing, so as to ensure that the output of the synchronous reacquisition signal has no phase deviation. When the error correction module detects that the value of the syn signal is 0, it clears the value of K and enters the state of asynchronous time keeping.

4）倍频计算。倍频计算模块运行流程图如图5所示。4) Multiplier calculation. The operating flow chart of the multiplier calculation module is shown in Figure 5.

由于FPGA中reg寄存器型变量可自由定义位宽，因此可以定义一个位宽W的reg寄存器型累加器Baund_acc与累加值变量Baund_inc。累加器Baund_acc容量2^w表示同步重采信号周期的数字量化值，累加值Baund_inc表示晶振周期的数字量化值。因此有Since the reg register type variable in FPGA can freely define the bit width, a reg register type accumulator Baund_acc and the accumulated value variable Baund_inc of a bit width W can be defined. The accumulator Baund_acc capacity 2 ^w represents the digital quantization value of the synchronous reacquisition signal cycle, and the accumulated value Baund_inc represents the digital quantization value of the crystal oscillator cycle. Therefore there are

F_cry/F_res=2^w/Baund_inc （3）F _cry /F _res =2 ^w /Baund_inc (3)

考虑到F_res=4000Hz，可求得considering F _res =4000Hz, can be obtained

BaundBaund __ incinc == 40004000 ·&Center Dot; 22 ww // Mm ‾‾ -- -- -- (( 44 ))

当倍频计算模块接收到误差校正模块发送的晶振频率校正值后，可通过式（4）向下取整计算出累加值Baund_inc。因为累加器Baund_acc为无符号整型，因此可以无视其溢出，不断做循环累加。在每个晶振周期到来时，累加器Baund_acc都会加上Baund_inc，进行一次累加计算，则累加器的最高位输出即为占空比为50%的同步重采信号。When the multiplier calculation module receives the crystal oscillator frequency correction value sent by the error correction module Afterwards, the accumulated value Baund_inc can be calculated by rounding down the formula (4). Because the accumulator Baund_acc is an unsigned integer, it can ignore its overflow and continuously accumulate in a loop. When each crystal oscillator cycle comes, the accumulator Baund_acc will add Baund_inc to perform an accumulation calculation, and the highest bit output of the accumulator is a synchronous reacquisition signal with a duty cycle of 50%.

因为Baund_inc在计算时向下取整，造成一段时间内累加器计数值偏小，可以在对同步重采信号的零时刻输出误差校正中对计数值进行修正。当倍频计算模块接收到误差校正模块发送的零时刻输出误差值K时，此时累加器Baund_acc的最高位刚刚完成由0到1的转变，生成0号重采信号。将Baund_inc乘以K得到t_o的数字量化值Baund_err。由于Baund_err为重采信号输出滞后的时间值，因此可以通过将累加器计数值Baund_acc加上Baund_err进行延时补偿。考虑到同步重采信号的调整需要实现平稳过渡，为防止相邻两个重采信号之间间隔过小，造成程序运行错误，需要对Baund_err加以限制，当K大于500时，Baund_err为500·Baund_inc。则实现同步重采信号的零时刻输出误差校正需要最长时间为Because Baund_inc is rounded down during calculation, the accumulator count value is relatively small for a period of time, and the count value can be corrected in the zero-time output error correction of the synchronous reacquisition signal. When the frequency doubling calculation module receives the zero-time output error value K sent by the error correction module, the highest bit of the accumulator Baund_acc has just completed the transition from 0 to 1 at this time, generating a No. 0 reacquisition signal. Multiply Baund_inc by K to get the digital quantization value Baund_err of t _o . Since Baund_err is the lag time value of the reacquisition signal output, delay compensation can be performed by adding the accumulator count value Baund_acc to Baund_err. Considering that the adjustment of the synchronous re-acquisition signal needs to achieve a smooth transition, in order to prevent the interval between two adjacent re-acquisition signals from being too small, resulting in program operation errors, Baund_err needs to be limited. When K is greater than 500, Baund_err is 500 · Baund_inc . Then it takes a maximum time of

t_s=F_cry/(500·F_res)=25s （5）t _s =F _cry /(500·F _res )=25s (5)

当PPS脉冲信号接入后，加上3s的PPS判断时间，最多需要28s，即可完全实现重采信号的同步输出。When the PPS pulse signal is connected, plus the PPS judgment time of 3s, it takes up to 28s to fully realize the synchronous output of the re-acquisition signal.

实施例：Example:

同步采样时钟的误差分析：Error analysis of synchronous sampling clock:

该同步采样时钟中由于Baund_inc计算时的取整操作，会在第n个同步重采信号处产生误差：In this synchronous sampling clock, due to the rounding operation during Baund_inc calculation, an error will be generated at the nth synchronous resampling signal:

ξξ 22 == || nno Ff resres -- nno ·· 22 WW BaundBaund __ incinc ·&Center Dot; 11 Ff crycry || -- -- -- (( 66 ))

由于同步时，每秒对重采信号的误差校正一次，所以当n取最大值4000以及Baund_inc取整误差最大为1，即n=4000，时，ξ₂有最大值为Since the error of the reacquisition signal is corrected once per second during synchronization, when n takes the maximum value of 4000 and the Baund_inc rounding error is at most 1, that is, n=4000, , ξ ₂ has a maximum value of

ξξ 22 maxmax == Mm ‾‾ 40004000 ·&Center Dot; 22 WW -- Mm ‾‾ -- -- -- (( 77 ))

不同于式（2）中传统倍频方法的同步重采信号输出误差ξ₁只受晶振精度的影响，由式（7）可知，通过本文方法实现的同步重采信输出最大误差ξ_2max同时受晶振精度与累加器位宽W的影响。因此可以在晶振精度不高，晶振实际振动频率较大时，加大位宽W，来减小ξ_2max。为进一步研究在取最大值5.0001×10⁷时，位宽W的不同取值对ξ_2max的影响情况，同时对Baund_inc计算值及其取整误差百分比δ进行了观察，如表1所示。Different from the traditional frequency multiplication method in formula (2), the synchronous reacquisition signal output error ξ ₁ is only affected by the precision of the crystal oscillator. From formula (7), it can be seen that the synchronous reacquisition signal output maximum error ξ _2max realized by the method in this paper is also affected by the crystal oscillator The effect of precision and accumulator bit width W. Therefore, when the precision of the crystal oscillator is not high, the actual vibration frequency of the crystal oscillator When it is larger, increase the bit width W to reduce ξ _2max . for further research in When the maximum value is 5.0001×10 ⁷ , the influence of different values of the bit width W on ξ _2max is observed, and the calculated value of Baund_inc and its rounding error percentage δ are observed, as shown in Table 1.

表1位宽W不同值对误差值的影响(M=5.0001×10⁷)Table 1 Influence of different values of bit width W on the error value (M=5.0001×10 ⁷ )

WW Baund_incBaund_inc δ(%)δ(%) ξ_2max(μs)ξ _2max (μs) 3232 343590343590 1.48977×10^-4 1.48977×10 ^-4 2.910452.91045 4040 8795917187959171 4.39513×10^-8 4.39513×10 ^-8 1.1369×10^-2 1.1369×10 ^-2 4141 175918342175918342 4.39513×10^-8 4.39513×10 ^-8 5.6845×10^-3 5.6845×10 ^-3 4848 2.25175×10¹⁰ 2.25175×10 ¹⁰ 3.98250×10^-9 3.98250×10 ^-9 4.4410×10^-5 4.4410×10 ^-5 6464 1.47571×10¹⁵ 1.47571×10 ¹⁵ 1.34631×10^-14 1.34631×10 ^-14 6.7764×10^-10 6.7764×10 ^-10

通过表1可以看出，位宽W越大时，Baund_inc对应的计算值也越大，其计算时忽略小数部分产生的取整误差百分比δ也相应越小，因此对应于取整误差造成的ξ_2max也越小。It can be seen from Table 1 that when the bit width W is larger, the calculated value corresponding to Baund_inc is also larger, and the rounding error percentage δ generated by ignoring the fractional part in the calculation is also correspondingly smaller, so corresponding to ξ caused by the rounding error _2max is also smaller.

同步采样时钟的实验研究：Experimental study of synchronous sampling clocks:

利用QuartusⅡ对同步采样时钟进行编程仿真，其时序仿真如图6所示，其中clk为本地晶振时钟输入，PPS_clk为PPS脉冲信号输入，resample_clk为同步重采信号输出，syn与K为内部寄存器变量。当PPS判断模块检测到PPS脉冲信号有效时，同步状态syn变为1，代表已同步。随后误差校正模块对0号重采脉冲信号进行校正，得到其输出误差值K，同时用timebar工具测得重采信号输出滞后PPS脉冲信号17.12μs。由于K为856，大于500，所以在第一次补偿时只补偿了500，当下一个PPS脉冲信号到来后，重新校正到重采脉冲信号的输出误差为356，并进行了补偿。最后同步重采信号与PPS脉冲信号在同时刻触发，其输出相位误差值K为0。Use Quartus II to program and simulate the synchronous sampling clock. The timing simulation is shown in Figure 6, where clk is the local crystal oscillator clock input, PPS_clk is the PPS pulse signal input, resample_clk is the synchronous resampling signal output, and syn and K are internal register variables. When the PPS judging module detects that the PPS pulse signal is valid, the synchronous status syn becomes 1, indicating that it has been synchronized. Then the error correction module corrects the re-acquisition pulse signal No. 0 to obtain its output error value K. At the same time, it is measured with the timebar tool that the re-acquisition signal output lags the PPS pulse signal by 17.12 μs. Since K is 856, which is greater than 500, only 500 is compensated in the first compensation. When the next PPS pulse signal arrives, the output error of the re-sampling pulse signal is recalibrated to 356 and compensated. Finally, the synchronous reacquisition signal and the PPS pulse signal are triggered at the same time, and the output phase error value K is 0.

将该同步采样时钟下载到电子式电流互感器合并单元中，采用江苏凌创NT702电子式互感器稳态校验系统进行了运行测试。晶振为20ppm的普通石英晶振，额定测量电流为5A，在不同电流强度下的合并单元的同步采样数据误差如图7所示。可以看出同步采样数据的比差分布较为均匀集中，在电流较小时，由于白噪声的毛刺干扰，角差波动较大，但总体上可以满足IEEE60044标准0.2S级的精度要求，反映出良好的同步性。The synchronous sampling clock is downloaded to the merging unit of the electronic current transformer, and the operation test is carried out by using the Jiangsu Lingchuang NT702 electronic transformer steady-state verification system. The crystal oscillator is a 20ppm ordinary quartz crystal oscillator, and the rated measurement current is 5A. The synchronous sampling data error of the merging unit under different current intensities is shown in Figure 7. It can be seen that the ratio difference distribution of the synchronous sampling data is relatively uniform and concentrated. When the current is small, the angle difference fluctuates greatly due to the glitch interference of white noise, but it can generally meet the 0.2S level accuracy requirements of the IEEE60044 standard, reflecting a good synchronicity.

本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。Those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.