CN103677040B - A kind of drive circuit of reference voltage - Google Patents
- ️Wed Jul 20 2016
CN103677040B - A kind of drive circuit of reference voltage - Google Patents
A kind of drive circuit of reference voltage Download PDFInfo
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- CN103677040B CN103677040B CN201210362016.8A CN201210362016A CN103677040B CN 103677040 B CN103677040 B CN 103677040B CN 201210362016 A CN201210362016 A CN 201210362016A CN 103677040 B CN103677040 B CN 103677040B Authority
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Abstract
本发明公开了一种参考电压的驱动电路，能够实现较好的PSRR，提高参考电压的建立速度，降低电路的功耗。本发明实施例提供的参考电压的驱动电路包括闭环负反馈环路和开环支路，开环支路中包括NMOS管（M31）和NMOS管（M32）；NMOS管（M31）的漏极连接至电源VDD，NMOS管（M31）的栅极接入闭环负反馈环路所提供的第一偏置电压，NMOS管（M31）的源极输出参考电压Vrp；NMOS管（M32）的漏极与NMOS管（M31）的源极相连接，NMOS管（M32）的栅极接入闭环负反馈环路所提供的第二偏置电压，NMOS管（M32）的源极通过隔离电器件接地，NMOS管（M32）的源极输出参考电压Vrn。
The invention discloses a driving circuit of a reference voltage, which can realize better PSRR, improve the establishment speed of the reference voltage, and reduce the power consumption of the circuit. The driving circuit of the reference voltage provided by the embodiment of the present invention includes a closed-loop negative feedback loop and an open-loop branch, and the open-loop branch includes an NMOS transistor (M31) and an NMOS transistor (M32); the drain connection of the NMOS transistor (M31) To the power supply VDD, the gate of the NMOS transistor (M31) is connected to the first bias voltage provided by the closed-loop negative feedback loop, and the source of the NMOS transistor (M31) outputs the reference voltage Vrp; the drain of the NMOS transistor (M32) is connected to the The source of the NMOS transistor (M31) is connected, the gate of the NMOS transistor (M32) is connected to the second bias voltage provided by the closed-loop negative feedback loop, the source of the NMOS transistor (M32) is grounded through an isolated electrical device, and the NMOS transistor (M32) The source of the tube (M32) outputs the reference voltage Vrn.
Description
Technical field
The present invention relates to circuit development technique field, particularly to the drive circuit of a kind of reference voltage.
Background technology
ADC(Analog-to-DigitalConverter, analog digital conversion) technology realizes converting analog signals into digital signal.From essence, the function of ADC is based on the comparative result of input analogue signal and input reference voltage to export digital coding.The error of reference voltage and noise are all converted into the error of output coding, and the performance of reference voltage directly affects performance and the precision of ADC.For the ADC device of a 12-bit precision, supply voltage 1.8V, if reference voltage range is supply voltage size, then the error of input reference voltage and noise must control within ± 0.4mV.
In actual scene, there are many factors can affect the performance of reference voltage.Such as, in the level circuit of flow line structure ADC, switching capacity (switched-capacitor) circuit extracts electric current from reference voltage driving circuit and realizes the discharge and recharge to electric capacity.On the one hand, switched-capacitor circuit needs stable reference voltage to guarantee its output accuracy, and on the other hand, reference voltage circuit can be introduced bigger transient load again by the high speed switching of switch, causes the shake of reference voltage.In high-speed ADC, the shake of reference voltage must realize stable within the shorter time cycle.Accordingly, it would be desirable to provide the implementation of stable reference voltage for high-speed ADC.
The implementation of existing reference voltage driving circuit is broadly divided into two classes: high impedance realizes technology and Low ESR realizes technology.High impedance realizes technology and generally adopts bigger on and off the chip electric capacity, utilizes bulky capacitor to absorb the change of electric charge to maintain stablizing of voltage.Low ESR realizes technology and depends on the transient current that high speed voltage buffer (buffer) provides bigger.Low ESR realizes the reference voltage that technology is more commonly used under current high-speed ADC and drives implementation.Referring to Fig. 1, show that existing Low ESR realizes the reference voltage driving circuit under technology for ADC, this circuit is driven an open-loop branch 2 to realize by a close loop negative feedback loop 1, reference voltage Vrp and Vrn is driven branch road 2 to export by open loop, and this open loop drives branch road 2 to be driven by close loop negative feedback loop 1.Input voltage Vrpin, Vrnin and Vcmoin are produced by band-gap reference and generating circuit from reference voltage 10, provide accurate magnitude of voltage through unit gain feedback loop 4 and loop 5, then through being exported and provide bigger driving electric current by open-loop branch 2.Reference voltage Vrp is by PMOS(P-ChannelMetalOxideSemiconductor, P-channel metal-oxide-semiconductor) pipe M11 and M12 generation, reference voltage Vrn is by NMOS(N-ChannelMentalOxideSemiconductor, N-channel metal-oxide semiconductor (MOS)) pipe M13 and M14 generation.
Existing reference voltage drive scheme at least has following defects that
Existing high impedance realizes technology to be needed to arrange jumbo off-chip electric capacity.Therefore, chip needs to increase extra chip bonding pad and package pins, and the stray inductance of binding line and off-chip electric capacity can limit reference voltage set up speed.
Existing Low ESR realizes technology, drives branch road generally to be realized by PMOS and NMOS tube.Owing to NMOS tube carrier mobility is more than the mobility of PMOS carrier, the design size of PMOS M11 and M12 is greater than NMOS tube size (such as: in SMIC13 technique, the mobility of electronics is 3 times of hole mobility, therefore 3 times that the design size of PMOS M11 and M12 is NMOS tube M13 and M14 size).Large-sized PMOS can bring bigger parasitic capacitance.On the one hand, the decoupling capacitance 6 of PMOS M11 and the parasitic capacitance of M11 form power line to the coupling path of outfan Vrp, reduce PSRR(PowerSupplyRejectionRatio, PSRR), have impact on circuit performance；On the other hand, the parasitic capacitance of two the PMOS M11 and M12 being connected with Vrp all becomes the capacitive load of output Vrp, causes that reference voltage Vrp's sets up speed relatively slowly, is ensure that certain reference voltage is set up speed and then will necessarily be increased circuit power consumption.
Summary of the invention
The invention provides the drive circuit of a kind of reference voltage, adopt that off-chip capacitive way needs to increase extra chip bonding pad and package pins, introducing stray inductance lowers the problem setting up speed solving existing scheme, and when adopting large scale PMOS, the PSRR of circuit is relatively low, the problem that ensures to cause circuit power consumption excessive when reference voltage sets up speed.
For reaching above-mentioned purpose, the embodiment of the present invention adopts the technical scheme that
The drive circuit of a kind of reference voltage that the embodiment of the present invention provides, described drive circuit includes close loop negative feedback loop and open-loop branch, and described open-loop branch includes NMOS tube M31 and NMOS tube M32；
The drain electrode of NMOS tube M31 is connected to the grid of power vd D, NMOS tube M31 and accesses the first bias voltage that close loop negative feedback loop provides, the source electrode output reference voltage Vrp of NMOS tube M31；
The drain electrode of NMOS tube M32 is connected with the source electrode of NMOS tube M31, and the grid of NMOS tube M32 accesses the second bias voltage that close loop negative feedback loop provides, and the source electrode of NMOS tube M32 is by isolating electrical part ground connection, the source electrode output reference voltage Vrn of NMOS tube M32.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS tube in open-loop branch realizes, avoid when open-loop branch adopts NMOS tube and PMOS simultaneously, the reference voltage needing large-sized PMOS and cause sets up the problem that speed is relatively slow, circuit power consumption is bigger, can quickly set up reference voltage Vrp and Vrn, reduce the power consumption of circuit；Further, in this programme, NMOS tube adopts source class follower to connect, and grid decoupling capacitance is connected to ground, reduces the power line coupling to outfan, it is possible to obtain good PSRR, thus improve circuit performance.
Further, the reference voltage driving circuit of this programme, circuit structure is simple, it is not necessary to the large bulk capacitance of off-chip, both need not increase extra chip bonding pad and package pins, reduce again circuit power consumption, optimizes circuit performance.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the reference voltage drive scheme under existing Low ESR technology；
The circuit diagram of the drive circuit of a kind of reference voltage that Fig. 2 provides for the embodiment of the present invention；
Fig. 3 provides the circuit diagram of the drive circuit of another kind of reference voltage for the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
The drive circuit of the reference voltage of the present embodiment is driven an open-loop branch to realize by a close loop negative feedback loop.Close loop negative feedback loop provides initial reference voltage value accurately, and open-loop branch provides output driving current, produces reference voltage.Referring to Fig. 2, the circuit diagram of the drive circuit of a kind of reference voltage provided for the embodiment of the present invention, this drive circuit includes close loop negative feedback loop and open-loop branch, and described open-loop branch includes NMOS tube M31 and NMOS tube M32；
The drain electrode of NMOS tube M31 is connected to power vd D, the grid of NMOS tube M31 accesses the first bias voltage that close loop negative feedback loop provides, the source electrode output reference voltage Vrp of NMOS tube M31, NMOS tube M31 drain electrode is connected to the connected mode of power vd D and has buffer action, and NMOS tube M31 grid realizes ground decoupling by decoupling capacitance 25, this structure improves the PSRR of circuit.
By upper, NMOS tube M31 drain electrode in the present embodiment, the connected mode of source electrode and grid and grid by decoupling capacitance 25 realize the structure of decoupling have good buffer action, reduce the power line coupling to outfan, improve the PSRR of circuit.
The drain electrode of NMOS tube M32 is connected with the source electrode of NMOS tube M31, and the grid of NMOS tube M32 accesses the second bias voltage that close loop negative feedback loop provides, and the source electrode of NMOS tube M32 is by isolating electrical part ground connection, the source electrode output reference voltage Vrn of NMOS tube M32.
Above-mentioned isolation electrical part can be realized by a NMOS tube, it is also possible to is realized by resistance, and this isolation electrical part is it is not recommended that adopt PMOS to realize.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS tube in open-loop branch realizes, avoid when open-loop branch adopts NMOS tube and PMOS simultaneously, the reference voltage needing large-sized PMOS and cause sets up the problem that speed is relatively slow, circuit power consumption is bigger, can quickly set up reference voltage Vrp and Vrn, reduce the power consumption of circuit；Further, this programme reduces the power line coupling to outfan, it is possible to obtain good PSRR, thus improve circuit performance.
Further, the drive circuit of the reference voltage of this programme, circuit structure is simple, it is not necessary to the large bulk capacitance of off-chip, had both reduced circuit power consumption, has optimized circuit performance, improves again the universal of circuit, it is simple to actually used.
Referring to Fig. 3, provide the circuit diagram of the drive circuit of another kind of reference voltage for the embodiment of the present invention.In the scene of Fig. 3, isolation electrical part is realized by NMOS tube M33, namely only includes NMOS tube in open-loop branch.The grid of NMOS tube M33 accesses the 3rd bias voltage that close loop negative feedback loop provides, the source ground of described NMOS tube M33.
Described close loop negative feedback loop includes branch road 21, and branch road 21 includes NMOS tube M34, NMOS tube M35 and NMOS tube M36, and it is 1:K that branch road 21 is set to the proportionate relationship of the electric current on branch road 21 and the electric current in open-loop branch, wherein,
The drain electrode of NMOS tube M34 is connected to the grid of power vd D, NMOS tube M34 and accesses the first bias voltage and be connected with the grid of NMOS tube M31, and the source electrode of NMOS tube M34 is connected with the drain electrode of NMOS tube M35；
The grid of NMOS tube M35 accesses the second bias voltage and is connected with the grid of NMOS tube M32, and the source electrode of NMOS tube M35 is connected with the drain electrode of NMOS tube M36；
The grid of NMOS tube M36 accesses the 3rd bias voltage and is connected with the grid of NMOS tube M33, the source ground of NMOS tube M36.
Close loop negative feedback loop includes difference transport and placing device 40 and difference transport and placing device 41, and described drive circuit also includes bias current sources, specific as follows:
The difference amplifier positive input terminal of difference transport and placing device 40 accesses initial reference voltage Vrpin(Vrpin and is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS tube M34, the outfan of difference transport and placing device 40 connects one end of electric charge pump 24, the other end of electric charge pump 24 is connected to the grid of NMOS tube M34, provides described first bias voltage to the grid of NMOS tube M34 and NMOS tube M31；
The difference amplifier positive input terminal of difference transport and placing device 41 accesses initial reference voltage Vrnin(Vrnin and is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS tube M35, the outfan of difference transport and placing device 41 is connected to the grid of NMOS tube M35, provides described second bias voltage to the grid of NMOS tube M35 and NMOS tube M32；
The outfan of bias current sources (Ibias) is connected to the drain electrode of NMOS tube M37, the source electrode of NMOS tube M37 is connected with the drain electrode of NMOS tube M38, the source ground of NMOS tube M38, the outfan of bias current sources and the grid of NMOS tube M38 are connected to the grid of NMOS tube M36, provide described 3rd bias voltage to the grid of NMOS tube M36 and NMOS tube M33.
As it is shown on figure 3, ADC reference voltage Vrp and Vrn is exported by open-loop branch 20, this open-loop branch 20 is driven by close loop negative feedback loop 19.Close loop negative feedback loop 19 copies the branch road 21 second level as close loop negative feedback loop using the breadth length ratio relation of 1:K according to open-loop branch 20, here duplication refers to that open-loop branch 20 is identical with quantity with the part category in branch road 21, structure is closely similar, and the proportionate relationship of the electric current of the electric current of branch road 21 and open-loop branch 20 is 1:K, such as, when device in open-loop branch 20 and branch road 21 is all NMOS tube, the proportionate relationship of the breadth length ratio of the NMOS tube in branch road 21 and the breadth length ratio of the NMOS tube of open-loop branch 20 can be set to 1:K, such that it is able to guarantee branch road 21 and open-loop branch 20 corresponding node voltage is equal and size of current relation is 1:K.
Input voltage Vrpin and Vrnin is produced by by band-gap reference and generating circuit from reference voltage 30, the negative feedback characteristic according to loop 22 and loop 23 so that the source voltage values of NMOS tube M34 and NMOS tube M35 is respectively equal to Vrpin and Vrnin.
In order to provide rational DC point to open-loop branch 20 and branch road 21, loop 22 introduces electric charge pump 24.Electric charge pump 24 includes electric capacity C1 and electric capacity C2, one end of electric capacity C1 is switched on or switched off by switching K11 and DC voltage Vbn2 and is switched on or switched off by switching one end of K21 and electric capacity C2, and the other end of electric capacity C1 is switched on or switched off by switching K12 and power vd D and is switched on or switched off by switching the other end of K22 and electric capacity C2；One end of electric capacity C2 is additionally coupled to the outfan of difference transport and placing device 40, and the other end of electric capacity C2 is additionally coupled to the grid of NMOS tube M34.
Clk1 and clk2 is the biphase work clock of electric charge pump, and Vbn2 is DC voltage.Clk1 and clk2 differs, and controls Guan Bi and the unlatching of switch K11 and K12 according to clk1, controls Guan Bi and the unlatching of switch K21 and K22 according to clk2.This electric charge pump makes the first bias voltage of the grid of voltage Vop(access NMOS tube M34) add C1 (VDD-Vbn2)/(C1+C2) than voltage Vop1, the numerical value of the first bias voltage can be adjusted by adjusting Vbn2, thus the first bias voltage that ensure that on the grid of NMOS tube M34 is sufficiently large, to guarantee NMOS tube M31 and M34 normal operation.
M32 and M35 gate voltage is provided by the voltage Von of the outfan of difference transport and placing device 41, M33, M36 and M38, and M32, M35 and M37 constitute current mirror, and Ibias is input bias current, and current mirror provides gate voltage (i.e. the 3rd bias voltage) for M33 and M36.
Optionally, also it is provided with decoupling capacitance 25, decoupling capacitance 26 and decoupling capacitance 27 respectively gate voltage for NMOS tube and realizes pressure stabilization function.Wherein, the grid of NMOS tube M34 is additionally coupled to one end of electric capacity 25, the other end ground connection of electric capacity 25, thus NMOS tube M31 grid can pass through decoupling capacitance 25 and realize ground decoupling, reduces the power line coupling to outfan, improves the PSRR of circuit；The grid of NMOS tube M35 is additionally coupled to one end of electric capacity 26, the other end ground connection of electric capacity 26；The grid of NMOS tube M36 is additionally coupled to one end of electric capacity 27, the other end ground connection of electric capacity 27.
Optionally, the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS tube M34 by resistance R1；The difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS tube M35 by resistance R2.The effect of burning voltage and electric current is played by resistance R1 and resistance R2.
From the above mentioned, the present embodiment is only realized by nmos source follower as the open-loop branch 20 of outfan, and circuit realiration is simple, and can provide bigger driving electric current for reference voltage Vrp and Vrn, sets up realizing reference voltage faster.Nmos source follower in this open-loop branch 20 has good buffer action, it is to avoid the impact of voltage dithering divided ring branch road, it is ensured that the stability of open-loop branch；And reduce the power line coupling to outfan, it is achieved that higher PSRR.Owing to open-loop branch adopts NMOS tube to realize, setting up the requirement of speed for meeting identical output voltage, drive branch road compared to PMOS, the program only needs less design size, thus reducing current drain, has saved power consumption.
Further, the present embodiment adopts NMOS tube M33 as isolation electrical part, and adopt current mirror to provide the mode of gate voltage for NMOS tube M33, it is possible to increase the precision of reference voltage Vrp and the Vrn of output.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS tube in open-loop branch realizes, avoid when open-loop branch adopts NMOS tube and PMOS simultaneously, the reference voltage needing large-sized PMOS and cause sets up the problem that speed is relatively slow, circuit power consumption is bigger, can quickly set up reference voltage Vrp and Vrn, reduce the power consumption of circuit；Further, in this programme, NMOS tube adopts source class follower to connect, and grid decoupling capacitance is connected to ground, reduces the power line coupling to outfan, it is possible to obtain good PSRR, thus improve circuit performance.
Further, the reference voltage driving circuit of this programme, circuit structure is simple, it is not necessary to the large bulk capacitance of off-chip, both need not increase extra chip bonding pad and package pins, reduce again circuit power consumption, optimizes circuit performance.
Shown in the drive circuit of another reference voltage that the embodiment of the present invention provides and Fig. 3, the difference of drive circuit essentially consists in, isolation electrical part adopts resistance R33 to realize, then in Fig. 3, the position of NMOS tube M36 is also adopted by resistance realization, bias current sources Ibias, NMOS tube M37 and M38 in Fig. 3 then can remove, and the miscellaneous part in Fig. 3 remains unchanged.
Concrete, one end of resistance R33 is connected to the source electrode of NMOS tube M32, the other end ground connection of described resistance R33.
Close loop negative feedback loop includes branch road 21, branch road 21 includes NMOS tube M34, NMOS tube M35 and resistance R36, the proportionate relationship being made electric current that branch road 21 is set on branch road 21 and the electric current in open-loop branch by the setting to the breadth length ratio of NMOS tube and the setting to resistance is 1:K, wherein
The drain electrode of NMOS tube M34 is connected to the grid of power vd D, NMOS tube M34 and accesses the first bias voltage and be connected with the grid of NMOS tube M31, and the source electrode of NMOS tube M34 is connected with the drain electrode of NMOS tube M35；
The grid of NMOS tube M35 accesses the second bias voltage and is connected with the grid of NMOS tube M32, and the source electrode of NMOS tube M35 is connected with one end of resistance R36；
The other end ground connection of resistance R36.
The difference amplifier positive input terminal of difference transport and placing device 40 accesses initial reference voltage Vrpin(Vrpin and is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS tube M34, the outfan of difference transport and placing device 40 connects one end of electric charge pump 24, the other end of electric charge pump 24 is connected to the grid of NMOS tube M34, provides described first bias voltage to the grid of NMOS tube M34 and NMOS tube M31；
The difference amplifier positive input terminal of difference transport and placing device 41 accesses initial reference voltage Vrnin(Vrnin and is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS tube M35, the outfan of difference transport and placing device 41 is connected to the grid of NMOS tube M35, provides described second bias voltage to the grid of NMOS tube M35 and NMOS tube M32.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS tube in open-loop branch realizes, avoid when open-loop branch adopts NMOS tube and PMOS simultaneously, the reference voltage needing large-sized PMOS and cause sets up the problem that speed is relatively slow, circuit power consumption is bigger, can quickly set up reference voltage Vrp and Vrn, reduce the power consumption of circuit；Further, this programme reduces the power line coupling to outfan, it is possible to obtain good PSRR, thus improve circuit performance.
Further, the drive circuit of the reference voltage of this programme, circuit structure is simple, it is not necessary to the large bulk capacitance of off-chip, had both reduced circuit power consumption, has optimized circuit performance, improves again the universal of circuit, it is simple to actually used.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit protection scope of the present invention.All make within the spirit and principles in the present invention any amendment, equivalent replacement, improvement etc., be all contained in protection scope of the present invention.
Claims (9)
1. the drive circuit of a reference voltage, it is characterised in that described drive circuit includes close loop negative feedback loop and open-loop branch, described open-loop branch includes N-channel metal-oxide semiconductor (MOS) NMOS tube M31 and NMOS tube M32；
The drain electrode of NMOS tube M31 is connected to the grid of power vd D, NMOS tube M31 and accesses the first bias voltage that close loop negative feedback loop provides, the source electrode output reference voltage Vrp of NMOS tube M31；
The drain electrode of NMOS tube M32 is connected with the source electrode of NMOS tube M31, and the grid of NMOS tube M32 accesses the second bias voltage that close loop negative feedback loop provides, and the source electrode of NMOS tube M32 is by isolating electrical part ground connection, the source electrode output reference voltage Vrn of NMOS tube M32；
Described close loop negative feedback loop includes branch road (21), difference transport and placing device 40, difference transport and placing device 41 and electric charge pump (24), and branch road (21) includes NMOS tube M34 and NMOS tube M35；
The difference amplifier positive input terminal of difference transport and placing device 40 accesses initial reference voltage Vrpin, the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS tube M34, the outfan of difference transport and placing device 40 connects one end of electric charge pump (24), the other end of electric charge pump (24) is connected to the grid of NMOS tube M34, provides described first bias voltage to the grid of NMOS tube M34 and NMOS tube M31；
The difference amplifier positive input terminal of difference transport and placing device 41 accesses initial reference voltage Vrnin, the difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS tube M35, the outfan of difference transport and placing device 41 is connected to the grid of NMOS tube M35, provides described second bias voltage to the grid of NMOS tube M35 and NMOS tube M32；
The drain electrode of NMOS tube M34 is connected to the grid of power vd D, NMOS tube M34 and accesses the first bias voltage and be connected with the grid of NMOS tube M31, and the source electrode of NMOS tube M34 is connected with the drain electrode of NMOS tube M35；
The grid of NMOS tube M35 accesses the second bias voltage and is connected with the grid of NMOS tube M32.
2. drive circuit according to claim 1, it is characterised in that
Described isolation electrical part is NMOS tube M33, and the drain electrode of described NMOS tube M33 is connected to the source electrode of NMOS tube M32, and the grid of described NMOS tube M33 accesses the 3rd bias voltage that close loop negative feedback loop provides, the source ground of described NMOS tube M33.
3. drive circuit according to claim 2, it is characterized in that, also include NMOS tube M36 in described branch road (21), it is 1:K that branch road (21) is set to the proportionate relationship of the electric current on branch road (21) and the electric current in open-loop branch, wherein
The grid of NMOS tube M36 accesses the 3rd bias voltage and is connected with the grid of NMOS tube M33, and the drain electrode of NMOS tube M36 is connected with the source electrode of NMOS tube M35, the source ground of NMOS tube M36.
4. drive circuit according to claim 3, it is characterised in that described drive circuit also includes bias current sources,
The outfan of bias current sources is connected to the drain electrode of NMOS tube M37, and the source electrode of NMOS tube M37 is connected with the drain electrode of NMOS tube M38, the source ground of NMOS tube M38,
The outfan of bias current sources and the grid of NMOS tube M38 are connected to the grid of NMOS tube M36, provide described 3rd bias voltage to the grid of NMOS tube M36 and NMOS tube M33.
5. drive circuit according to claim 4, it is characterised in that
The difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS tube M34 by resistance R1；
The difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS tube M35 by resistance R2.
6. drive circuit according to claim 4, it is characterised in that
The grid of NMOS tube M34 is additionally coupled to one end of electric capacity 25, the other end ground connection of electric capacity 25；
The grid of NMOS tube M35 is additionally coupled to one end of electric capacity 26, the other end ground connection of electric capacity 26；
The grid of NMOS tube M36 is additionally coupled to one end of electric capacity 27, the other end ground connection of electric capacity 27.
7. drive circuit according to claim 4, it is characterised in that described electric charge pump (24) includes electric capacity C1 and electric capacity C2,
One end of electric capacity C1 is switched on or switched off by switching K11 and DC voltage Vbn2 and is switched on or switched off by switching one end of K21 and electric capacity C2, and the other end of electric capacity C1 is switched on or switched off by switching K12 and power vd D and is switched on or switched off by switching the other end of K22 and electric capacity C2；
One end of electric capacity C2 is additionally coupled to the outfan of difference transport and placing device 40, and the other end of electric capacity C2 is additionally coupled to the grid of NMOS tube M34.
8. drive circuit according to claim 1, it is characterised in that described isolation electrical part is resistance R33, one end of described resistance R33 is connected to the source electrode of NMOS tube M32, the other end ground connection of described resistance R33.
9. drive circuit according to claim 8, it is characterized in that, also include resistance R36 in described branch road (21), it is 1:K that branch road (21) is set to the proportionate relationship of the electric current on branch road (21) and the electric current in open-loop branch, wherein
One end of resistance R36 is connected with the source electrode of NMOS tube M35, other end ground connection.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210362016.8A CN103677040B (en) | 2012-09-25 | 2012-09-25 | A kind of drive circuit of reference voltage |
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| CN201210362016.8A CN103677040B (en) | 2012-09-25 | 2012-09-25 | A kind of drive circuit of reference voltage |
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| CN103677040A CN103677040A (en) | 2014-03-26 |
| CN103677040B true CN103677040B (en) | 2016-07-20 |
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| CN105049047B (en) * | 2015-08-28 | 2019-03-08 | 西安启微迭仪半导体科技有限公司 | A kind of driving circuit of analog-digital converter reference voltage |
| CN105049041B (en) * | 2015-08-28 | 2018-12-25 | 西安启微迭仪半导体科技有限公司 | Low-power consumption piece internal reference Voltag driving circuit applied to high-speed AD converter |
| CN108874006B (en) * | 2017-05-10 | 2020-03-24 | 深圳清华大学研究院 | Reference voltage driving circuit |
| CN108563276B (en) * | 2018-06-01 | 2020-05-26 | 电子科技大学 | A high-speed reference voltage buffer with cross-coupling filter network |
| CN111367341B (en) * | 2018-12-26 | 2022-07-01 | 北京兆易创新科技股份有限公司 | Reference voltage generating circuit and NAND chip |
| CN112234990A (en) * | 2020-11-18 | 2021-01-15 | 润石芯科技(深圳)有限公司 | Multi-reference driven pipelined ADC architecture |
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