CN103677916A - On-line reconfiguration system and method based on FPGA - Google Patents

The invention discloses an on-line reconfiguration system and method based on an FPGA. The method is achieved mainly through the FPGA. A standard communication interface module, a memory control module, a high-performance embedded processor core, a reconfiguration function module, a reconfiguration control module and an output interface control module are achieved in the FPGA. A high-performance processor embedded into the FPGA is used for being in communication with an upper computer, locally and dynamically configuring the reconfiguration module in the FPGA and transmitting corresponding data to the reconfiguration hardware function module according to different hardware functions, and processed data are output to a peripheral interface unit through the output interface control module. By adopting the on-line reconfiguration system and method based on the FPGA, time division multiplexing of various hardware function modules with different functions can be achieved, the utilization ratio of resources in the FPGA of an embedded processing system is improved, and complex hardware function circuits can be achieved through less hardware resources.

A kind of online reconfiguration system and method based on FPGA

Technical field

The invention belongs to embedded processing systems designing technique, particularly relate to a kind of online reconfiguration system and method based on FPGA.

Background technology

In embedded processing systems, require system must there is the ability of processing within the predetermined time mass data, to guarantee the real-time of system.Meanwhile, embedded processing technology also has stricter requirement to the volume of system, power consumption, stability etc.Thereby FPGA is widely used because of the distinguishing feature that it has high integration, high speed and high reliability in embedded processing.

Because the hardware capability module of embedded processing systems has a large amount of data to need system to process it when realizing, while therefore using FPGA to realize hardware capability module, module amount is generally all larger.Simultaneously; the corresponding hardware capabilitys of data source different in system is also different; in traditional embedded processing systems, tend to realize a plurality of hardware capability modules with difference in functionality in a slice FPGA; and these hardware module circuit with difference in functionality often not can with time move; the scale of FPGA modular circuit can increase along with the increase of system complexity like this, yet the resource utilization of FPGA inside declines along with the increase of system scale complexity on the contrary.

Summary of the invention

The object of this invention is to provide a kind of online reconfiguration system based on FPGA, utilize FPGA reconfiguration technology, realize the multiple time division multiplex with the hardware capability module of difference in functionality.

Technical scheme of the present invention is:

An online reconfiguration system based on FPGA, comprises Upper system, fpga chip, processor, interface unit, storer, communication interface, and its special character is:

Described fpga chip comprises memory control module, communications interface control module, reshuffles hardware capability module, reshuffles control module, Output Interface Control module,

Described memory control module, communications interface control module, reshuffle hardware capability module, reshuffle control module and be connected with processor respectively,

The input end of described Output Interface Control module is connected with the output terminal of reshuffling hardware capability module, and the output terminal of described Output Interface Control module is connected with the input end of interface unit,

Described Upper system is connected with communications interface control module by communication interface, and described storer is connected with memory control module.

The above-mentioned hardware capability module of reshuffling is connected with processor bus by bus transfer interface,

Described bus transfer interface comprises processor bus interface and reshuffles application interface,

Described processor bus interface is used for the data in bus, address and control information to be transferred to and to reshuffle interface section,

The described interface section of reshuffling comprises state controller, status register, I/O FIFO and interrupt request,

Described state controller is connected with processor bus interface,

The input end of described status register is connected with state controller, the running status of collecting for store status controller, and the output of described status register is connected with processor by processor bus interface,

The input end of described input FIFO is connected with processor by processor bus interface, the described output of inputting FIFO with reshuffle hardware capability module and be connected,

The input end of described output FIFO with reshuffle hardware capability module and be connected, the described output terminal of exporting FIFO is connected with processor by processor bus interface,

The input of described interrupt request is connected with the output of state controller, and the output of described interrupt request is connected with processor by processor bus.

Above-mentioned processor is the embedded processor core of FPGA, and described processor core is a kind of in processor soft core or processor stone.

Above-mentioned processor core with memory control module, communications interface control module, reshuffle hardware capability module, reshuffle to control and be connected by bus on chip.

Above-mentioned bus on chip is a kind of in PLB bus or AXI bus.

An online reconfiguration method based on FPGA, its special character is: comprise the following steps:

1] FPGA interior zone is divided into static storage area and reconfigurable region;

2] FPGA is reshuffled to the local bit stream file of using and store, described local bit stream file comprises reshuffles the required different hardware configurations information of functional module in reconfiguration course;

3] from Upper system, obtain raw data;

4] type of Upper system judgement to the needed hardware configuration information of original data processing;

5] Upper system checks the current hardware configuration information of FPGA and running status; If current configuration information can meet step 3] in the processing of the raw data obtained, without carrying out FPGA, reshuffle, otherwise, to FPGA, send reconfigure command and stop the transmission of data source, carry out step 6];

6] FPGA reshuffles;

Processor is chosen corresponding hardware configuration information, and hardware configuration information is write and reshuffled in control module, and utilize and to reshuffle the processing requirements that local dynamic station that control module completes counterweight configuring area reshuffles to meet raw data,

7] utilize the FPGA after configuration to process raw data.

Compared with prior art, advantage is in the present invention:

1, the present invention in FPGA internal separation one reshuffle region, realize the multiple time division multiplex with the hardware capability module of difference in functionality, improved the utilization rate of FPGA internal resource in embedded processing systems, reduced system development costs, utilize FPGA Local Gravity And configuring technical, can in the operational process of system, complete the online reconfiguration to hardware capability, can realize more complicated hardware capability circuit with less hardware resource.

2, the embedded high-performance processor of host computer and FPGA communicates by Ethernet, guarantees real-time and the high efficiency of data transmission;

3, adopt FPGA reconfiguration technology, multiple different hardware capability is realized in same physical region, improve FPGA resource utilization, improve the dirigibility of system;

4, there is unified bus transfer interface, simplified and reshuffled communicating by letter between functional module and bus on chip;

5, system hardware realization is simple, working stability is reliable.

Accompanying drawing explanation

Fig. 1 is theory diagram of the present invention;

Fig. 2 is module principle block diagram in the specific embodiment of the invention;

Fig. 3 is bus interface theory diagram in the specific embodiment of the invention.

Embodiment

Online reconfiguration technology based on FPGA, the main FPGA of employing realizes, and has realized standard communication interface module, storer control module, high performance flush bonding processor core, reshuffles functional module, reshuffles control module and Output Interface Control module in FPGA inside.Host computer transfers to FPGA by data source by standard communication interface (such as Ethernet, serial ports etc.), the embedded high-performance processor of FPGA is responsible for and the communicating by letter and the functional module of reshuffling of FPGA inside is carried out local dynamic station and reshuffled of host computer, and can be according to different hardware capabilitys by corresponding data transmission to reshuffling hardware capability module, data after treatment export peripheral interface units to by Output Interface Control module.

With a specific embodiment, the invention will be further described below:

1. system architecture

Online reconfiguration system based on FPGA, comprise Upper system, fpga chip, processor, interface unit, storer, communication interface, fpga chip comprises memory control module, communication interface modules, reshuffle hardware capability module, reshuffle control module, Output Interface Control module, memory control module, communications interface control module, reshuffle hardware capability module, reshuffling control module is connected with processor respectively, the input end of Output Interface Control module is connected with the output terminal of reshuffling hardware capability module, the output terminal of Output Interface Control module is connected with the input end of interface unit, Upper system is connected with communications interface control module by communication interface, storer is connected with memory control module.

The high-performance PowerPC processor core that processor adopting FPGA is embedded, what storer was selected is Flash storer, communication interface is selected RS232 and Ethernet, FPGA has realized inside FLASH control module, URAT control module, ethernet control module and ICAP interface module, wherein ethernet control module is responsible for communicating by letter of FPGA and host computer, and host computer transfers to FPGA by ICP/IP protocol by data source; Output Interface Control module is responsible for the data after processing to be sent to peripheral interface units, and peripheral interface units is for exporting the result after reshuffling; Reshuffling hardware capability module is a functional module operating in the Local Gravity And configuring area that FPGA internal separation is good, internal configurations access interface (Internal Configuration Access Port, ICAP) module can be configured to above-mentioned Local Gravity And configuring area the hardware module circuit of difference in functionality according to different system requirements, ICAP interface is responsible for receiving the Local Gravity And configuration bitstream file that PowerPC processor sends in system, thereby will reshuffle area configurations, becomes corresponding hardware capability circuit.For the interactive interface between unified different hardware function module circuit and processor, in FPGA inside, also realized the transmission interface for PLB bus.

2. bus transfer interface

For simplifying, reshuffle communicating by letter between hardware capability module and PLB bus, also to have realized a bus transfer interface module in FPGA, this part of module by PLB bus interface partly and reshuffle application interface and partly form.Wherein the effect of PLB bus interface part is that the data of PLB bus, address and control information are passed to and reshuffle interface section; Reshuffle interface section and formed by state controller, I/O FIFO and interrupt request three parts, as shown in Figure 2.

Reshuffling the functional area of reshuffling that the state controller in interface section is outside provides concrete control signal and periodically collects the running status of reshuffling functional area, and the running status of collecting is stored in inner status register, CPU just can play by accessing this register the effect that monitors the running status of reshuffling region; I/O FIFO is for the buffering of data input and output, and the data on data bus are transferred to and reshuffled region by output FIFO, and the data after completing by hardware capability processing of circuit are sent to peripheral interface units.For versatility, consider, also realized an input FIFO in bus interface module, the operation result of reshuffling region can also transfer on data bus by input FIFO.The function of interrupt request part be after receiving the result of reshuffling functional module to interrupt request of CPU, allow CPU export in time the data result in buffering.

3. system treatment scheme

System is by host computer Real-time Obtaining raw data, and utilize ICP/IP protocol to transfer to FPGA, on the embedded PowerPC processor core of FPGA, moving an Ethernet oracle listener, when listening to host computer and having data source to transmit, PowerPC is just sent to by PLB bus the data of receiving reshuffle function module circuit, after part of module circuit is being finished dealing with, the data after processing is exported to the result after reshuffling in peripheral interface unit by Output Interface Control module.

Host computer, when sending raw data to FPGA, also needs judgement need to adopt which kind of hardware configuration information to realize to this section of raw data, for example data processing function circuit, image processing function circuit etc.Certainly, these hardware configuration informations are to realize with checking and completing in advance, and according to this online reconfiguration system, generated, be to carry out for FPGA the local bit stream file of Local Gravity And configuration simultaneously.These local bit stream files are stored in the high-capacity FLASH of FPGA outside.In FPGA inside, realized a status register based on hardware capability, can be by the function information of current FPGA internal configurations and running status by RS232 interface notice host computer, host computer determines whether to need that this part hardware capability is carried out to local dynamic station again and reshuffles afterwards.If needed, host computer sends a reconfigure command and stops the transmission of data source to FPGA, FPGA is after receiving this reconfigure command, PowerPC chooses corresponding local bit stream file and local bit stream file is write in ICAP interface in FLASH, and the local dynamic station that is completed counterweight configuring area by ICAP interface is reshuffled.Configured rear notice host computer, host computer transfers to FPGA by ICP/IP protocol by corresponding data source again.