CN103680602B - Resistive random access memory and reset operation method thereof - Google Patents

本发明涉及微电子技术领域，具体涉及一种阻变存储器及其复位操作方法，其中，阻变存储器包括控制电路、写电压产生电路和电流检测电路；采用连续阶梯状脉冲对阻变存储器进行复位操作；本发明的阻变存储器在复位操作过程中去除了验证操作，保证了复位的良率不降低，又缩短了复位的操作时间，具有良好的应用价值。

The present invention relates to the technical field of microelectronics, in particular to a resistive variable memory and a reset operation method thereof, wherein the resistive variable memory includes a control circuit, a write voltage generating circuit and a current detection circuit; the resistive variable memory is reset by adopting continuous ladder pulses Operation: The resistive memory of the present invention eliminates the verification operation during the reset operation, which ensures that the reset yield is not reduced, and shortens the reset operation time, which has good application value.

一种阻变存储器及其复位操作方法A resistive memory and its reset operation method

技术领域technical field

本发明属于微电子技术领域，具体涉及一种阻变存储器（Resistive SwitchingMemory）及其复位操作方法。The invention belongs to the technical field of microelectronics, and in particular relates to a resistive switching memory (Resistive Switching Memory) and a reset operation method thereof.

背景技术Background technique

阻变存储器又称为电阻型存储器，其基于具有电阻转换功能的存储层进行信息存储。通常，阻变存储器的操作包括读（Read）操作、置位（Set）操作和复位（Reset）操作等，其中，置位操作为由高阻态向低阻态转变的过程，复位操作为由低阻态向高阻态转变的过程。Resistive memory, also known as resistive memory, stores information based on a memory layer with a resistance switching function. Usually, the operation of RRAM includes read (Read) operation, set (Set) operation and reset (Reset) operation, etc., wherein, the set operation is the process of changing from a high resistance state to a low resistance state, and the reset operation is by The transition from a low-resistance state to a high-resistance state.

现有阻变存储器的置位操作普遍采用固定单脉冲激励，即SVP（single voltagepulse）方法。复位操作采用幅度逐渐增加的离散脉冲序列（包括多个几个激励脉冲），并在每个激励脉冲之后进行验证操作（例如偏置小幅度的验证脉冲），若复位成功，则停止施加激励，否则施加幅度更大的激励脉冲，该方法通常称为RPS（ramped-pulse series,write-verify-write）方法，或者在此基础上引入反馈机制，在复位过程中，若单元电阻复位成功，则快速去掉单元上的激励，然后经验证操作确保复位成功，否则施加幅度更大的激励脉冲，即RPS&SAWM（ramped-pulse series&self-adaptive write mode）方法。The setting operation of the existing resistive memory generally adopts a fixed single pulse excitation, that is, the SVP (single voltage pulse) method. The reset operation adopts a discrete pulse sequence with gradually increasing amplitude (including several excitation pulses), and a verification operation is performed after each excitation pulse (such as a verification pulse with a small offset). If the reset is successful, stop applying the excitation. Otherwise, an excitation pulse with a larger amplitude is applied. This method is usually called the RPS (ramped-pulse series, write-verify-write) method, or a feedback mechanism is introduced on this basis. During the reset process, if the unit resistance is successfully reset, then Quickly remove the excitation on the unit, and then verify the operation to ensure that the reset is successful, otherwise apply a larger excitation pulse, that is, the RPS&SAWM (ramped-pulse series&self-adaptive write mode) method.

然而，对于采用SVP实现置位的方法，若阻变存储单元电阻置位成功时该固定单脉冲激励仍施加，将会在低阻状态下产生较大电流，带来较大的功耗;对于采用RPS实现复位的方法，在每个激励脉冲施加过程中，若阻变存储单元电阻复位成功时激励仍施加，单元电阻可能被置位回去导致复位失败，从而使复位操作的良率不高。相比于采用RPS实现复位的方法，采用RPS&SAWM实现复位的方法，置位操作功耗得到节省，复位良率也获得大幅提升，但复位操作过程中的反馈本身有验证功能，每个复位激励脉冲后再有验证操作导致复位操作时间较长。However, for the method of using SVP to realize setting, if the fixed single-pulse excitation is still applied when the resistance of the resistive memory unit is successfully set, a large current will be generated in a low-resistance state, resulting in large power consumption; for Using the RPS reset method, during the application of each excitation pulse, if the excitation is still applied when the resistance of the resistive memory cell is successfully reset, the cell resistance may be set back and the reset fails, so that the yield of the reset operation is not high. Compared with the method of using RPS to realize the reset, the method of using RPS&SAWM to realize the reset can save the power consumption of the set operation, and the reset yield rate has also been greatly improved. However, the feedback itself during the reset operation has a verification function, and each reset excitation pulse Afterwards, there is a verification operation, which results in a longer reset operation time.

发明内容Contents of the invention

本发明的目的就是克服现有技术因阻变存储的复位过程中的验证操作导致复位操作时间过长，而提出的一种阻变存储器及其复位操作方法。The object of the present invention is to overcome the excessively long reset operation time caused by the verification operation in the reset process of the resistive memory in the prior art, and propose a resistive memory and a reset operation method thereof.

为实现以上目的或者其他目的，按照发明的一方面，提供一种阻变存储器的复位操作方法，该复位操作方法包括如下步骤：In order to achieve the above purpose or other purposes, according to an aspect of the invention, a reset operation method of a resistive variable memory is provided, and the reset operation method includes the following steps:

选中需要进行复位的存储单元；Select the storage unit that needs to be reset;

向需要复位的存储单元施加连续阶梯状脉冲；Apply continuous step-like pulses to the memory cells that need to be reset;

根据存储单元的阻态变化判断复位是否成功，若复位成功则根据电流变化产生的反馈信号及时停止施加连续阶梯状脉冲，否则继续施加所述连续阶梯状脉冲。Judging whether the reset is successful according to the resistance state change of the storage unit, if the reset is successful, stop applying the continuous step pulse in time according to the feedback signal generated by the current change, otherwise continue to apply the continuous step pulse.

进一步，所述连续阶梯状脉冲的极性相对置位操作所使用的脉冲信号的极性可以相同或者相反。Further, the polarity of the continuous step-shaped pulse may be the same or opposite to that of the pulse signal used in the set operation.

优选地，所述连续阶梯状脉冲的最高脉冲高度Vn被选择为使所述阻变存储器的存储阵列的存储单元复位成功率能达到预定值的电压值。Preferably, the highest pulse height Vn of the continuous step-shaped pulses is selected as a voltage value at which the memory cells of the memory array of the resistive change memory can be reset with a success rate reaching a predetermined value.

优选地，所述连续阶梯状脉冲中的每个阶梯的阶梯宽度相等。Preferably, the step width of each step in the continuous step-like pulses is equal.

为实现以上目的或者其他目的，按照发明的又一方面，提供一种阻变存储器，该阻变存储器包括控制电路（110）、写电压产生电路（120）和包括多个存储单元的存储阵列（170），还包括电流检测电路（140）；In order to achieve the above object or other objects, according to another aspect of the invention, a resistive variable memory is provided, which includes a control circuit (110), a write voltage generation circuit (120) and a memory array ( 170), further comprising a current detection circuit (140);

其中，所述控制电路（110）控制写电压产生电路（120）向需要复位的存储单元施加连续阶梯状脉冲，电流检测电路（140）将检测到的写通路的电流变化的反馈信号发送给控制电路（110）；Wherein, the control circuit (110) controls the write voltage generation circuit (120) to apply continuous step-like pulses to the memory cells that need to be reset, and the current detection circuit (140) sends the feedback signal of the detected current change of the write path to the control circuit(110);

其中，对该阻变存储器进行复位操作时，若所述反馈信号表示复位成功时，控制电路（110）根据复位成功的反馈信号控制写电压产生电路（120）停止施加所述连续阶梯状脉冲，若所述反馈信号表示复位失败时，控制电路（110）根据复位失败的反馈信号控制写电压产生电路（120）继续施加所述的连续阶梯状脉冲。Wherein, when performing a reset operation on the resistive variable memory, if the feedback signal indicates that the reset is successful, the control circuit (110) controls the write voltage generating circuit (120) to stop applying the continuous step-shaped pulse according to the feedback signal of a successful reset, If the feedback signal indicates reset failure, the control circuit (110) controls the writing voltage generating circuit (120) to continue applying the continuous step-shaped pulse according to the feedback signal of reset failure.

按照本发明第一实施例的阻变存储器，其中，还包括极性选择电路（150）、电流调节器（180）列和选通电路（160）；The RRAM according to the first embodiment of the present invention further includes a polarity selection circuit (150), a current regulator (180) column, and a gate circuit (160);

其中，电流调节器（180）主要由运算放大器（130）和NMOS管组成；控制电路（110）的输出端分别与写电压产生电路（120）的输入端和极性选择电路（150）的输入端相连，写电压产生电路（120）的输出端与电流调节器（180）中的运算放大器（130）的正向输入端相连，电流调节器（180）中运算放大器（130）的负向输入端与极性选择电路（150）相连，极性选择电路（150）的输出端分别与列选通电路（160）的输入端和存储阵列（170）的源线相连，列选通电路（160）的输出端与存储阵列（170）的位线相连，电流检测电路（140）根据电流调节器（180）中流经所述NMOS管的电流的变化产生相应的所述反馈信号发送到控制电路（110）的输入端。Among them, the current regulator (180) is mainly composed of an operational amplifier (130) and an NMOS tube; the output terminal of the control circuit (110) is connected to the input terminal of the write voltage generation circuit (120) and the input terminal of the polarity selection circuit (150) respectively. The output terminal of the write voltage generation circuit (120) is connected to the positive input terminal of the operational amplifier (130) in the current regulator (180), and the negative input terminal of the operational amplifier (130) in the current regulator (180) terminal is connected to the polarity selection circuit (150), the output terminal of the polarity selection circuit (150) is respectively connected to the input terminal of the column gating circuit (160) and the source line of the storage array (170), and the column gating circuit (160 ) is connected to the bit line of the storage array (170), and the current detection circuit (140) generates the corresponding feedback signal according to the change of the current flowing through the NMOS tube in the current regulator (180) and sends it to the control circuit ( 110) input terminal.

按照本发明第二实施例的阻变存储器，其中，还包括编程开关（250）、电流调节器（180）列和选通电路（160）；The resistive memory according to the second embodiment of the present invention further includes a program switch (250), a current regulator (180) column and a gate circuit (160);

其中，电流调节器（180）主要由运算放大器（130）和NMOS管组成；控制电路（110）的输出端分别与写电压产生电路（120）的输入端和编程开关（250）的输入端相连，写电压产生电路（120）的输出端与电流调节器（180）中的运算放大器（130）的正向输入端相连，电流调节器（180）中运算放大器（130）的负向输入端与编程开关（250）相连，编程开关（250）的输出端与列选通电路（160）的输入端连接，列选通电路（160）的输出端与存储阵列（170）的位线相连，存储阵列（170）的源线接地，电流检测电路（140）根据电流调节器（180）中流经所述NMOS管的电流的变化产生相应的所述反馈信号发送到控制电路（110）的输入端。Among them, the current regulator (180) is mainly composed of an operational amplifier (130) and an NMOS tube; the output terminal of the control circuit (110) is respectively connected to the input terminal of the write voltage generating circuit (120) and the input terminal of the programming switch (250) , the output terminal of the write voltage generating circuit (120) is connected to the positive input terminal of the operational amplifier (130) in the current regulator (180), and the negative input terminal of the operational amplifier (130) in the current regulator (180) is connected to the The programming switch (250) is connected, the output end of the programming switch (250) is connected with the input end of the column gating circuit (160), the output end of the column gating circuit (160) is connected with the bit line of the memory array (170), and the storage The source line of the array (170) is grounded, and the current detection circuit (140) generates the corresponding feedback signal according to the change of the current flowing through the NMOS tube in the current regulator (180) and sends it to the input terminal of the control circuit (110).

为实现以上目的或者其他目的，按照发明的还一方面，提供一种对以上所述及的第一实施例的阻变存储器进行复位操作的方法，其包括如下步骤：In order to achieve the above objects or other objects, according to another aspect of the invention, there is provided a method for resetting the resistive memory of the above-mentioned first embodiment, which includes the following steps:

（1）控制电路根据写入数据DATA、写使能信号WEN和反馈信号FB产生使能信号EN；(1) The control circuit generates the enable signal EN according to the write data DATA, the write enable signal WEN and the feedback signal FB;

（2）若使能信号EN有效，极性选择电路正常工作，写电压产生电路产生连续阶梯状脉冲，转步骤（3）；若使能信号EN无效，写电压产生电路和极性选择电路的输出均为零，复位结束；(2) If the enable signal EN is valid, the polarity selection circuit works normally, and the write voltage generation circuit generates continuous ladder pulses, then go to step (3); if the enable signal EN is invalid, the write voltage generation circuit and the polarity selection circuit The output is all zero, and the reset is over;

（3）连续阶梯状脉冲通过电流调节器把相应的写电压Vw输出给极性选择电路，极性选择电路根据写入的数据DATA和使能信号EN将写电压Vw施加到存储阵列的源线，将零电压通过列选通电路施加到存储阵列的位线，对阻变存储器进行复位；同时，电流检测电路对电流调节器的反映写通路的电流Iw进行检测；(3) The continuous ladder pulse outputs the corresponding write voltage Vw to the polarity selection circuit through the current regulator, and the polarity selection circuit applies the write voltage Vw to the source line of the memory array according to the written data DATA and the enable signal EN , applying zero voltage to the bit line of the memory array through the column gate circuit to reset the resistive variable memory; at the same time, the current detection circuit detects the current Iw reflecting the write path of the current regulator;

（4）若复位成功，存储单元的存储电阻的阻值发生改变，电流调节器的电流Iw相应地发生变化，电流检测电路将电流Iw发生变化的反馈信号FB发送给控制电路，控制电路根据该反馈信号FB使使能信号EN无效，转步骤（1）；(4) If the reset is successful, the resistance value of the storage resistor of the storage unit changes, and the current Iw of the current regulator changes accordingly, and the current detection circuit sends the feedback signal FB of the change of the current Iw to the control circuit, and the control circuit according to this The feedback signal FB makes the enable signal EN invalid, go to step (1);

若复位失败，阻变存储单元的存储电阻阻值不发生改变，电流调节器的电流Iw未改变，电流检测电路将电流Iw未发生变化的反馈信号FB发送给控制电路，控制电路根据该反馈信号FB使使能信号EN有效，转步骤（1）。If the reset fails, the resistance value of the storage resistance of the resistive storage unit does not change, the current Iw of the current regulator does not change, the current detection circuit sends the feedback signal FB that the current Iw does not change to the control circuit, and the control circuit according to the feedback signal FB enables the enable signal EN to be valid, go to step (1).

为实现以上目的或者其他目的，按照发明的再一方面，提供一种对以上所述及的第二实施例的阻变存储器进行复位操作的方法，其包括如下步骤：In order to achieve the above objects or other objects, according to another aspect of the invention, a method for resetting the resistive memory of the second embodiment mentioned above is provided, which includes the following steps:

（1）控制电路根据写入数据DATA、写使能信号WEN和反馈信号FB产生使能信号EN；(1) The control circuit generates the enable signal EN according to the write data DATA, the write enable signal WEN and the feedback signal FB;

（2）若使能信号EN有效，编程开关正常工作，写电压产生电路产生连续阶梯状脉冲，转步骤（3）；若使能信号EN无效，写电压产生电路和编程开关的输出均为零，复位结束；(2) If the enable signal EN is valid, the programming switch works normally, and the writing voltage generating circuit generates continuous ladder pulses, then go to step (3); if the enabling signal EN is invalid, the output of the writing voltage generating circuit and the programming switch are both zero , the reset ends;

（3）连续阶梯状脉冲通过电流调节器把相应的写电压Vw输出给编程开关，编程开关根据使能信号EN将写电压Vw通过列选通电路施加到存储阵列的位线，对阻变存储器进行复位；同时，电流检测电路对电流调节器的电流Iw进行检测；(3) The continuous ladder-shaped pulse outputs the corresponding write voltage Vw to the programming switch through the current regulator, and the programming switch applies the write voltage Vw to the bit line of the memory array through the column gate circuit according to the enable signal EN, and the resistive variable memory Reset; at the same time, the current detection circuit detects the current Iw of the current regulator;

（4）若复位成功，存储单元的存储电阻的阻值发生改变，电流调节器的电流Iw也相应的发生变化，电流检测电路将电流Iw发生变化的反馈信号FB发送给控制电路，控制电路根据该反馈信号FB使使能信号EN无效，转步骤（1）；(4) If the reset is successful, the resistance value of the storage resistor of the storage unit changes, and the current Iw of the current regulator changes accordingly. The current detection circuit sends the feedback signal FB of the change of the current Iw to the control circuit, and the control circuit according to The feedback signal FB makes the enable signal EN invalid, go to step (1);

若复位失败，存储单元的存储电阻阻值不发生改变，电流调节器的电流Iw未改变，电流检测电路将电流Iw未发生变化的反馈信号FB发送给控制电路，控制电路根据该反馈信号FB使使能信号EN有效，转步骤（1）。If the reset fails, the resistance value of the storage resistor of the storage unit does not change, the current Iw of the current regulator does not change, the current detection circuit sends the feedback signal FB that the current Iw does not change to the control circuit, and the control circuit uses the feedback signal FB according to the feedback signal FB. The enable signal EN is valid, go to step (1).

本发明的有益效果为：采用连续阶梯状的脉冲序列进行复位操作，并结合写通路的电路变化的反馈信号来判断是否停止施加该连续阶梯状脉冲，可以在复位成功马上停止施加连续阶梯状脉冲，去除了不需要在复位操作过程中的进行验证操作，一个连续阶梯状脉冲即可实现复位操作，既保证复位的良率不降低，又缩短了复位操作的时间，大大提高了复位操作的效率，同时不降低复位操作的良率。The beneficial effects of the present invention are as follows: the reset operation is performed by adopting a continuous stepped pulse sequence, and the feedback signal of the circuit change of the write path is used to judge whether to stop applying the continuous stepped pulse, and the application of the continuous stepped pulse can be stopped immediately after the reset is successful , eliminating the need to perform verification operations during the reset operation, a continuous stepped pulse can realize the reset operation, which not only ensures that the reset yield does not decrease, but also shortens the reset operation time, greatly improving the reset operation efficiency , while not degrading the yield of the reset operation.

附图说明Description of drawings

图1是按照本发明一实施例的复位操作过程中所使用的连续阶梯状脉冲的形状示意图。FIG. 1 is a schematic diagram of the shape of a continuous staircase pulse used during a reset operation according to an embodiment of the present invention.

图2是按照本发明一实施例的阻变存储器的模块结构示意图。FIG. 2 is a schematic diagram of a module structure of a resistive variable memory according to an embodiment of the present invention.

图3是按照本发明又一实施例的阻变存储器的模块结构示意图。FIG. 3 is a schematic diagram of a module structure of a resistive variable memory according to another embodiment of the present invention.

其中：控制电路110，写电压产生电路120，运算放大器130，NMOS管106，电流检测电路140，极性选择电路150，列选通电路160，阵列170，电流调节器180，运算放大器130，N管106，编程开关250，写入数据DATA101，写使能端WEN102，电流检测模块反馈到输入端的信号FB103，写电压产生电路输出给电流调节器180的写偏压Vw_Bias104，电流调节器180输出的写电压Vw105，电流调节器180输出给电流检测模块140的写通路电流Iw107，地108，阵列的一条位线BL109，阵列的源线SL111，阻变存储单元的存储电阻112，阻变存储单元的选通管113，控制电路输出使能信号EN114。Among them: control circuit 110, write voltage generation circuit 120, operational amplifier 130, NMOS tube 106, current detection circuit 140, polarity selection circuit 150, column gating circuit 160, array 170, current regulator 180, operational amplifier 130, N Tube 106, programming switch 250, write data DATA101, write enable terminal WEN102, signal FB103 fed back to the input terminal by the current detection module, write bias voltage Vw_Bias104 output by the write voltage generation circuit to the current regulator 180, output by the current regulator 180 The write voltage Vw105, the write path current Iw107 output by the current regulator 180 to the current detection module 140, the ground 108, a bit line BL109 of the array, the source line SL111 of the array, the storage resistor 112 of the resistive memory unit, and the Strobe tube 113, the control circuit outputs enable signal EN114.

具体实施方式detailed description

下面介绍的是本发明的多个可能实施例中的一些，旨在提供对本发明的基本了解。并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。Presented below are some of the many possible embodiments of the invention, intended to provide a basic understanding of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of protection.

图1所示为按照一实施例的复位操作过程中所使用的连续阶梯状脉冲的形状示意图。在该实施例的复位操作过程中，包括以下步骤：FIG. 1 is a schematic diagram illustrating the shape of successive staircase-like pulses used during a reset operation according to an embodiment. During the reset operation in this embodiment, the following steps are included:

S10，选中阻变存储器的存储阵列中需要进行复位的一个或多个存储单元；S10, selecting one or more memory cells that need to be reset in the memory array of the resistive variable memory;

S20，向需要复位的存储单元施加连续阶梯状脉冲90。如图1所示，在该实施例中，连续阶梯状脉冲90以电压脉冲为例进行说明，该连续阶梯状脉冲90可以随时间t的增加阶梯状地抬高脉冲的高度，例如，从V₀抬高至V₁、V₁抬高至V₂、连续地直至抬高至V_n，n为大于或等于2的整数，其中（V₁-V₀）、（V₂-V₁）等称之为阶梯高度，具体每个阶梯的高度大小可以相等，每个阶梯的宽度大小可以相等，当然也可以不相等，其可以根据具体情况设置。连续阶梯状脉冲90的最高脉冲高度V_n可以选择为使阻变存储器的存储阵列的存储单元复位成概率能达到某一预定值的电压值，例如，可以使99.99%的存储阵列的存储单元复位成功的电压值，由于存储阵列可能存在坏的存储单元，不可能复位操作成功，因此，设置一个最高值以防止连续阶梯状脉冲90的电压过高。以上所述一预定值可以根据存储阵列的一致性等情况来设置。S20 , applying continuous staircase pulses 90 to memory cells that need to be reset. As shown in FIG. 1, in this embodiment, the continuous stepped pulse 90 is illustrated by taking a voltage pulse as an example. The continuous stepped pulse 90 can increase the height of the pulse stepwise with the increase of time t, for example, from V ₀ is raised to V ₁ , V ₁ is raised to V ₂ , and continuously until it is raised to V _n , n is an integer greater than or equal to 2, where (V ₁ -V ₀ ), (V ₂ -V ₁ ), etc. It is called the height of the steps. Specifically, the height of each step can be equal, and the width of each step can be equal or unequal, which can be set according to specific conditions. The highest pulse height V _n of the continuous ladder-shaped pulse 90 can be selected to reset the storage cells of the storage array of the resistive variable memory to a voltage value that has a probability of reaching a certain predetermined value, for example, 99.99% of the storage cells of the storage array can be reset For the successful voltage value, since there may be bad memory cells in the memory array, it is impossible for the reset operation to be successful. Therefore, a highest value is set to prevent the voltage of the continuous staircase pulse 90 from being too high. The aforementioned predetermined value may be set according to conditions such as the consistency of the storage array.

S30，根据存储单元的阻态变化判断复位是否成功，若复位成功则根据电流变化产生的反馈信号及时停止施加连续阶梯状脉冲，否则继续施加所述连续阶梯状脉冲。在该步骤中，如图1所示，如果在t1时刻复位成功，则连续阶梯状脉冲90不需要再阶梯抬高脉冲高度，停止施加连续阶梯状脉冲90至存储单元，因此，可以在t1时刻连续阶梯状脉冲90的电压下降至0，此时，连续阶梯状脉冲90表现为脉冲90₁所示的单个脉冲；同样地，如果在t2时刻复位成功，则连续阶梯状脉冲90不需要再阶梯抬高脉冲高度，停止施加连续阶梯状脉冲90至存储单元，因此，可以在t2时刻连续阶梯状脉冲90的电压下降至0，此时，连续阶梯状脉冲90表现为脉冲90₂所示的脉冲形状；类推地，在t_n时刻复位成功，连续阶梯状脉冲90则表现为脉冲90_n所示的脉冲形状（前面为连续阶梯状脉冲）。S30, judging whether the reset is successful according to the change of the resistance state of the storage unit, if the reset is successful, stop applying the continuous step pulse in time according to the feedback signal generated by the current change, otherwise continue to apply the continuous step pulse. In this step, as shown in FIG. 1, if the reset is successful at time t1, the continuous step pulse 90 does not need to step up the pulse height again, and stops applying the continuous step pulse 90 to the memory cell. Therefore, at time t1 The voltage of the continuous stepped pulse 90 drops to 0, and at this moment, the continuous stepped pulse 90 appears as a single pulse shown in pulse 90 ₁ ; similarly, if the reset is successful at time t2, then the continuous stepped pulse 90 does not need to be stepped Raise the pulse height and stop applying the continuous stepped pulse 90 to the memory cell, so the voltage of the continuous stepped pulse 90 can drop to 0 at time t2, at this time, the continuous stepped pulse 90 is shown as the pulse shown in pulse 90 ₂ shape; analogously, at time t _n the reset is successful, and the continuous stepped pulse 90 is shown as the pulse shape shown by pulse 90 _n (the front is a continuous stepped pulse).

因此，在脉冲90每次作阶梯抬升之后，并不需要终止该脉冲来偏置另一验证脉冲作验证操作以判断是否复位成功，解决了RPS&SAWM方法中的复位时间长的问题。Therefore, after each step-up of the pulse 90, it is not necessary to terminate the pulse to bias another verification pulse for verification operation to determine whether the reset is successful, which solves the problem of long reset time in the RPS&SAWM method.

图2所示为按照本发明一实施例的阻变存储器的模块结构示意图。如图2所示，在该实施例中，阻变存储器适用于双极性写操作，阻变存储器包括控制电路110、写电压产生电路120、电流检测电路140、极性选择电路150、电流调节器180、列选通电路160和存储阵列170；其中，电流调节器180主要由运算放大器130和NMOS管106组成；存储阵列170由多个按行和列的形式排列的阻变存储单元组成，其中，示意性地给出了其中一个存储单元的结构，存储单元主要由存储电阻112和选通管113组成；控制电路110的输出端分别与写电压产生电路120的输入端和极性选择电路150的输入端相连接，写电压产生电路120的输出端与电流调节器180中的运算放大器130的正向输入端相连，电流调节器180中运算放大器130的负向输入端与极性选择电路150相连，极性选择电路150的输出端分别与列选通电路160的输入端和存储阵列170的源线相连，列选通电路160的输出端与阵列170的位线相连，电流检测电路140根据电流调节器180中电流的变化产生相应的反馈信号发送到控制电路110的输入端。FIG. 2 is a schematic diagram of a module structure of a resistive variable memory according to an embodiment of the present invention. As shown in Figure 2, in this embodiment, the resistive variable memory is suitable for bipolar write operation, and the resistive variable memory includes a control circuit 110, a write voltage generation circuit 120, a current detection circuit 140, a polarity selection circuit 150, a current regulation device 180, column gating circuit 160, and storage array 170; wherein, the current regulator 180 is mainly composed of an operational amplifier 130 and an NMOS transistor 106; the storage array 170 is composed of a plurality of resistive memory cells arranged in rows and columns, Among them, the structure of one of the memory cells is schematically shown, and the memory cell is mainly composed of a memory resistor 112 and a gating tube 113; the output end of the control circuit 110 is connected with the input end of the write voltage generation circuit 120 and the polarity selection circuit respectively. The input end of 150 is connected, the output end of write voltage generating circuit 120 is connected with the positive input end of operational amplifier 130 in the current regulator 180, the negative input end of operational amplifier 130 in the current regulator 180 is connected with the polarity selection circuit 150, the output terminal of the polarity selection circuit 150 is connected with the input terminal of the column gating circuit 160 and the source line of the memory array 170 respectively, the output terminal of the column gating circuit 160 is connected with the bit line of the array 170, and the current detection circuit 140 According to the change of the current in the current regulator 180 , a corresponding feedback signal is generated and sent to the input terminal of the control circuit 110 .

当阻变存储器进行复位操作时，写入数据DATA 101为0，控制电路110根据写入数据DATA 101、写使能信号WEN 102和反馈信号FB103产生使能信号EN 114。若使能信号EN114有效，写电压产生电路120将产生如图1所示形状的连续阶梯状脉冲V_{w_Bias}104，极性选择电路150也将正常工作，在该实施例中，其为双极性的阻变存储器，也即复位操作的信号与置位操作的信号方向相反；若使能信号EN 114无效，写电压产生电路120输出为零，而且极性选择电路150的输出SL 111和115也为零。Vw_Bias104通过电流调节器180把连续阶梯状脉冲对应的写电压Vw 105输出给极性选择电路150，同时电流检测电路140会检测写通路的电流Iw 107。电流检测电路140根据复位过程中阻变存储单元阻值改变后导致写通路的电流Iw 107变化产生相应的反馈信号FB 103给控制电路110。当极性选择电路150正常工作时，极性选择电路150根据写入数据DATA 101和使能信号EN 114施加分别写电压Vw和零电压到SL 111和115，115通过列选通电路160把其上电压施加到阵列170的BL 109上。When the RRAM is reset, the write data DATA 101 is 0, and the control circuit 110 generates the enable signal EN 114 according to the write data DATA 101 , the write enable signal WEN 102 and the feedback signal FB103 . If the enable signal EN114 is effective, the write voltage generation circuit 120 will generate the continuous ladder-like pulse V _{w_Bias} 104 of the shape shown in Figure 1, and the polarity selection circuit 150 will also work normally. In this embodiment, it is bipolar That is, the direction of the reset operation signal is opposite to that of the set operation signal; if the enable signal EN 114 is invalid, the output of the write voltage generation circuit 120 is zero, and the output SL 111 and 115 of the polarity selection circuit 150 are also to zero. The Vw_Bias 104 outputs the write voltage Vw 105 corresponding to the continuous stepped pulses to the polarity selection circuit 150 through the current regulator 180 , and the current detection circuit 140 detects the current Iw 107 of the write path. The current detection circuit 140 generates a corresponding feedback signal FB 103 to the control circuit 110 according to the change of the current Iw 107 of the write path caused by the change of the resistance value of the resistive memory cell during the reset process. When the polarity selection circuit 150 is working normally, the polarity selection circuit 150 applies write voltage Vw and zero voltage to SL 111 and 115 respectively according to the write data DATA 101 and the enable signal EN 114, and SL 115 passes through the column gating circuit 160. The upper voltage is applied to the BL 109 of the array 170 .

由上可知，写入数据DATA 101可以是写“0”、也可以是写“1”，也即该实施例的阻变存储器可以进行置位操作和复位操作；在进行复位操作时，写电压产生电路120对应地产生如图1所示的连续阶梯状脉冲；在进行置位操作时，可以产生诸如单脉冲等信号进行置位操作；复位操作的信号与置位操作的信号的极性相反，例如，置位操作的信号为正向，复位操作的信号为反向。It can be seen from the above that writing data DATA 101 can be writing "0" or writing "1", that is, the resistive memory of this embodiment can perform a set operation and a reset operation; when performing a reset operation, the write voltage The generating circuit 120 correspondingly generates the continuous step-like pulses as shown in FIG. 1; when performing the setting operation, a signal such as a single pulse can be generated to perform the setting operation; the signal of the reset operation is opposite in polarity to the signal of the setting operation , for example, the signal for the set operation is forward, and the signal for the reset operation is reverse.

图3所示为按照本发明又一实施例的阻变存储器的模块结构示意图。如图3所示，在该实施例中，阻变存储器包括控制电路110、写电压产生电路120、电流检测电路140、编程开关250、电流调节器180、列选通电路160和存储阵列170；其中，电流调节器180主要由运算放大器130和NMOS管组成；存储阵列170由多个按行和列的形式排列的阻变存储单元组成，其中，示意性地给出了其中一个存储单元的结构，存储单元主要由存储电阻112和选通管113组成；控制电路110的输出端分别与写电压产生电路120的输入端和编程开关250的输入端相连，写电压产生电路120的输出端与电流调节器180中的运算放大器130的正向输入端相连，电流调节器180中运算放大器130的负向输入端与编程开关250相连，编程开关250的输出端与列选通电路160的输入端连接，列选通电路160的输出端与阵列170的位线相连，存储阵列170的源线接地，电流检测电路140根据电流调节器180中电流的变化产生相应的反馈信号发送到控制电路110的输入端。相比于图2所示实施例的阻变存储器，采用编程开关250替换了极性选择电路150，因此，图3所示实施例的阻变存储器适用于单极性写操作。FIG. 3 is a schematic diagram of a module structure of a resistive variable memory according to another embodiment of the present invention. As shown in FIG. 3 , in this embodiment, the RRAM includes a control circuit 110, a write voltage generation circuit 120, a current detection circuit 140, a programming switch 250, a current regulator 180, a column gating circuit 160 and a memory array 170; Among them, the current regulator 180 is mainly composed of an operational amplifier 130 and an NMOS transistor; the storage array 170 is composed of a plurality of resistive memory cells arranged in rows and columns, wherein the structure of one of the memory cells is schematically shown , the storage unit is mainly composed of a storage resistor 112 and a gating tube 113; the output end of the control circuit 110 is connected to the input end of the write voltage generating circuit 120 and the input end of the programming switch 250 respectively, and the output end of the write voltage generating circuit 120 is connected to the current The positive input terminal of the operational amplifier 130 in the regulator 180 is connected, the negative input terminal of the operational amplifier 130 in the current regulator 180 is connected with the programming switch 250, and the output terminal of the programming switch 250 is connected with the input terminal of the column gating circuit 160 , the output terminal of the column gating circuit 160 is connected to the bit line of the array 170, the source line of the storage array 170 is grounded, and the current detection circuit 140 generates a corresponding feedback signal according to the change of the current in the current regulator 180 and sends it to the input of the control circuit 110 end. Compared with the RRAM in the embodiment shown in FIG. 2 , the programming switch 250 is used to replace the polarity selection circuit 150 . Therefore, the RRAM in the embodiment shown in FIG. 3 is suitable for unipolar write operation.

当阻变存储器进行复位操作时，写入数据DATA 101为0，控制电路110根据写入数据DATA 101、写使能信号WEN 102和反馈信号FB103产生使能信号EN 114。若使能信号EN114有效，写电压产生电路120将产生如图1所示形状的连续阶梯状的脉冲Vw_Bias104，编程开关250也将正常工作；若使能信号EN 114无效，写电压产生电路120输出为零，而且编程开关250的输出115也为零。Vw_Bias104通过电流调节器180把连续阶梯状脉冲对应的写电压Vw 105输出给编程开关250，同时电流检测电路140会检测写通路的电流Iw 107。电流检测电路140根据复位过程中阻变存储单元阻值改变后写通路的电流Iw 107变化产生相应的反馈信号FB 103给控制电路110。当编程开关250正常工作时，编程开关250施加写电压Vw到线115，线115通过列选通电路160把其上电压施加到阵列170的BL 109上，SL 111接地108。When the RRAM is reset, the write data DATA 101 is 0, and the control circuit 110 generates the enable signal EN 114 according to the write data DATA 101 , the write enable signal WEN 102 and the feedback signal FB103 . If the enable signal EN114 is effective, the write voltage generating circuit 120 will generate the continuous ladder-like pulse Vw_Bias104 of the shape shown in Figure 1, and the programming switch 250 will also work normally; if the enable signal EN114 is invalid, the write voltage generating circuit 120 will output is zero, and the output 115 of the programming switch 250 is also zero. The Vw_Bias 104 outputs the write voltage Vw 105 corresponding to the continuous step pulses to the programming switch 250 through the current regulator 180 , and the current detection circuit 140 detects the current Iw 107 of the write path. The current detection circuit 140 generates a corresponding feedback signal FB 103 to the control circuit 110 according to the change of the current Iw 107 of the write path after the resistance value of the resistive memory unit changes during the reset process. When the programming switch 250 works normally, the programming switch 250 applies the write voltage Vw to the line 115 , and the line 115 applies its voltage to the BL 109 of the array 170 through the column gating circuit 160 , and the SL 111 is grounded 108 .

同样地，图3所示实施例的阻变存储器可以类似地进行置位操作。Likewise, the RRAM in the embodiment shown in FIG. 3 can similarly perform a set operation.

在本文中，术语“连接”之前未加词语“直接”来限定时，表示两个部件之间的连接可以是直接连接，也可以是间接连接，也即连接的两个部件中间可以通过其他中间部件来实现连接。In this article, when the term "connection" is not defined by the word "direct" before it, it means that the connection between two parts can be a direct connection or an indirect connection, that is, the two connected parts can pass through other intermediate parts. components to connect.

以上所述仅是本发明的具体实施方式，任何基于本发明方法基础的等效变换，均属于本发明保护范围之内。The above descriptions are only specific implementation methods of the present invention, and any equivalent transformation based on the method of the present invention falls within the protection scope of the present invention.