CN103683179B - Switchgear in current distribution system - Google Patents

本发明涉及一种开关设备，特别具有低压功率开关，其分别当满足预先给定的电流条件时自动断开，具有与前面设置的开关(2)上的一个公共的接口(8)连接的数字式通信连接(6，7)和具有形式为串行的位序列(VBF，BF)的数字信号(S8，SI)，其由高状态和低状态构成，并且当满足电流条件时通过通信连接(6，7)向前面设置的开关(2)发送，其中前面设置的开关(2)分别在接收信号(S8)后至少在一个预先给定的延迟时间内不断开。为分别能够保证保护功能，建议：每一个被置位的位(B3‑B7)通过低状态构建，并且位序列(VBF)的各多个彼此直接相继的位(B3，B3以及B6，B7)或者位序列(BF)的末尾处的最后的时间区域(H)的预先给定的位(B5，B6)被置位。

The invention relates to a switching device, in particular with a low-voltage power switch, which is automatically disconnected when a predetermined current condition is met, respectively, and has a digital connection with a common interface (8) on the previously provided switch (2). type communication connection (6, 7) and a digital signal (S8, SI) having the form of a serial bit sequence (VBF, BF), which consists of a high state and a low state, and passes through the communication connection ( 6, 7) Send to the preceding switch (2), wherein the preceding switch (2) does not open at least for a predetermined delay time after receiving the signal (S8). In order to be able to guarantee the protective function, it is recommended that each set bit (B3‑B7) be formed with a low state and that each of several directly successive bits (B3, B3 and B6, B7) of the bit sequence (VBF) Alternatively, a predetermined bit (B5, B6) of the last time range (H) at the end of the bit sequence (BF) is set.

电流分配系统中的开关设备Switchgear in current distribution systems

技术领域technical field

本发明涉及根据本发明的电流分配系统中的开关设备。The invention relates to a switchgear in a current distribution system according to the invention.

背景技术Background technique

已知在电流分配系统中通过开关特别是低压功率开关向单个设备支路(或者耗电器)分配电流。这些开关分别为额定电流设计并且在故障情况下中断流过开关的电流，例如在短路时出现的电流。在此应该分别仅切断出现故障的或者最接近故障的设备支路。这种行为被称为选择地切断。至少在每一个从供电看在前面设置的开关内存在一个检测装置和一个脱扣单元。检测装置借助变换器分别采集流过开关的电流，其中脱扣单元验证是否满足预先给定的电流条件。如果是，则脱扣单元使开关脱扣。It is known to distribute current to individual plant branches (or consumers) in current distribution systems via switches, in particular low-voltage power switches. These switches are each designed for a rated current and interrupt the current flowing through the switch in the event of a fault, such as occurs in the event of a short circuit. In this case, only the faulty or the closest to the faulty system branch should be disconnected in each case. This behavior is known as selective cutting. At least one detection device and one tripping unit are located in each switch located at the front as viewed from the power supply. The detection devices each detect the current flowing through the switch by means of a converter, wherein the tripping unit checks whether a predetermined current condition is fulfilled. If yes, the trip unit trips the switch.

已知这样的开关设备，其中开关为选择地切断而彼此通信。于是一个例如特别因为存在短路而满足电流条件的(后面设置的)开关通过相应的信号将此通知前面设置的开关。作为结果前面设置的开关自身不立即断开，而是在规定的时间(预先规定的延迟时间)内等待后面设置的开关是否脱扣。如果后面设置的开关在经过上述延迟时间后未脱扣，则前面设置的开关中断电流流动。该通信途径分别由供电方向上后面设置的开关进行。人们称这种选择性为缩短时间的选择性控制ZSS，它也被称为ZSI(Zone SelectiveInterlocking，区域选择性联锁)。Switching devices are known in which the switches communicate with each other for selective switching off. A (subsequent) switch which fulfills the current condition, for example in particular because of the presence of a short circuit, then informs the preceding switch of this via a corresponding signal. As a result, the preceding switch does not open itself immediately, but waits for a predetermined time (predetermined delay time) whether the downstream switch has tripped. If the switch arranged later does not trip after the above-mentioned delay time has elapsed, the switch arranged earlier interrupts the current flow. This communication path is carried out in each case by a switch arranged downstream in the power supply direction. People call this selectivity shortened selective control ZSS, which is also called ZSI (Zone SelectiveInterlocking, regional selective interlocking).

信号可以作为数字信号构建，如从US 7058482所知。The signal can be constructed as a digital signal, as known from US7058482.

如果在一个开关后面直接设置多个开关，则它们通常通过一个公共的接口例如通过一条总线与前面设置的开关连接。If a plurality of switches are arranged directly behind a switch, they are usually connected to the preceding switch via a common interface, for example via a bus.

缺点是，在已知的借助数字信号的通信中，如果两个开关同时向前面设置的开关发送信号，则可能在公共的接口上出现不确定的状态，这可能会影响保护功能。A disadvantage is that, with the known communication by means of digital signals, if two switches simultaneously send signals to the preceding switch, undefined states can occur at the common interface, which can affect the protective function.

发明内容Contents of the invention

本发明的任务是避免不确定的状态，以便在任何时间都能够保证保护功能。The object of the invention is to avoid indeterminate states in order to be able to guarantee the protective function at all times.

该任务通过本发明的特征解决；本发明描述了有利的设计方案。This object is solved by the features of the invention; the invention describes an advantageous refinement.

第一方案规定，通过低状态构建信号的第一位序列(Bitfolge)的被置位的位和通过高状态构建不被置位的位，该信号为同步分别用一个被置位的位开始，并且第一位序列分别具有多个彼此直接相继的被置位的位。A first variant provides that the set bits of the first bit sequence (Bitfolge) of a signal are formed by a low state and the non-set bits are formed by a high state, the signals each starting with a set bit for synchronization, And each of the first bit sequences has a plurality of set bits directly following one another.

为缩短延迟时间，建议：提供一个数字信号，它包括第二位序列，它的位由高状态和低状态构成，并且它由在后面设置的开关分别通过通信连接向前面设置的开关发送，其中，前面设置的开关分别在接收该信号后断开，其中，第二位序列分别具有多个彼此直接相继的被置位的位，并且在至少一个位置通过被置位的位与第一位序列不同。In order to shorten the delay time, it is suggested that a digital signal is provided, which includes a second bit sequence, whose bits are composed of a high state and a low state, and which is sent by the switch arranged at the back to the switch arranged at the front respectively through a communication connection, wherein , the previously set switches are respectively disconnected after receiving this signal, wherein the second bit sequence respectively has a plurality of set bits directly following each other, and at least one position is connected to the first bit sequence by the set bit different.

如果第二位序列的彼此直接相继的被置位的位的数目大于第一位序列的彼此直接相继的被置位的位的数目，则能够改善保护功能。The protection function can be improved if the number of set bits which are set immediately after one another of the second bit sequence is greater than the number of set bits which are set directly one after another of the first bit sequence.

如果在存在其它位序列的情况下第一位序列的各彼此直接相继的被置位的位的数目大于其它位序列的彼此直接相继的被置位的位的数目，则能够得到保护功能的进一步改善。If, in the presence of other bit sequences, the number of set bits that are directly successive to one another of the first bit sequence is greater than the number of set bits that are directly consecutive to one another of the other bit sequences, a further increase in the protective function can be obtained. improve.

如果第一位序列多重具有彼此直接相继的被置位的位，则还能实现更好地保护。Even better protection is also achieved if the first bit sequence has multiple set bits that are set immediately after one another.

单个位的时间上的位长度分别相同是适宜的。It is expedient for the temporal bit lengths of the individual bits to be the same in each case.

第二解决方案规定，位序列的被置位的位通过低状态构建，该位序列由彼此相继的时间区域构建，第一时间区域在位序列的开始处具有一个被置位的位，当一个预先给定的位或者多个预先给定的位被置位时最后的时间区域包含延迟信息，最后的时间区域在时间上比其余的时间区域长，并且当在位序列的末尾处的最后的时间区域的预先给定的一个或者多个位被置位时，该信号触发延迟时间。A second solution provides that the set bit of a bit sequence is formed by a low state, the bit sequence is formed of successive time regions, the first time region has a set bit at the beginning of the bit sequence, when a The last time field contains delay information when the predetermined bit or multiple predetermined bits are set, the last time field is longer in time than the rest of the time fields, and when the last time field at the end of the bit sequence This signal triggers the delay time when one or more predefined bits of the time field are set.

附图说明Description of drawings

下面根据一个实施例详细描述本发明。附图中：The present invention is described in detail below based on an embodiment. In the attached picture:

图1示出了一个电流分配系统，具有一个前面设置的和两个后面设置的开关，Figure 1 shows a current distribution system with one front and two rear switches,

图2示出了根据图1的开关的通信连接，用于传输形式为数字信号的信息，Figure 2 shows the communication connection of the switch according to Figure 1 for the transmission of information in the form of digital signals,

图3示出了根据图2的信号的例子，Figure 3 shows an example of the signal according to Figure 2,

图4示出了根据图3的信号的例子，它包含延迟信息，Figure 4 shows an example of a signal according to Figure 3, which contains delay information,

图5示出了根据图3的信号的例子，它包含撤销信息，和Figure 5 shows an example of a signal according to Figure 3, which contains revocation information, and

图6示出了根据图2的信号的例子，它由三个时间区域构成。FIG. 6 shows an example of a signal according to FIG. 2, which consists of three time zones.

具体实施方式detailed description

图1示出了一种电流分配1，具有三个开关2、3、4，它们作为低压功率开关构造，并且在供电5上连接。从供电5看，开关2直接在两个开关3、4前面设置，而两个开关3、4直接在开关2后面设置。FIG. 1 shows a power distribution 1 with three switches 2 , 3 , 4 which are designed as low-voltage power switches and connected to a power supply 5 . Seen from the power supply 5 , the switch 2 is arranged directly in front of the two switches 3 , 4 , while the two switches 3 , 4 are arranged directly behind the switch 2 .

流过直接在后面设置的开关3、4的电流也流过前面设置的开关2。每一个开关2、3、4当一般说满足预先给定的电流条件时分别自动地断开，这里是当超过电流阈值时。电流阈值例如在短路时被超过。The current flowing through the immediately downstream switches 3 , 4 also flows through the preceding switch 2 . Each switch 2 , 3 , 4 is automatically opened in each case when, generally speaking, a predetermined current condition is met, here when a current threshold value is exceeded. The current threshold is exceeded, for example, in the event of a short circuit.

开关2、3、4按照层次级(分级地)设置，其中开关2建立一个层次级(等级)，直接在后面设置的开关3、4建立在其下设置的层次级(等级)。然后直接在开关3、4后面设置的开关(这里不存在)建立位于其下的层次级，等等。The switches 2 , 3 , 4 are arranged hierarchically (hierarchically), wherein switch 2 establishes a hierarchical level (level) and switches 3 , 4 arranged directly behind establish the hierarchical level (level) arranged below it. The switches (which do not exist here) which are arranged directly after the switches 3, 4 then establish the hierarchy levels which lie below them, and so on.

给一个级的每一开关2和3、4预先规定一个延迟时间，它在超过电流阈值后将开关2、3、4的脱扣以及由此的电流的中断延迟该延迟时间。该延迟时间对于同一级的所有开关2和3、4分别都相同，它在朝向供电5的方向上增加。A delay time is predetermined for each switch 2 and 3 , 4 of a stage, which delays the tripping of the switches 2 , 3 , 4 and thus the interruption of the current flow after a current threshold value has been exceeded. This delay time is the same for all switches 2 and 3 , 4 respectively of the same stage, it increases towards the supply 5 .

因为开关3、4构成最下面的级，所以它们(优选)不延迟地脱扣，也就是说它们的延迟时间是0ms。开关2的延迟时间在这里例如是50ms。(在按照图1的电流分配的情况下，如果在开关3、4下面存在另外一个唯一的级并且它的开关构成最下面的级并且因此相应地(优选)不延迟地脱扣，则开关2的延迟时间例如是100ms，而开关3、4的延迟时间是50ms。)Since the switches 3 , 4 form the lowest stage, they trip (preferably) without delay, that is to say their delay time is 0 ms. The delay time of switch 2 is here, for example, 50 ms. (In the case of the current distribution according to FIG. 1, if there is another single stage below switches 3, 4 and its switches form the lowest stage and therefore trip accordingly (preferably) without delay, then switch 2 The delay time of the switch is 100ms, for example, and the delay time of switches 3 and 4 is 50ms.)

如果开关3在超过电流阈值并且在经过开关2的50ms的延迟时间后还不脱扣，则(前面设置的)开关2脱扣。If switch 3 has not tripped after the current threshold value has been exceeded and after a delay time of 50 ms for switch 2 has elapsed, then switch 2 (previously provided) trips.

为减少前面设置的开关的延迟时间，这里仅是开关2的延迟时间，开关3、4通过通信连接6、7彼此连接。连接6、7作为总线连接6a、7a实现，并且在前面设置的开关2的一个公共的总线接口8处汇合。In order to reduce the delay time of the previously provided switches, here only the delay time of switch 2 , switches 3 , 4 are connected to each other via communication connections 6 , 7 . The connections 6 , 7 are realized as bus connections 6 a , 7 a and merge at a common bus interface 8 of the previously provided switch 2 .

在图2中示意性示出了ZSI系统(或者通过总线连接6a、7a的开关2、3、4的ZSI连接)的基本结构。可以看出，每一个开关2、3、4既具有通信输入ZSI_IN2、ZSI_IN3、ZSI_IN4，也具有通信输出ZSI_OUT2、ZSI_OUT3、ZSI_OUT4，它们分别属于一个ETU/ZSI模块：ETU/ZSI2、ETU/ZSI3、ETU/ZSI4，其中，ZSI是Zone Selective Interlocking(信号选择性)的缩写，ETU是Electronic Trip Unit(电子脱扣单元)的缩写。公共的总线接口8位于前面设置的开关2的输入ZSI_IN2处。通过总线连接6a、7a，前面设置的开关2和两个后面设置的开关3、4交换信息，也就是说，总线连接6a、7a在这里是双向连接，但是也可以构造为后面设置的3、4与前面设置的开关2之间的单向连接。通过总线连接6a、7a的信息交换例如借助发送的和接收的信号S1－S9进行。The basic structure of a ZSI system (or a ZSI connection via switches 2 , 3 , 4 of bus connections 6 a , 7 a ) is schematically shown in FIG. 2 . It can be seen that each switch 2, 3, and 4 not only has communication inputs ZSI_IN2, ZSI_IN3, ZSI_IN4, but also has communication outputs ZSI_OUT2, ZSI_OUT3, ZSI_OUT4, which belong to an ETU/ZSI module: ETU/ZSI2, ETU/ZSI3, ETU /ZSI4, where ZSI is Zone Selective Interlocking( Signal selectivity), ETU is the abbreviation of Electronic Trip Unit (electronic trip unit). The common bus interface 8 is located at the input ZSI_IN2 of the previously provided switch 2 . Via the bus connections 6a, 7a, the front switch 2 and the two rear switches 3, 4 exchange information, that is to say, the bus connections 6a, 7a are bidirectional connections here, but can also be configured as rear 3, 4 4 is a one-way connection with the switch 2 set earlier. The information exchange via the bus connections 6 a , 7 a takes place, for example, by means of sent and received signals S1 - S9 .

图3示出了例如九个不同的信号S1－S9，它们以数字的位编码的形式构建。信号S1－S9由时间上彼此相继的位B1－B20(binary digits，二进制数字)组成，它们的电压电平在这里要么位于0伏特(低状态)要么位于+5伏特(高状态)。一个位的时间长度在这里分别规定为10μs(微秒)。一个位当其具有低状态时被置位(亦即逻辑1)，当其具有高状态时不被置位(亦即逻辑0)，也就是说取决于在位序列的相应的位置存在的是低状态还是高状态。电压电平在所有信号S1－S9中必须在20个位B1－B20的开始前在高状态下存在预先规定的至少60μs。FIG. 3 shows, for example, nine different signals S1 - S9 which are constructed in digital bit-coded form. Signals S1 - S9 consist of chronologically consecutive bits B1 - B20 (binary digits), whose voltage level is here either 0 volts (low state) or +5 volts (high state). The duration of one bit is defined here as 10 μs (microseconds) in each case. A bit is set (i.e. logic 1) when it has a low state and not set (i.e. logic 0) when it has a high state, i.e. depends on the presence of low state or high state. The voltage level must be present in the high state for at least 60 μs predetermined in all signals S1 - S9 before the start of the 20 bits B1 - B20 .

每一个信号S1－S9以一个被置位的同步位B1开始，其后跟随位B2，它分别不被置位。这两个位B1、B2(逻辑二进制数“10”，亦即一个二进制数1和一个二进制数0)在信号S1－S9的开始分别用于同步，它们在图3中作为同步位序列SBF表示。Each signal S1-S9 begins with a set synchronization bit B1 followed by bit B2 which is respectively not set. These two bits B1, B2 (logic binary number "10", that is, a binary number 1 and a binary number 0) are used for synchronization at the beginning of the signal S1-S9 respectively, and they are represented as a synchronization bit sequence SBF in Figure 3 .

在两个位B1、B2后首先跟随五个位B3－B7，它们构成一个包含要传输的信息的位序列，下面称为信息位序列IBF。理论上说信息位序列IBF的所有五个位B3－B7都可以被置位；在在图3中信号S1－S9的情况下位序列IBF的最多四个位B3－B7被置位。After the two bits B1 and B2, five bits B3-B7 are first followed, which form a bit sequence containing the information to be transmitted, which is called the information bit sequence IBF below. Theoretically all five bits B3-B7 of the information bit sequence IBF can be set; in the case of signals S1-S9 in FIG. 3 at most four bits B3-B7 of the bit sequence IBF are set.

无同步的信息位序列IBF出于冗余的原因一个接一个重复，其中，在每三个信息位序列IBF之间设置一个不被置位的位B8、B14、B20作为分割位TB。The information bit sequences IBF without synchronization repeat one after the other for reasons of redundancy, wherein between every three information bit sequences IBF a non-set bit B8 , B14 , B20 is provided as a separator bit TB.

图4中示出了信号S8(延迟信号VS)连同它的二进制逻辑对应10 11011 0 11011 011011 0。延迟信号VS用于，由后面设置的开关3或4启动前面设置的开关2的延迟时间，这里是在超过开关3或4的电流阈值后。信号S8的三个信息位序列IBF的每一个(逻辑二进制数11011)，下面称延迟位序列VBF，分别由两个彼此直接相继的被置位的位(逻辑11)组成，它们通过一个不被置位的位(逻辑0)分开。两个彼此直接相继的被置位的位对于第一个延迟位序列VBF是位B3、B4以及B6、B7，也就是说两个位对B3、B4和B6、B7(分别为逻辑11)，它们在这里存在两次。Signal S8 (delayed signal VS) is shown in FIG. 4 together with its binary logic counterpart 10 11011 0 11011 011011 0 . The delay signal VS is used for the delay time for the activation of the preceding switch 2 by the subsequent switch 3 or 4 , here after the current threshold value of the switch 3 or 4 has been exceeded. Each of the three information bit sequences IBF of the signal S8 (logic binary number 11011), hereinafter referred to as the delayed bit sequence VBF, respectively consists of two set bits (logic 11) directly following each other, which are passed through an uninterrupted Set bits (logic 0) are separated. The two set bits immediately following each other are bits B3, B4 and B6, B7 for the first delayed bit sequence VBF, that is to say two bit pairs B3, B4 and B6, B7 (logic 11 in each case), They exist here twice.

也就是说，一般地信号S8具有一个(第一)位序列，即延迟位序列VBF，多次带有多个彼此直接相继的被置位的位(B3、B4和B6、B7；…)。彼此直接相继的位(B3、B4和B6、B7；…)在延迟位序列VBF(逻辑二进制数10 11011 0 11011 0 11011 0)内多次(这里是两次)存在。This means that signal S8 generally has a (first) bit sequence, ie delayed bit sequence VBF, multiple times with a plurality of set bits (B3, B4 and B6, B7; . . . ) directly following one another. The bits (B3, B4 and B6, B7; . . . ) directly following one another are present multiple times (here twice) within the delayed bit sequence VBF (logical binary number 10 11011 0 11011 0 11011 0).

如果开关3识别到短路，则它向前面设置的开关2发送信号S8，开关2同样识别到短路，但是不脱扣，而是等待给它预先规定的、由信号S8的接收触发的50ms的延迟时间，也就是说延迟(自己的)脱扣。如果开关3在经过50ms后还未脱扣，则前面设置的开关2脱扣。If switch 3 detects a short circuit, it sends a signal S8 to the previously arranged switch 2, which also detects a short circuit, but does not trip, but waits for the predetermined delay of 50 ms triggered by the reception of signal S8 time, that is to say delay (own) tripping. If switch 3 has not tripped after 50 ms, the previously set switch 2 trips.

如果通过开关3的电流的中断由于某种原因不可能，则开关3通过信号S9(撤销信号AS)重新撤销(结束)通过信号S8触发的前面设置的开关2的延迟。If interruption of the current flow through switch 3 is not possible for some reason, switch 3 again cancels (ends) the previously set delay of switch 2 triggered by signal S8 via signal S9 (deselect signal AS).

信号S9在图5中被示出，并且作为信息位序列IBF包括撤销位序列ABF(逻辑二进制数00111)。对于第一撤销位序列ABF是位B3、B4、B5、B6、B7，它具有两个彼此直接相继的不被置位的位B3、B4(逻辑二进制数00)和三个彼此直接相继的被置位的位B5、B6、B7(逻辑二进制数111)，其中延迟位序列VBF和撤销位序列ABF在一个位置即位B5彼此不同。这里撤销位序列ABF的彼此直接相继的位的数目大于进行触发的延迟位序列VBF的数目。Signal S9 is shown in FIG. 5 and comprises the abort bit sequence ABF (logic binary number 00111) as information bit sequence IBF. For the first deactivation bit sequence ABF are bits B3, B4, B5, B6, B7, which have two non-set bits B3, B4 (logic binary number 00) directly following each other and three set bits directly following each other. Set bits B5 , B6 , B7 (logical binary number 111 ), wherein the delay bit sequence VBF and the deactivation bit sequence ABF differ from each other in one position, bit B5 . Here, the number of directly successive bits of the deactivation bit sequence ABF is greater than the number of triggering delayed bit sequences VBF.

一般地信号S9包括一个(第二)位序列，即撤销位序列ABF，它像信号S8一样，具有多个彼此直接相继的位。两个位序列，即延迟位序列VBF和撤销位序列ABF，在至少一个位置(位B5、B11、B17)彼此不同。这里该(第二)位序列(撤销位序列ABF)的彼此直接相继的被置位的位的数目大于进行触发的(第一)位序列(延迟位序列VBF)的被置位的位。Signal S9 generally comprises a (second) bit sequence, the abort bit sequence ABF, which, like signal S8, has a plurality of bits directly following one another. The two bit sequences, the delay bit sequence VBF and the deactivation bit sequence ABF, differ from each other in at least one position (bits B5, B11, B17). The (second) bit sequence (abort bit sequence ABF) has a greater number of set bits immediately following one another than the set bits of the triggering (first) bit sequence (delayed bit sequence VBF).

如果开关3由于出现的技术问题不断开，则它向前面设置的开关2发送信号S9，该信号重新撤销由信号S8触发的开关2的延迟，而开关2立即脱扣。If the switch 3 does not open due to a technical problem, it sends a signal S9 to the previously arranged switch 2, which cancels the delay of the switch 2 triggered by the signal S8 again, and the switch 2 trips immediately.

在信号S8、S9之外存在的信号S1－S7不具有彼此直接相继的被置位的位。Signals S1 - S7 present outside of signals S8 , S9 have no set bits immediately following one another.

一般地说，信号S8、S9的两个位序列VBF、ABF的彼此直接相继的位的数目大于信号S1－S7的位序列IBF的彼此直接相继的位的数目，后者的数目这里例如是一。Generally speaking, the number of bits directly following each other of the two bit sequences VBF, ABF of the signals S8, S9 is greater than the number of bits directly following each other of the bit sequence IBF of the signals S1-S7, which here is, for example, one .

图6示出了，信号S1－S9的信息替换地也可以包含在一个信号SI内，该信号SI由带有三个时间区域SYN、IL、H的位序列BF构成，其中时间区域SYN、IL、H分别一个接一个设置，并且分别具有预先规定的固定的数目的被置位的位(这里是B1、B2、B3、B4、B5、B6)。每一个时间区域SYN、IL、H包含至少一个信息SYN、ESCD、S、G、V。第一时间区域SYN包含同步化信息SYN，这里是一个被置位的同步位B1。具有三个(可被置位的)位B2、B3、B4的第二时间区域IL，即联锁时间区域，在这里包含三个信息：早期短路检测(ESCD)、短时间延迟(S)、接地故障电流(接地故障电流G)，其中每一位B2、B3、B4相应于一个信息：ESCD、S、G。图6中为更加直观所有三个位B2、B3、B4都被置位，实际上分别仅三个位中的唯一的一个位B2或B3或B4被置位。延迟信息V包含在第三个即最后的时间区域H内，也就是说在位序列BF的末尾设置。其可以由一个或者多个位构成，这里由两个位B5、B6构成。FIG. 6 shows that the information of the signals S1-S9 can alternatively also be contained in a signal SI consisting of a bit sequence BF with three time domains SYN, IL, H, wherein the time domains SYN, IL, H are each set one after the other and each have a predetermined fixed number of set bits (here B1, B2, B3, B4, B5, B6). Each time zone SYN, IL, H contains at least one piece of information SYN, ESCD, S, G, V. The first time zone SYN contains the synchronization information SYN, here a set synchronization bit B1. The second time zone IL with three (can be set) bits B2, B3, B4, the interlocking time zone, contains here three pieces of information: early short circuit detection (ESCD), short time delay (S), Ground fault current (ground fault current G), where each bit B2, B3, B4 corresponds to a piece of information: ESCD, S, G. In FIG. 6 , all three bits B2 , B3 , B4 are set, in fact only one of the three bits, B2 or B3 or B4 , is set. The delay information V is contained in the third and last time range H, that is to say at the end of the bit sequence BF. It can consist of one or more bits, here two bits B5, B6.

也就是说，信息SYN、ESCD、S、G、V一个接一个以固定的顺序包含在信号SI中，其中，为了置位信息SYN、ESCD、S、G、V分别必须置位所属的位B2、B3、B4、B5、B6。That is to say, the information SYN, ESCD, S, G, V are contained one after the other in the signal SI in a fixed sequence, wherein in order to set the information SYN, ESCD, S, G, V each associated bit B2 must be set , B3, B4, B5, B6.

一般地延迟信息V被至少设置在位序列BF的一个远在后面的时间区域H内。Generally, the delay information V is provided at least in a distant time region H of the bit sequence BF.

位序列BF(一般地)由彼此相继的时间区域SYN、IL、H构成，并且位序列BF的第一时间区域(带有同步化信息SYN)具有一个分别被置位的位。如果位序列BF的最后的时间区域(这里是H)的预先给定的一个或者多个位(这里是B5、B6)被置位，则信号SI解除延迟时间。The bit sequence BF is (generally) formed from successive time regions SYN, IL, H, and the first time region of the bit sequence BF (with the synchronization information SYN) has a respectively set bit. Signal SI cancels the delay time if one or more bits (here B5 , B6 ) of the last time domain (here H) of the bit sequence BF are set.

这里在该实施例中位B1、B2、B3、B4、B5、B6的不同在于它们的长度。原因是，位B2、B3、B4实际上由两个具有位B1的长度的“基本位”构成，位B5、B6则由三个构成。可以说位B1仅由一个“基本位”构成。仅从该原因出发具有延迟信息V的时间区域H在时间上比其余的时间区域SYN、IL长，优选它如图6所示比另外两个时间区域SYN、IL长。The bits B1 , B2 , B3 , B4 , B5 , B6 differ here in the exemplary embodiment by their length. The reason is that bits B2, B3, B4 actually consist of two "basic bits" of the length of bit B1, and bits B5, B6 consist of three. It can be said that the bit B1 is composed of only one "basic bit". For this reason alone, the time range H with the delay information V is longer in time than the remaining time ranges SYN, IL, preferably longer than the other two time ranges SYN, IL as shown in FIG. 6 .

应该注意，每一个开关2、3、4分别具有一个由结构决定的本征延迟时间，其不可能被低于，并且在此例如是35ms。它必须分别与上面提到的对于所有开关2、3、4的延迟时间相加。It should be noted that each switch 2 , 3 , 4 has a construction-dependent intrinsic delay time, which cannot be lowered, and is here, for example, 35 ms. It must be added to the delay times mentioned above for all switches 2, 3, 4 respectively.