CN103684698B - The treating method and apparatus of data-signal - Google Patents

The invention discloses a kind for the treatment of method and apparatus of data-signal.Wherein, the method includes：The first data-signal, the first clock signal and second clock signal are obtained, wherein, the first data-signal is corresponding with the first clock signal, and the clock cycle of the first clock signal is identical with the clock cycle of second clock signal；If the first clock signal is located at the first pre-set interval relative to the phase difference of second clock signal, the first data-signal is gathered using the rising edge of second clock signal；If phase difference is located at the second pre-set interval, the first data-signal is gathered using the trailing edge of second clock signal；Second data-signal is obtained according to the data-signal obtained by the first data-signal of collection, wherein, the second data-signal is corresponding with second clock signal.The present invention solves the technical problem of timing margins of the uncontrollable data-signal in the transmission path that cross clock domain is transmitted in the prior art.

Data signal processing method and device

Technical Field

The present invention relates to the field of electronic circuits, and in particular, to a method and an apparatus for processing a data signal.

Background

In the conventional scheme of clock domain crossing transmission of data signals, transition edges of one clock signal are usually used to acquire a data signal corresponding to another clock signal, so as to obtain a data signal corresponding to a previous clock signal. However, in this scheme, the timing margin of the data signal on the transmission path of the cross-clock domain transmission is uncontrollable and uncertain, the timing margin may be larger in one case or smaller in another case, and when the timing margin is smaller, the data state is relatively unstable due to the shorter duration of the updated value of the data signal as the acquisition object, and therefore the acquired data is also inaccurate, thereby affecting the reliability of the cross-clock domain transmission of the data signal. In other words, the conventional scheme cannot guarantee that the requirement on the timing margin is met, and the reason for the requirement can be summarized as the problem that the timing margin of the data signal on the transmission path of the clock domain crossing transmission cannot be controlled in the prior art.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

The embodiment of the invention provides a method and a device for processing a data signal, which are used for at least solving the technical problem that the timing sequence margin of the data signal on a transmission path for cross-clock domain transmission cannot be controlled in the prior art.

According to an aspect of the embodiments of the present invention, there is provided a method for processing a data signal, including: acquiring a first data signal, a first clock signal and a second clock signal, wherein the first data signal corresponds to the first clock signal, and the clock period of the first clock signal is the same as the clock period of the second clock signal; acquiring the first data signal by using a rising edge of the second clock signal if the phase difference of the first clock signal relative to the second clock signal is within a first preset interval; if the phase difference is in a second preset interval, acquiring the first data signal by using the falling edge of the second clock signal; and acquiring a second data signal according to the data signal acquired by acquiring the first data signal, wherein the second data signal corresponds to the second clock signal.

According to another aspect of the embodiments of the present invention, there is also provided a data signal processing apparatus, including: an obtaining unit, configured to obtain a first data signal, a first clock signal, and a second clock signal, where the first data signal corresponds to the first clock signal, and a clock cycle of the first clock signal is the same as a clock cycle of the second clock signal; a selection unit configured to acquire the first data signal using a rising edge of the second clock signal when a phase difference between the first clock signal and the second clock signal is within a first preset interval, and acquire the first data signal using a falling edge of the second clock signal when the phase difference is within a second preset interval; and the processing unit is used for acquiring a second data signal according to the data signal acquired by acquiring the first data signal, wherein the second data signal corresponds to the second clock signal.

In the embodiment of the present invention, a manner of selecting between collecting a first data signal corresponding to a first clock signal between a rising edge and a falling edge of a second clock signal according to a phase difference between the first clock signal and the second clock signal is adopted to obtain the second clock signal corresponding to the second clock signal and meeting a requirement for a timing margin, wherein the control of the timing margin can be implemented by combining the selection mechanism with a first preset interval and a second preset interval, thereby solving a technical problem that the timing margin of the data signal on a transmission path of cross-clock domain transmission cannot be controlled in the prior art. Furthermore, the design requirement for clock domain crossing transmission of the data signal can be met through reasonable setting of the first preset interval and the second preset interval, and the clock domain crossing transmission reliability of the data signal is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of a method of processing a data signal according to an embodiment of the invention;

FIG. 2 is a schematic diagram of cross-clock domain transmission of a data signal according to the prior art;

FIG. 3 is a schematic diagram of another clock domain crossing transmission of a data signal according to the prior art;

FIG. 4 is a schematic diagram of cross-clock domain transmission of a data signal according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another cross-clock domain transmission of a data signal according to an embodiment of the invention;

fig. 6 is a schematic diagram of a data signal processing apparatus according to an embodiment of the present invention;

fig. 7 is a schematic diagram of another data signal processing apparatus according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

Example 1

According to an embodiment of the present invention, there is provided a processing method of a data signal, as shown in fig. 1, the processing method including:

s102: acquiring a first data signal, a first clock signal and a second clock signal, wherein the first data signal corresponds to the first clock signal, and the clock period of the first clock signal is the same as that of the second clock signal;

s104: if the phase difference of the first clock signal relative to the second clock signal is in a first preset interval, acquiring a first data signal by using the rising edge of the second clock signal; if the phase difference is in a second preset interval, acquiring a first data signal by using a falling edge of a second clock signal;

s106: and acquiring a second data signal according to the data signal acquired by acquiring the first data signal, wherein the second data signal corresponds to the second clock signal.

It should be clear that one of the technical problems to be solved by the present invention is to provide a method for processing a data signal to implement transmission of the data signal across clock domains, that is, to convert a data signal corresponding to one clock signal into a data signal corresponding to another clock signal, and the contents of the two data signals are the same, where, for convenience of description, the "one clock signal" is referred to as a first clock signal, the "another clock signal" is referred to as a second clock signal, the data signal corresponding to the first clock signal is referred to as a first data signal, and the data signal corresponding to the second clock signal is referred to as a second data signal.

In the embodiment of the present invention, the correspondence relationship between the first data signal and the first clock signal may be generally expressed as that the first data signal and the first clock signal are aligned with each other, that is, the update frequency of the first data signal is consistent with the clock frequency of the first clock signal, and the two phases are the same, for example, in fig. 2, the first data signal shown in row 2 corresponds to the first clock signal shown in row 1. However, the present invention is not limited to this, for example, in some embodiments of the present invention, the corresponding relationship between the first data signal and the first clock signal may also be represented by a certain determined phase relationship between the same frequency signals, which is orthogonal or inverse equal, in this scenario, although the first data signal and the first clock signal are not aligned, since the phase relationship between the two is determined and known, the timing of the first data signal may still be accurately inferred by the first clock signal, so that the first data signal may still be regarded as being in the clock domain of the first clock signal.

Similarly, in the embodiment of the present invention, the corresponding relationship between the second data signal and the second clock signal may also be represented as similar to the corresponding relationship between the first data signal and the first clock signal, however, it should be noted that the two corresponding relationships are not necessarily completely consistent, for example, in the embodiment of the present invention, the first data signal may be aligned with the first clock signal, and the second data signal may be inverted with respect to the second clock signal, which is not limited by the present invention. Furthermore, in the embodiment of the present invention, the clock cycles of the second clock signal and the first clock signal may be the same.

Based on the above description, the above problem of implementing clock domain crossing transmission of data signals proposed by the present invention can also be expressed as: the method comprises the steps of converting a first data signal corresponding to a first clock signal into a second data signal corresponding to a second clock signal, wherein the first data signal and the second data signal have the same content, but have different time sequences and respectively correspond to the first clock signal and the second clock signal.

To solve this problem, in the prior art, the transition edge of the second clock signal is usually used to acquire the first data signal to obtain the second data signal, for example, in fig. 2, the rising edge of the second clock signal as shown in row 3 may be used to acquire the first data signal as shown in row 2, and the acquired data signal as shown in row 4 may be used as the second data signal, where as can be seen from fig. 2, the first data signal corresponds to the first clock signal, and the second data signal corresponds to the second clock signal, so as to implement the transmission of the data signals across clock domains.

It can be easily seen that in fig. 2, the timing margin t on the transmission path of the first data signal as shown in row 2 to the second data signal as shown in row 4₁More than half a clock period T/2, where T represents the clock period of the first clock signal, i.e. when the rising edge of the second clock signal is used to collect the first data signal, the duration of the state in which the first data signal is updated to the value a exceeds T/2, so that the data state is relatively speaking the data stateThe data acquisition device can be more easily recovered from the disturbance such as the glitch generated by numerical value updating and transits to a more stable state, and the data acquired by using the rising edge of the second clock signal is more accurate, which is beneficial to the clock domain crossing transmission of the data signal.

However, in fact, with the above-described prior art scheme, the timing margin of the data signal on the transmission path of the transmission across the clock domain is uncertain, and in one scenario, such as the scenario shown in fig. 2, the timing margin thereof is large, and in another scenario, such as the scenario shown in fig. 3, the timing margin t thereof is large₂The value is relatively small, and is at least less than half a clock cycle, when the first data signal is acquired by using the rising edge of the second clock signal in the scene, because the duration of updating the first data signal to the value a is short, the data state of the first data signal may not be stable, and thus the acquired data is not accurate, thereby affecting the reliability of the data signal in transmission across clock domains. In other words, the manner of acquiring the first data signal to generate the second data signal by using the rising edge of the second clock signal cannot guarantee that the requirement for the timing margin is met, and correspondingly, the manner of acquiring the first data signal to generate the second data signal by using the falling edge of the second clock signal also has a similar problem, and the reason can be summarized as the problem that the timing margin of the data signal on the transmission path of the cross-clock domain transmission cannot be controlled in the prior art.

To solve this problem, in the embodiment of the present invention, a manner of acquiring a first data signal by using a second clock signal to generate a second data signal may be followed, and the first data signal and the second clock signal may be acquired in step S102, however, unlike the prior art, according to the processing method provided in the embodiment of the present invention, in step S104, a selection may be made between using a rising edge or a falling edge of the second clock signal according to a phase relationship between the first clock signal and the second clock signal, wherein if a phase difference between the first clock signal and the second clock signal is within a first preset interval, the first data signal may be acquired by using the rising edge of the second clock signal, and if the phase difference is within a second preset interval, the first data signal may be acquired by using the falling edge of the second clock signal. In other words, in the embodiment of the present invention, the first data signal is not statically acquired by using the rising edge or the falling edge of the second clock signal, but one of the rising edge and the falling edge may be selected for different situations to perform acquisition relatively dynamically, so as to control the timing margin of the data signal on the transmission path of the cross-clock transmission, and further meet the requirement of the timing margin.

It should be noted that the "dynamically" selection is not limited to a real-time selection, in the embodiment of the present invention, a period for selecting between the "rising edge acquisition" and the "falling edge acquisition" may be a shorter time period or a longer time period, and the selected mechanism may be further coupled to other mechanisms, for example, a judgment mechanism, wherein the selection may also be triggered according to a result generated by the judgment mechanism, and the like, which is not limited in the present invention. In addition, as an alternative embodiment, the selection mechanism may be implemented by hardware logic, such as a logic circuit, and may be further packaged in a physical interface to improve the integration level and the processing speed and reduce the processing pressure of the processor, or may be implemented by software logic, such as programming a programmable platform, such as an MCU, an FPGA, or a PLC, which is not limited in this disclosure.

The working principle of the solution of an embodiment of the invention will be explained in detail below with reference to fig. 4 and 5. In an embodiment of the present invention, the first preset interval may be set to (T/2, T), and the second preset interval may be set to (0, T/2). In the present application, the phase difference of the first clock signal with respect to the second clock signal indicates the amount of advance of the first clock signal with respect to the second clock signal, and for example, when the first clock signal is advanced 1/4 clock cycles with respect to the second clock signal, the phase difference of the first clock signal with respect to the second clock signal is 1/4 clock cycles.

As shown in fig. 4, in one scenario of the embodiment of the present invention, the first clock signal may be the clock signal shown in line 1, the first data signal may be the data signal shown in line 2, and the second clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference between the first clock signal and the second clock signal is greater than half a clock cycle, that is, the first clock signal is located in the first preset interval (T/2, T), so that according to step S104, the rising edge of the second clock signal can be selected to be used for collecting the first data signal, and the data signal shown in row 4 is obtained as the second data signal. It is easy to see that in the above scenario, the first data signal corresponds to the first clock signal, the second data signal corresponds to the second clock signal, and the data content of the second data signal is identical to the first data signal, i.e. a clock domain crossing transmission of the first data signal is achieved, on the other hand, the timing margin on the transmission path of the cross-clock domain transmission is equal to the phase difference, and the phase difference is located in the first predetermined interval and is greater than half a clock cycle, so the timing margin is greater than half a clock cycle, that is, in the embodiment of the present invention, the control of the timing margin can be partly realized by the first preset interval, so that the requirement of the timing margin can be met through reasonable setting of the first preset interval, therefore, the effects of accurately acquiring data and improving the reliability of clock domain crossing transmission of the data signals are achieved.

In contrast, in the above scenario, if the falling edge of the second clock signal is selected to acquire the first data signal, the acquired data signal may be the data signal as shown by the dashed line in fig. 4, line 5, and it is easy to see that the timing margin of the acquired data signal with respect to the first data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the first preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

As shown in fig. 5, in another scenario of the embodiment of the present invention, the first clock signal may be the clock signal shown in line 1, the first data signal may be the data signal shown in line 2, and the second clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference between the first clock signal and the second clock signal is less than half a clock cycle, that is, the first clock signal is located in the second preset interval (0, T/2), so that according to step S104, the falling edge of the second clock signal can be selected to be used for collecting the first data signal, and the data signal shown in row 5 is obtained as the second data signal. It is easy to see that, in the above scenario, on the basis of implementing the clock domain crossing transmission of the first data signal, the timing margin on the transmission path of the clock domain crossing transmission is equal to the phase difference plus a half clock cycle, and the phase difference is within the second preset interval and less than a half clock cycle, so that the timing margin is greater than a half clock cycle, that is, in the embodiment of the present invention, the control of the timing margin may be partially implemented by the second preset interval, so that the requirement for the timing margin may be met by reasonably setting the second preset interval, and the effects of accurately acquiring data and improving the reliability of the clock domain crossing transmission of the data signal are achieved.

In contrast, in the above scenario, if the rising edge of the second clock signal is selected to acquire the first data signal, the acquired data signal may be the data signal represented by the dashed line in fig. 5, row 4, and it is easy to see that the timing margin of the acquired data signal with respect to the first data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the second preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

Through the above embodiments, the working principle of the scheme of the embodiment of the present invention is explained. It should be noted that, in the embodiment of the present invention, for the first preset interval, the timing margin defined by the first preset interval is usually the first preset interval itself, and for the second preset interval, when the partial interval in the second preset interval is set to be located at (0, T/2), the timing margin defined by the partial interval is the partial interval plus a half clock cycle, and when the partial interval in the second preset interval is set to be located at (T/2, T), the timing margin defined by the partial interval will actually be represented as the partial interval minus a half clock cycle. That is, if the timing margin of the data signal transmitted across the clock domain on the transmission path is required to be large, the first preset interval may be set within (T/2, T), and the second preset interval may be set within (0, T/2), otherwise, the first preset interval may be set within (0, T/2), and the second preset interval may be set within (T/2, T). The specific settings and applications of the first preset interval and the second preset interval are not limited in any way.

Of course, the above conclusion is derived based on the corresponding relationship between the first data signal and the first clock signal, and the second data signal and the second clock signal are aligned, in some other embodiments of the present invention, for other expressions of the corresponding relationship, the determined phase relationship between the first data signal and the first clock signal and the determined phase relationship between the second data signal and the second clock signal may be combined to obtain the range of the timing margin defined by the first preset interval and the second preset interval after two offsets corresponding to the two phase relationships, which is not described herein in detail.

It should be further noted that the source and usage of the first data signal and the usage of the second data signal are not limited in any way, wherein the corresponding relationship between the first data signal and the first clock signal may generally be derived from the manner of acquiring the first data signal, for example, in some embodiments of the present invention, the first data signal may be a data signal obtained by acquiring corresponding data using a rising edge or a falling edge of the first clock signal, and the acquisition may be performed once or multiple times. However, this is not meant to limit the present invention, and in the embodiment of the present invention, the preprocessing of the data signal before the first data signal is acquired may also include other processing manners, such as delay processing or inversion processing with determined delay. In addition, the present invention does not limit the data content of the first data signal and the second data signal, for example, in some embodiments of the present invention, the first data signal may represent a memory address in the memory, and the second data signal may represent either the memory address or memory data read from the memory according to the memory address represented by the data signal obtained by collecting the first data signal, wherein the memory address represented by the first data signal may correspond to the first clock signal in terms of time sequence, and the memory address or memory data represented by the second data signal may correspond to the second clock signal in terms of time sequence, in this case, the first data signal may be input as a write address of the memory, another data signal may be input as write data of the memory, and the second data signal may be a read address input of the memory, Or the data signal obtained by collecting the first data signal is input as the read address of the memory to obtain the read data output of the memory, so that the clock domain crossing transmission of the 'another data signal' can be realized through the clock domain crossing transmission of the first data signal. This embodiment is particularly suitable for an application scenario in which the delay of the clock domain crossing transmission of the "another data signal" is not critical, but the accuracy and reliability thereof are high, but the present invention is not limited thereto.

It should be noted that, in the embodiment of the present invention, the first data signal may be a serial data signal or a parallel data signal, where the data width of the serial data signal may be 1 bit or multiple bits, and the specific processing manner may be as described in the foregoing embodiment, for the parallel data signal, if multiple data signals are transmitted synchronously, a processing manner similar to that of the multi-bit serial data signal may be adopted to process, and if multiple data signals are asynchronous, each signal may be separately processed as the first data signal.

On the basis of the above description, according to the processing method of the data signal provided by the embodiment of the invention, in step S106, a second data signal may be obtained from the data signal resulting from the acquisition of the first data signal, in other words, in the embodiment of the present invention, after the first data signal is collected in step S104, the collected data may be directly used as the second data signal as shown in the foregoing embodiment, or other feasible subsequent processing may be performed on the data signal obtained by collecting the first data signal according to specific design requirements, e.g., delayed, inverted, reacquired, registered one or more beats, etc., and the resulting processed data signal is taken as the second data signal, although it will be appreciated that, in the above-mentioned processing procedures, all should pertain to processing within the clock domain of the second clock signal, i.e., the obtained second data signal should still correspond to the second clock signal.

For example, optionally, in the embodiment of the present invention, step S106 may include:

s1: the following operations are performed N times: acquiring the data signal acquired last time again by using the rising edge or the falling edge of the second clock signal, wherein the initial value of the data signal acquired last time is the data signal acquired by acquiring the first data signal, and N is more than or equal to 1;

s2: and taking the data signal acquired after the N times of operations as a second data signal.

In the above scenario, after the first data signal is collected in step S104, the data signal obtained by collecting the first data signal may be collected again in step S1, and the "collecting again" operation may be repeatedly performed N times, where N is greater than or equal to 1, where, in an embodiment of the present invention, the N operations are not limited to "using a rising edge of the second clock signal" or "using a falling edge of the second clock signal", for example, in an embodiment, one operation of the N operations may use rising edge collection, and the next operation of the operation may use falling edge collection, which is not limited by the present invention.

It should be understood that, in the embodiment of the present invention, the data signal obtained by the N reacquisition operations performed by using the transition edge of the second clock signal, that is, the second data signal, still stays in the clock domain of the second clock signal, in general, for the case where the above-mentioned "previous acquisition" including the acquisition operation on the first data signal described in step S104 uses the rising edge of the second clock signal, for the reacquisition performed after the previous acquisition, if the rising edge of the second clock signal is still used, it is equivalent to delaying the data signal obtained by the previous acquisition by one clock cycle, or registering one beat, and if the falling edge of the second clock signal is used instead, it is equivalent to delaying the data signal obtained by the previous acquisition by half clock cycle, or registering one-half beat, correspondingly, for the previous acquisition, the falling edge of the second clock signal is used, similar effects can be obtained. In the method, no matter whether half-beat, one-beat or multi-beat is registered, the timing margin in the secondary acquisition is at least half clock period, so that the problem of accuracy and reliability reduction caused by insufficient timing margin of the data signal on a transmission path can be avoided.

Specifically, in the embodiment of the present invention, step S106 may include:

s3: if the phase difference is in a first preset interval, acquiring the data signal obtained by acquiring the first data signal again by using the falling edge of the second clock signal, and taking the acquired data signal as a second data signal; and/or the presence of a gas in the gas,

s4: and if the phase difference is in a second preset interval, acquiring the data signal obtained by acquiring the first data signal again by using the rising edge of the second clock signal, and taking the acquired data signal as a second data signal.

In the embodiment of the present invention, step S3 or step S4 may be combined with step S104 to obtain the second data signal that maintains alignment with the rising edge of the second clock signal or maintains alignment with the falling edge of the second clock signal. For example, in an embodiment, step S3 may be taken as step S106, in this scenario, if the phase difference is in a first preset interval, a first data signal may be acquired by step S104 using a rising edge of the second clock signal, and then the data signal obtained by acquiring the first data signal may be acquired again by step S3 using a falling edge of the second clock signal, so as to obtain a second data signal that meets the requirement for the timing margin and is aligned with the falling edge of the second clock signal, if the phase difference is in a second preset interval, the first data signal may be acquired by step S104 using the falling edge of the second clock signal, and obtain a second data signal that meets the requirement for the timing margin and is aligned with the falling edge of the second clock signal, and the second data signal obtained in the above manner may be guaranteed to be aligned with the falling edge of the second clock signal, and the phase difference is not related to the first preset interval or the second preset interval, so that the use and subsequent processing of the second data signal can be facilitated. Similarly, in the embodiment of the present invention, step S4 may be further taken as step S106, and a second data signal that meets the requirement for the timing margin and is aligned with the rising edge of the second clock signal is obtained, which will not be described herein in detail.

Further, in consideration of the requirement of double-rate Data transfer ddr (double Data rate) for both rising edge Data and falling edge Data, in an embodiment of the present invention, the first Data signal may include a third Data signal and a fourth Data signal, and the second Data signal may include a fifth Data signal and a sixth Data signal, where step S106 may include:

s5: if the phase difference is in a first preset interval, acquiring a data signal obtained by acquiring a third data signal again by using a falling edge of a second clock signal, acquiring a data signal obtained by acquiring a fourth data signal again by using a rising edge of the second clock signal, taking the data signal obtained by acquiring the third data signal again as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; if the phase difference is in a second preset interval, acquiring a data signal obtained by acquiring a fourth data signal again by using the rising edge of the second clock signal, taking the data signal obtained by acquiring a third data signal as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; or,

s6: if the phase difference is in a first preset interval, acquiring a data signal obtained by acquiring a fourth data signal again by using a falling edge of a second clock signal, taking the data signal obtained by acquiring a third data signal as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; and if the phase difference is in a second preset interval, acquiring the data signal obtained by acquiring the third data signal again by using the rising edge of the second clock signal, acquiring the data signal obtained by acquiring the fourth data signal again by using the falling edge of the second clock signal, taking the data signal obtained by acquiring the third data signal again as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal.

In the embodiment of the present invention, the third data signal and the fourth data signal as the first data signal both correspond to the first clock signal, and the selective acquisition of the first data signal in step S104 is also applicable to the acquisition of the third data signal and the fourth data signal, so that the fifth data signal and the sixth data signal as the second data signal can be obtained according to the acquired data signal.

As an alternative, step S5 may be taken as step S106, and when the phase difference is in the first preset interval, the acquiring process may be represented as:

the third data signal-rising edge (S104) -falling edge (S5) -the fifth data signal;

the fourth data signal-rising edge (S104) -rising edge (S5) -the sixth data signal;

when the phase difference is in a second preset interval, the acquiring process may be represented as:

the third data signal-falling edge (S104) -the fifth data signal;

the fourth data signal-falling edge (S104) -rising edge (S5) -the sixth data signal.

It is easy to see that as a feature of this embodiment, first, the fifth data signal obtained by processing the third data signal is aligned with the falling edge of the second clock signal, the sixth data signal obtained by processing the fourth data signal is aligned with the rising edge of the second clock signal, and second, the fifth data signal is advanced by half a clock cycle, or by half a beat, with respect to the sixth data signal. On this basis, in the embodiment of the present invention, the fifth data signal and the sixth data signal may be further processed by using the above feature to obtain a data signal that meets the timing requirement of the DDR, for example, optionally, after step S5, the processing method may further include:

s7: outputting a fifth data signal when the second clock signal is 1, and outputting a sixth data signal when the second clock signal is 0; or,

s8: the fifth data signal is output when the second clock signal is 0, and the sixth data signal is output when the second clock signal is 1.

Since the fifth data signal is aligned with the falling edge of the second clock signal, the sixth data signal is aligned with the rising edge of the second clock signal, and the fifth data signal is advanced by half a clock cycle relative to the sixth data signal, the double-frequency data signal can be obtained in step S7 or step S8, starting with the rising edge or the falling edge of the second clock signal, where the data represented by the fifth data signal is before the data represented by the sixth data signal in one clock cycle, so that the purpose of carrying the data carried by two data signals through one data signal is achieved, that is, the data transmission mechanism of the DDR is realized.

Preferably, in the embodiment of the present invention, the frequency multiplication manner described in step S7 may be adopted, wherein, since the fifth data signal is aligned with the falling edge of the second clock signal, when the second clock signal changes from 0 to 1, that is, the rising edge comes from, the fifth data signal lasts for half a clock cycle after the update, and therefore the fifth data signal output when the second clock signal is 1 will be relatively stable, and correspondingly, since the sixth data signal is aligned with the rising edge of the second clock signal, when the second clock signal changes from 1 to 0, that is, the falling edge comes from, the sixth data signal lasts for half a clock cycle after the update, and therefore the sixth data signal output when the second clock signal is 0 will also be relatively stable.

As another alternative, step S6 may be taken as step S106, and when the phase difference is in the first preset interval, the acquiring process may be represented as:

the third data signal-rising edge (S104) -the fifth data signal;

the fourth data signal-rising edge (S104) -falling edge (S6) -the sixth data signal;

when the phase difference is in a second preset interval, the acquiring process may be represented as:

the third data signal-falling edge (S104) -rising edge (S6) -the fifth data signal;

the fourth data signal-falling edge (S104) -falling edge (S6) -the sixth data signal.

It is easy to see that this embodiment is symmetrical to the acquisition strategy adopted in the above-mentioned alternative embodiment, and as a feature of this embodiment, firstly, the fifth data signal obtained by processing the third data signal is aligned with the rising edge of the second clock signal, the sixth data signal obtained by processing the fourth data signal is aligned with the falling edge of the second clock signal, and secondly, the fifth data signal is advanced by half a clock cycle, or by half a beat, with respect to the sixth data signal. Similarly, on the basis, if the operations in step S7 or step S8 are further performed, the double-frequency data signal starting with the rising edge or the falling edge of the second clock signal and preceding the data represented by the fifth data signal and succeeding the data represented by the sixth data signal in one clock cycle can also be obtained, and the data transmission mechanism corresponding to the DDR can be implemented.

Preferably, in the embodiment of the present invention, the frequency multiplication manner described in step S8 may be adopted, wherein, since the fifth data signal is aligned with the rising edge of the second clock signal, when the second clock signal changes from 1 to 0, that is, the falling edge comes from, the fifth data signal lasts for half a clock cycle after the update, and therefore the fifth data signal output when the second clock signal is 0 will be relatively stable, and correspondingly, since the sixth data signal is aligned with the falling edge of the second clock signal, when the second clock signal changes from 0 to 1, that is, the rising edge comes from, the sixth data signal lasts for half a clock cycle after the update, and therefore the sixth data signal output when the second clock signal is 1 will also be relatively stable.

The present invention is illustrated in two alternative embodiments by the above examples, however, it should be understood that the above examples are only for understanding the technical solutions of the present invention, and should not be construed as limiting the present invention. In the embodiments of the present invention, there may be other possible embodiments, which are not described herein, and it should be understood that these embodiments are all considered to be within the scope of the present invention.

Based on the above description, more specifically, in the embodiment of the present invention, the first clock signal may be a system clock of a memory controller, the second clock signal may be a write data clock of the memory controller, the first data signal may be data to be transmitted by the memory controller, and the second data signal may be write data transmitted to the memory chip by the memory controller, where clock cycles of the write data clock and the memory clock of the memory chip may be the same, and a preset timing requirement may be satisfied between the write data clock and the memory clock.

In this scenario, in combination with the method for processing a data signal provided in the embodiment of the present invention, effective transmission of data to be transmitted from a memory controller to a memory chip may be achieved, where the data to be transmitted may be a data signal corresponding to a system clock acquired or generated by the memory controller, and write data obtained through the above processing operation may be a data signal corresponding to a write data clock, so as to facilitate receiving and identifying the write data by the memory. Although the write data clock may also be obtained or generated by the memory controller, the write data clock and the memory clock should meet the predetermined timing requirement. The adjustment operation for the write data clock will be given in the subsequent embodiment.

Generally, in the embodiment of the present invention, the preset timing requirement may be expressed as: the write data generated according to the write data clock advances by K clock cycles relative to the memory clock when reaching the memory chip, where K is an arbitrary value between 0 and 1. Such a requirement is generally associated with the DDR protocol, for example, the current DDR protocol provides that when write data arrives at the memory chip, a transition edge of the memory clock should be located in the middle of the write data obtained by the memory chip, or the write data arrives at the memory chip about 1/4 or 3/4 clock cycles ahead of the memory clock, so that K may be set to 1/4 or 3/4, but the present invention is not limited to this, and in other embodiments of the present invention, the specific value of K may be set to other values between 0 and 1 for different memory data transmission protocols.

Further optionally, in this embodiment of the present invention, before step S102, the processing method may further include:

s10: repeatedly executing the following operations for M times before meeting the execution termination condition corresponding to the preset time sequence requirement:

s11, adjusting the write data clock or the third clock signal lagging K clock cycles relative to the write data clock forwards or backwards, and transmitting a seventh data signal corresponding to the adjusted write data clock or the adjusted third clock signal to the memory chip;

s12, receiving an eighth data signal returned by the memory chip according to the seventh data signal, and judging whether the execution termination condition is met according to the received eighth data signal; wherein M is greater than or equal to 1.

One loop formed by steps S11 and S12 can be summarized as: the process of adjusting, transmitting, and feeding back, wherein the eighth data signal fed back to the memory chip according to the seventh data signal transmitted thereto may generally carry information corresponding to "whether the execution termination condition is satisfied" or "whether the preset timing requirement is satisfied between the write data clock and the memory clock", so that whether the cycle is terminated may be determined by identifying and determining the eighth data signal, and the write data clock obtained after the above-mentioned M operations or the write data clock determined according to the third clock signal obtained after the M operations may be used as the second clock signal determined before the clock domain crossing transmission of the data signal is performed, so as to be the basis for selecting according to the phase difference in step S104. It is noted that the above-described loop may also have other equivalent variations, for example, an equivalent loop may also be summarized as: the process of delivering-feeding-adjusting according to the feedback, the present invention is not limited to the division of a single operation or a cycle of M operations, and each embodiment based on the above description should be considered as being within the protection scope of the present invention.

In general, in an embodiment of the present invention, the condition for terminating the execution of the M operations may correspond to achievement of a predetermined timing requirement, for example, in an embodiment, the seventh data signal may be set as a pulse signal aligned with a rising edge or a falling edge of the third clock signal, and the eighth data signal may represent a data signal obtained by the memory chip using the pulse signal to acquire the memory clock, where if the seventh data signal is aligned with the rising edge of the third clock signal, the condition for terminating the execution may be: the received eighth data signal is changed from 0 to 1; if the seventh data signal is aligned with the falling edge of the third clock signal, the termination condition may be: the received eighth data signal is changed from 1 to 0.

Since the third clock signal lags behind the write data clock by K clock cycles, if the write data generated according to the write data clock is required to be advanced by K clock cycles relative to the memory clock when reaching the memory chip, the seventh data signal generated according to the third clock signal should be required to be aligned with the memory clock when reaching the memory chip. On the other hand, when the eighth data signal obtained by the memory chip collecting the memory clock according to the seventh data signal received by the memory chip changes from 0 to 1, it can be considered that the pulse signal as the seventh data signal captures a rising edge of the eighth data signal, and when the eighth data signal changes from 1 to 0, it can be considered that the pulse signal captures a falling edge of the eighth data signal. Therefore, if the rising edges of the seventh data signal and the third clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the rising edge of the memory clock when the seventh data signal reaches the memory chip, that is, the eighth data signal is changed from 0 to 1, and if the falling edges of the seventh data signal and the third clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the falling edge of the memory clock when the seventh data signal reaches the memory chip, that is, the eighth data signal is changed from 1 to 0.

In particular, for DDR3, in some embodiments of the present invention, the write level function provided by the DDR3 memory may be utilized, and in this scenario, the DDR3 memory may be first placed in the write level mode, and the write data strobe signal (write DQS) is used as the third clock signal, so as to perform the above-mentioned M operations.

Further, in the embodiment of the present invention, since the adjustment of the write data clock and/or the third clock signal in step S11 may reflect the phase shift of the write data clock as the second clock signal, the phase difference between the first clock signal and the second clock signal, which is used as the basis for selection in step S104, may also be obtained according to the adjustment completed by the above-mentioned M operations. Wherein, optionally,

before executing the M operations, the processing method may further include: s13, taking a clock signal aligned with the system clock as an initial value of the write data clock or a third clock signal;

in performing the M operations, the adjusting the write data clock and/or the third clock signal forward or backward in step S11 may include: s14, delaying the write data clock or the third clock signal for 1/L clock cycles as the adjusted write data clock or the third clock signal, wherein L is a positive integer; and the number of the first and second groups,

after performing M operations, the processing method may further include: s15, if the clock signal aligned with the system clock is used as the write data clock, the phase difference is obtained according to the following formula: Δ ═ M/L × T; s16, if the clock signal aligned with the system clock is used as the third clock signal, obtaining the phase difference according to the following formula: Δ ═ (M/L-K) × T; where Δ represents the phase difference and T represents the clock period.

In the above scenario, the larger the value of L is, the smaller the adjustment amount of the write data clock or the third clock signal in a single operation is, the more accurate the calibration of the write data clock or the third clock signal is, the closer the timing between the write data clock and the memory clock is to the preset timing requirement, and on the other hand, the more accurate the phase difference Δ obtained according to the calibration is, so that the more accurate the control of the timing margin on the transmission path of the data signal across the clock domain by the processing method of the data signal is.

The present invention is further explained by providing a preferred embodiment, but it should be noted that the preferred embodiment is only for better describing the present invention and should not be construed as unduly limiting the present invention.

Example 2

According to an embodiment of the present invention, there is also provided a data signal processing apparatus for implementing the above data signal processing method, as shown in fig. 6, the processing apparatus including:

1) an obtaining unit 602, configured to obtain a first data signal, a first clock signal, and a second clock signal, where the first data signal corresponds to the first clock signal, and a clock period of the first clock signal is the same as a clock period of the second clock signal;

2) a selecting unit 604, configured to acquire a first data signal using a rising edge of a second clock signal when a phase difference of the first clock signal with respect to the second clock signal is in a first preset interval, and acquire the first data signal using a falling edge of the second clock signal when the phase difference is in a second preset interval;

3) the processing unit 606 is configured to obtain a second data signal according to a data signal obtained by acquiring the first data signal, where the second data signal corresponds to the second clock signal.

It should be clear that one of the technical problems to be solved by the present invention is to provide a device for processing a data signal, so as to implement transmission of the data signal across clock domains, that is, to convert a data signal corresponding to one clock signal into a data signal corresponding to another clock signal, and the contents of the two data signals are the same, where for convenience of description, the "one clock signal" is referred to as a first clock signal, the "another clock signal" is referred to as a second clock signal, the data signal corresponding to the first clock signal is referred to as a first data signal, and the data signal corresponding to the second clock signal is referred to as a second data signal.

In the embodiment of the present invention, the correspondence relationship between the first data signal and the first clock signal may be generally expressed as that the first data signal and the first clock signal are aligned with each other, that is, the update frequency of the first data signal is consistent with the clock frequency of the first clock signal, and the two phases are the same, for example, in fig. 2, the first data signal shown in row 2 corresponds to the first clock signal shown in row 1. However, the present invention is not limited to this, for example, in some embodiments of the present invention, the corresponding relationship between the first data signal and the first clock signal may also be represented by a certain determined phase relationship between the same frequency signals, which is orthogonal or inverse equal, in this scenario, although the first data signal and the first clock signal are not aligned, since the phase relationship between the two is determined and known, the timing of the first data signal may still be accurately inferred by the first clock signal, so that the first data signal may still be regarded as being in the clock domain of the first clock signal.

Similarly, in the embodiment of the present invention, the corresponding relationship between the second data signal and the second clock signal may also be represented as similar to the corresponding relationship between the first data signal and the first clock signal, however, it should be noted that the two corresponding relationships are not necessarily completely consistent, for example, in the embodiment of the present invention, the first data signal may be aligned with the first clock signal, and the second data signal may be inverted with respect to the second clock signal, which is not limited by the present invention. Furthermore, in the embodiment of the present invention, the clock cycles of the second clock signal and the first clock signal may be the same.

Based on the above description, the above problem of implementing clock domain crossing transmission of data signals proposed by the present invention can also be expressed as: the method comprises the steps of converting a first data signal corresponding to a first clock signal into a second data signal corresponding to a second clock signal, wherein the first data signal and the second data signal have the same content, but have different time sequences and respectively correspond to the first clock signal and the second clock signal.

To solve this problem, in the prior art, the transition edge of the second clock signal is usually used to acquire the first data signal to obtain the second data signal, for example, in fig. 2, the rising edge of the second clock signal as shown in row 3 may be used to acquire the first data signal as shown in row 2, and the acquired data signal as shown in row 4 may be used as the second data signal, where as can be seen from fig. 2, the first data signal corresponds to the first clock signal, and the second data signal corresponds to the second clock signal, so as to implement the transmission of the data signals across clock domains.

It can be easily seen that in fig. 2, the timing margin t on the transmission path of the first data signal as shown in row 2 to the second data signal as shown in row 4₁More than half a clock cycle T/2, where T represents the clock cycle of the first clock signal, that is, when the rising edge of the second clock signal is used to acquire the first data signal, the duration of the state in which the first data signal is updated to the value a exceeds T/2, so that the data state is relatively easier to recover from the disturbance such as the glitch generated by the value update and to transition to a more stable state, and the data acquired by using the rising edge of the second clock signal is more accurate, which is advantageous for the transmission of the data signal across the clock domain.

However, in fact, with the above-described prior art scheme, the timing margin of the data signal on the transmission path of the transmission across the clock domain is uncertain, and in one scenario, such as the scenario shown in fig. 2, the timing margin thereof is large, and in another scenario, such as the scenario shown in fig. 3, the timing margin t thereof is large₂The value is relatively small, and is at least less than half a clock cycle, when the first data signal is acquired by using the rising edge of the second clock signal in the scene, because the duration of updating the first data signal to the value a is short, the data state of the first data signal may not be stable, and thus the acquired data is not accurate, thereby affecting the reliability of the data signal in transmission across clock domains. In other words, the manner in which the rising edge of the second clock signal is used to acquire the first data signal to generate the second data signal does not guarantee that the requirements for the timing margin described above are met, and correspondingly, the falling edge of the second clock signal is used to acquire the first data signal to generate the second data signalSimilar problems exist in the manner of data signals, and the reason for this can be summarized as the problem that the timing margin of the data signals on the transmission path of the data signals transmitted across the clock domain cannot be controlled in the prior art.

To solve the problem, in the embodiment of the present invention, a manner of acquiring a first data signal by using a second clock signal to generate a second data signal may be followed, and the first data signal and the second clock signal may be acquired in the acquiring unit 602, however, unlike the prior art, according to the processing apparatus provided in the embodiment of the present invention, in the selecting unit 604, a selection may be performed between using a rising edge or a falling edge of the second clock signal according to a phase relationship between the first clock signal and the second clock signal, wherein if a phase difference of the first clock signal with respect to the second clock signal is in a first preset interval, the first data signal may be acquired by using the rising edge of the second clock signal, and if the phase difference is in a second preset interval, the first data signal may be acquired by using the falling edge of the second clock signal. In other words, in the embodiment of the present invention, the first data signal is not statically acquired by using the rising edge or the falling edge of the second clock signal, but one of the rising edge and the falling edge may be selected for different situations to perform acquisition relatively dynamically, so as to control the timing margin of the data signal on the transmission path of the cross-clock transmission, and further meet the requirement of the timing margin.

It should be noted that the "dynamically" selection is not limited to a real-time selection, in the embodiment of the present invention, a period for selecting between the "rising edge acquisition" and the "falling edge acquisition" may be a shorter time period or a longer time period, and the selected mechanism may be further coupled to other mechanisms, for example, a judgment mechanism, wherein the selection may also be triggered according to a result generated by the judgment mechanism, and the like, which is not limited in the present invention. In addition, as an alternative embodiment, the selection mechanism may be implemented by hardware logic, such as a logic circuit, and may be further packaged in a physical interface to improve the integration level and the processing speed and reduce the processing pressure of the processor, or may be implemented by software logic, such as programming a programmable platform, such as an MCU, an FPGA, or a PLC, which is not limited in this disclosure.

The working principle of the solution of an embodiment of the invention will be explained in detail below with reference to fig. 4 and 5. In an embodiment of the present invention, the first preset interval may be set to (T/2, T), and the second preset interval may be set to (0, T/2). In the present application, the phase difference of the first clock signal with respect to the second clock signal indicates the amount of advance of the first clock signal with respect to the second clock signal, and for example, when the first clock signal is advanced 1/4 clock cycles with respect to the second clock signal, the phase difference of the first clock signal with respect to the second clock signal is 1/4 clock cycles.

As shown in fig. 4, in one scenario of the embodiment of the present invention, the first clock signal may be the clock signal shown in line 1, the first data signal may be the data signal shown in line 2, and the second clock signal may be the clock signal shown in line 3. Under the above scenario, the phase difference between the first clock signal and the second clock signal is greater than half a clock cycle, that is, the first clock signal is located in the first preset interval (T/2, T), so that according to the selection unit 604, the rising edge of the second clock signal can be selected to be used for acquiring the first data signal, and the data signal shown in row 4 is obtained as the second data signal. It is easy to see that in the above scenario, the first data signal corresponds to the first clock signal, the second data signal corresponds to the second clock signal, and the data content of the second data signal is identical to the first data signal, i.e. a clock domain crossing transmission of the first data signal is achieved, on the other hand, the timing margin on the transmission path of the cross-clock domain transmission is equal to the phase difference, and the phase difference is located in the first predetermined interval and is greater than half a clock cycle, so the timing margin is greater than half a clock cycle, that is, in the embodiment of the present invention, the control of the timing margin can be partly realized by the first preset interval, so that the requirement of the timing margin can be met through reasonable setting of the first preset interval, therefore, the effects of accurately acquiring data and improving the reliability of clock domain crossing transmission of the data signals are achieved.

In contrast, in the above scenario, if the falling edge of the second clock signal is selected to acquire the first data signal, the acquired data signal may be the data signal as shown by the dashed line in fig. 4, line 5, and it is easy to see that the timing margin of the acquired data signal with respect to the first data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the first preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

As shown in fig. 5, in another scenario of the embodiment of the present invention, the first clock signal may be the clock signal shown in line 1, the first data signal may be the data signal shown in line 2, and the second clock signal may be the clock signal shown in line 3. Under the above scenario, the phase difference between the first clock signal and the second clock signal is less than half a clock cycle, that is, the first clock signal is located in the second preset interval (0, T/2), so that according to the selection unit 604, the falling edge of the second clock signal can be selected to be used for acquiring the first data signal, and the data signal shown in row 5 is obtained as the second data signal. It is easy to see that, in the above scenario, on the basis of implementing the clock domain crossing transmission of the first data signal, the timing margin on the transmission path of the clock domain crossing transmission is equal to the phase difference plus a half clock cycle, and the phase difference is within the second preset interval and less than a half clock cycle, so that the timing margin is greater than a half clock cycle, that is, in the embodiment of the present invention, the control of the timing margin may be partially implemented by the second preset interval, so that the requirement for the timing margin may be met by reasonably setting the second preset interval, and the effects of accurately acquiring data and improving the reliability of the clock domain crossing transmission of the data signal are achieved.

In contrast, in the above scenario, if the rising edge of the second clock signal is selected to acquire the first data signal, the acquired data signal may be the data signal represented by the dashed line in fig. 5, row 4, and it is easy to see that the timing margin of the acquired data signal with respect to the first data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the second preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

Through the above embodiments, the working principle of the scheme of the embodiment of the present invention is explained. It should be noted that, in the embodiment of the present invention, for the first preset interval, the timing margin defined by the first preset interval is usually the first preset interval itself, and for the second preset interval, when the partial interval in the second preset interval is set to be located at (0, T/2), the timing margin defined by the partial interval is the partial interval plus a half clock cycle, and when the partial interval in the second preset interval is set to be located at (T/2, T), the timing margin defined by the partial interval will actually be represented as the partial interval minus a half clock cycle. That is, if the timing margin of the data signal transmitted across the clock domain on the transmission path is required to be large, the first preset interval may be set within (T/2, T), and the second preset interval may be set within (0, T/2), otherwise, the first preset interval may be set within (0, T/2), and the second preset interval may be set within (T/2, T). The specific settings and applications of the first preset interval and the second preset interval are not limited in any way.

Of course, the above conclusion is derived based on the corresponding relationship between the first data signal and the first clock signal, and the second data signal and the second clock signal are aligned, in some other embodiments of the present invention, for other expressions of the corresponding relationship, the determined phase relationship between the first data signal and the first clock signal and the determined phase relationship between the second data signal and the second clock signal may be combined to obtain the range of the timing margin defined by the first preset interval and the second preset interval after two offsets corresponding to the two phase relationships, which is not described herein in detail.

It should be further noted that the source and usage of the first data signal and the usage of the second data signal are not limited in any way, wherein the corresponding relationship between the first data signal and the first clock signal may generally be derived from the manner of acquiring the first data signal, for example, in some embodiments of the present invention, the first data signal may be a data signal obtained by acquiring corresponding data using a rising edge or a falling edge of the first clock signal, and the acquisition may be performed once or multiple times. However, this is not meant to limit the present invention, and in the embodiment of the present invention, the preprocessing of the data signal before the first data signal is acquired may also include other processing manners, such as delay processing or inversion processing with determined delay. In addition, the present invention does not limit the data content of the first data signal and the second data signal, for example, in some embodiments of the present invention, the first data signal may represent a memory address in the memory, and the second data signal may represent either the memory address or memory data read from the memory according to the memory address represented by the data signal obtained by collecting the first data signal, wherein the memory address represented by the first data signal may correspond to the first clock signal in terms of time sequence, and the memory address or memory data represented by the second data signal may correspond to the second clock signal in terms of time sequence, in this case, the first data signal may be input as a write address of the memory, another data signal may be input as write data of the memory, and the second data signal may be a read address input of the memory, Or the data signal obtained by collecting the first data signal is input as the read address of the memory to obtain the read data output of the memory, so that the clock domain crossing transmission of the 'another data signal' can be realized through the clock domain crossing transmission of the first data signal. This embodiment is particularly suitable for an application scenario in which the delay of the clock domain crossing transmission of the "another data signal" is not critical, but the accuracy and reliability thereof are high, but the present invention is not limited thereto.

It should be noted that, in the embodiment of the present invention, the first data signal may be a serial data signal or a parallel data signal, where the data width of the serial data signal may be 1 bit or multiple bits, and the specific processing manner may be as described in the foregoing embodiment, for the parallel data signal, if multiple data signals are transmitted synchronously, a processing manner similar to that of the multi-bit serial data signal may be adopted to process, and if multiple data signals are asynchronous, each signal may be separately processed as the first data signal.

On the basis of the above description, according to the data signal processing apparatus provided in the embodiment of the present invention, in the processing unit 606, the second data signal may be obtained according to the data signal obtained by acquiring the first data signal, in other words, in the embodiment of the present invention, after the first data signal is acquired by the selecting unit 604, the acquired data may be directly used as the second data signal as shown in the foregoing embodiment, or other processes that are feasible subsequently, such as delaying, inverting, acquiring again, registering one or more beats and the like, may be performed on the data signal obtained by acquiring the first data signal according to specific design requirements, and the processed data signal may be used as the second data signal, however, it should be understood that, in the above processing process, all belong to the processing in the clock domain of the second clock signal, that is, the obtained second data signal should still correspond to the second clock signal.

For example, optionally, in the embodiment of the present invention, the processing unit 606 may include:

1) an execution module, configured to execute the following operations N times: acquiring the data signal acquired last time again by using the rising edge or the falling edge of the second clock signal, wherein the initial value of the data signal acquired last time is the data signal acquired by acquiring the first data signal, and N is more than or equal to 1;

2) and the output module is used for taking the data signal acquired after the N operations as a second data signal.

In the above scenario, after the first data signal is collected by the selection unit 604, the data signal obtained by collecting the first data signal may be collected again in the execution module, and the operation of "collecting again" may be repeatedly performed N times, where N is greater than or equal to 1, where, in an embodiment of the present invention, the N operations are not limited to "using a rising edge of the second clock signal" or "using a falling edge of the second clock signal", for example, in an embodiment, one operation of the N operations may use rising edge collection, and the next operation of the operation may use falling edge collection, which is not limited by the present invention.

It should be understood that, in the embodiment of the present invention, the data signal obtained by the N reacquisition operations performed by using the transition edge of the second clock signal, that is, the second data signal, still stays in the clock domain of the second clock signal, in general, for the case where the above-mentioned "previous acquisition" including the acquisition operation on the first data signal described in the selection unit 604 uses the rising edge of the second clock signal, for the reacquisition performed after the previous acquisition, if the rising edge of the second clock signal is still used, it is equivalent to delaying the data signal obtained by the previous acquisition by one clock cycle, or registering one beat, and if the falling edge of the second clock signal is used instead, it is equivalent to delaying the data signal obtained by the previous acquisition by half clock cycle, or registering one-half beat, correspondingly, for the case where the falling edge of the second clock signal is used for the previous acquisition, similar effects can be obtained. In the method, no matter whether half-beat, one-beat or multi-beat is registered, the timing margin in the secondary acquisition is at least half clock period, so that the problem of accuracy and reliability reduction caused by insufficient timing margin of the data signal on a transmission path can be avoided.

Specifically, in this embodiment of the present invention, the processing unit 606 may include:

1) the first processing module is used for performing secondary acquisition on the data signal obtained by acquiring the first data signal by using the falling edge of the second clock signal when the phase difference is in a first preset interval, and taking the data signal obtained by the secondary acquisition as a second data signal; and/or the presence of a gas in the gas,

2) and the second processing module is used for performing secondary acquisition on the data signal obtained by acquiring the first data signal by using the rising edge of the second clock signal when the phase difference is in a second preset interval, and taking the data signal obtained by secondary acquisition as a second data signal.

In an embodiment of the present invention, the first processing module or the second processing module may be combined with the selection unit 604 to obtain the second data signal that maintains alignment with the rising edge of the second clock signal or the second data signal that maintains alignment with the falling edge of the second clock signal. For example, in an embodiment, a first processing module may be used as the processing unit 606, in this scenario, if the phase difference is in a first preset interval, the selecting unit 604 may first acquire a first data signal by using a rising edge of a second clock signal, and then the first processing module may acquire a data signal obtained by acquiring the first data signal again by using a falling edge of the second clock signal, so as to obtain a second data signal that meets the requirement for the timing margin and is aligned with the falling edge of the second clock signal, and if the phase difference is in a second preset interval, the selecting unit 604 may acquire the first data signal by using the falling edge of the second clock signal, and obtain a second data signal that meets the requirement for the timing margin and is aligned with the falling edge of the second clock signal, and the second data signal obtained in the above manner may ensure to be aligned with the falling edge of the second clock signal, and the phase difference is not related to the first preset interval or the second preset interval, so that the use and subsequent processing of the second data signal can be facilitated. Similarly, in the embodiment of the present invention, a second processing module may also be used as the processing unit 606, and obtain a second data signal that meets the requirement for the timing margin and is aligned with the rising edge of the second clock signal, which is not described herein in detail.

Further, in consideration of the requirement of double-rate Data transfer ddr (double Data rate) for both rising edge Data and falling edge Data, in an embodiment of the present invention, the first Data signal may include a third Data signal and a fourth Data signal, and the second Data signal may include a fifth Data signal and a sixth Data signal, where the processing unit 606 may include:

1) the third processing module is used for performing secondary acquisition on a data signal obtained by acquiring a third data signal by using a falling edge of the second clock signal when the phase difference is in a first preset interval, performing secondary acquisition on a data signal obtained by acquiring a fourth data signal by using a rising edge of the second clock signal, taking the data signal obtained by acquiring the third data signal again as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; when the phase difference is in a second preset interval, acquiring a data signal obtained by acquiring a fourth data signal again by using the rising edge of a second clock signal, taking the data signal obtained by acquiring a third data signal as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; or,

2) the fourth processing module is used for performing secondary acquisition on the data signal obtained by acquiring the fourth data signal by using the falling edge of the second clock signal when the phase difference is in the first preset interval, taking the data signal obtained by acquiring the third data signal as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal; and when the phase difference is in a second preset interval, acquiring the data signal obtained by acquiring the third data signal again by using the rising edge of the second clock signal, acquiring the data signal obtained by acquiring the fourth data signal again by using the falling edge of the second clock signal, taking the data signal obtained by acquiring the third data signal again as a fifth data signal, and taking the data signal obtained by acquiring the fourth data signal again as a sixth data signal.

In the embodiment of the present invention, the third data signal and the fourth data signal as the first data signal both correspond to the first clock signal, and the selective acquisition of the first data signal in the selection unit 604 is also applicable to the acquisition of the third data signal and the fourth data signal, so that the fifth data signal and the sixth data signal as the second data signal can be obtained according to the acquired data signal.

As an alternative, a third processing module may be used as the processing unit 606, and when the phase difference is in a first preset interval, the acquiring process may be represented as:

third data signal-rising edge (selection unit) -falling edge (third processing module) -fifth data signal;

fourth data signal-rising edge (selection unit) -rising edge (third processing module) -sixth data signal;

when the phase difference is in a second preset interval, the acquiring process may be represented as:

third data signal-falling edge (selection unit) -fifth data signal;

fourth data signal-falling edge (selection unit) -rising edge (third processing module) -sixth data signal.

It is easy to see that as a feature of this embodiment, first, the fifth data signal obtained by processing the third data signal is aligned with the falling edge of the second clock signal, the sixth data signal obtained by processing the fourth data signal is aligned with the rising edge of the second clock signal, and second, the fifth data signal is advanced by half a clock cycle, or by half a beat, with respect to the sixth data signal. On this basis, in the embodiment of the present invention, the fifth data signal and the sixth data signal may be further processed by using the above features to obtain a data signal meeting the timing requirement of the DDR, for example, optionally, the processing apparatus may further include, coupled to the third processing module:

1) a first output unit, configured to output a fifth data signal when the second clock signal is 1, and output a sixth data signal when the second clock signal is 0; or,

2) and the second output unit is used for outputting a fifth data signal when the second clock signal is 0 and outputting a sixth data signal when the second clock signal is 1.

Because the fifth data signal is aligned with the falling edge of the second clock signal, the sixth data signal is aligned with the rising edge of the second clock signal, and the fifth data signal is advanced by half a clock cycle relative to the sixth data signal, the first output unit or the second output unit can respectively obtain the double-frequency data signal which starts from the rising edge or the falling edge of the second clock signal and is represented by the fifth data signal before the data represented by the sixth data signal in one clock cycle, so that the purpose of carrying the data carried by the two data signals through one data signal is achieved, and the data transmission mechanism of the DDR is also achieved.

Preferably, in the embodiment of the present invention, the frequency multiplication manner described in the first output unit may be adopted, wherein, since the fifth data signal is aligned with the falling edge of the second clock signal, when the second clock signal changes from 0 to 1, that is, the rising edge comes from, the fifth data signal lasts for half a clock cycle after being updated, and therefore, the fifth data signal output when the second clock signal is 1 will be relatively stable, and correspondingly, since the sixth data signal is aligned with the rising edge of the second clock signal, when the second clock signal changes from 1 to 0, that is, the falling edge comes from, the sixth data signal lasts for half a clock cycle after being updated, and therefore, the sixth data signal output when the second clock signal is 0 will also be relatively stable.

As another alternative, a fourth processing module may be used as the processing unit 606, and when the phase difference is in a first preset interval, the acquiring process may be represented as:

third data signal-rising edge (selection unit) -fifth data signal;

fourth data signal-rising edge (selection unit) -falling edge (fourth processing module) -sixth data signal;

when the phase difference is in a second preset interval, the acquiring process may be represented as:

third data signal-falling edge (selection unit) -rising edge (fourth processing module) -fifth data signal;

fourth data signal-falling edge (selection unit) -falling edge (fourth processing module) -sixth data signal.

It is easy to see that this embodiment is symmetrical to the acquisition strategy adopted in the above-mentioned alternative embodiment, and as a feature of this embodiment, firstly, the fifth data signal obtained by processing the third data signal is aligned with the rising edge of the second clock signal, the sixth data signal obtained by processing the fourth data signal is aligned with the falling edge of the second clock signal, and secondly, the fifth data signal is advanced by half a clock cycle, or by half a beat, with respect to the sixth data signal. Similarly, on the basis, if the operations of the first output unit or the second output unit are further performed, the double-frequency data signal starting from the rising edge or the falling edge of the second clock signal and having the data represented by the fifth data signal before and the data represented by the sixth data signal after in one clock cycle may also be obtained, and the data transmission mechanism corresponding to the DDR may be implemented.

Preferably, in the embodiment of the present invention, the frequency multiplication manner described in the second output unit may be adopted, wherein, since the fifth data signal is aligned with the rising edge of the second clock signal, when the second clock signal changes from 1 to 0, that is, the falling edge comes from, the fifth data signal lasts for half a clock cycle after the updating, so that the fifth data signal output when the second clock signal is 0 will be relatively stable, and correspondingly, since the sixth data signal is aligned with the falling edge of the second clock signal, when the second clock signal changes from 0 to 1, that is, the rising edge comes from, the sixth data signal lasts for half a clock cycle after the updating, and therefore, the sixth data signal output when the second clock signal is 1 will also be relatively stable.

The present invention is illustrated in two alternative embodiments by the above examples, however, it should be understood that the above examples are only for understanding the technical solutions of the present invention, and should not be construed as limiting the present invention. In the embodiments of the present invention, there may be other possible embodiments, which are not described herein, and it should be understood that these embodiments are all considered to be within the scope of the present invention.

Based on the above description, more specifically, in the embodiment of the present invention, the first clock signal may be a system clock of a memory controller, the second clock signal may be a write data clock of the memory controller, the first data signal may be data to be transmitted by the memory controller, and the second data signal may be write data transmitted to the memory chip by the memory controller, where clock cycles of the write data clock and the memory clock of the memory chip may be the same, and a preset timing requirement may be satisfied between the write data clock and the memory clock.

In this scenario, in combination with the data signal processing apparatus provided in the embodiment of the present invention, effective transmission of data to be transmitted from a memory controller to a memory chip may be achieved, where the data to be transmitted may be a data signal that is acquired or generated by the memory controller and corresponds to a system clock, and write data obtained through the processing operation may be a data signal that corresponds to a write data clock, so as to facilitate receiving and identifying the write data by the memory. Although the write data clock may also be obtained or generated by the memory controller, the write data clock and the memory clock should meet the predetermined timing requirement. The adjustment operation for the write data clock will be given in the subsequent embodiment.

Generally, in the embodiment of the present invention, the preset timing requirement may be expressed as: the write data generated according to the write data clock advances by K clock cycles relative to the memory clock when reaching the memory chip, where K is an arbitrary value between 0 and 1. Such a requirement is generally associated with the DDR protocol, for example, the current DDR protocol provides that when write data arrives at the memory chip, a transition edge of the memory clock should be located in the middle of the write data obtained by the memory chip, or the write data arrives at the memory chip about 1/4 or 3/4 clock cycles ahead of the memory clock, so that K may be set to 1/4 or 3/4, but the present invention is not limited to this, and in other embodiments of the present invention, the specific value of K may be set to other values between 0 and 1 for different memory data transmission protocols.

Further optionally, in this embodiment of the present invention, before the obtaining unit 602, the processing apparatus may further include:

1) the adjusting unit is used for repeatedly executing the following operations for M times before meeting the execution termination condition corresponding to the preset time sequence requirement: adjusting a write data clock or a third clock signal lagging K clock cycles relative to the write data clock forward or backward, and transmitting a seventh data signal corresponding to the adjusted write data clock or the adjusted third clock signal to the memory chip; receiving an eighth data signal returned by the memory chip according to the seventh data signal, and judging whether the execution termination condition is met according to the received eighth data signal; wherein M is greater than or equal to 1.

One cycle formed in the adjustment unit can be summarized as: the process of adjusting, transmitting, and feeding back, wherein the eighth data signal fed back to the memory chip according to the seventh data signal transmitted thereto may generally carry information corresponding to "whether the execution termination condition is satisfied" or "whether the preset timing requirement is satisfied between the write data clock and the memory clock", so that whether the cycle is terminated may be determined by identifying and determining the eighth data signal, and the write data clock obtained after the above M operations or the write data clock determined according to the third clock signal obtained after the M operations may be used as the second clock signal determined before the clock domain crossing transmission of the data signal is performed, so as to be used as a basis for selecting according to the phase difference in the selecting unit 604. It is noted that the above-described loop may also have other equivalent variations, for example, an equivalent loop may also be summarized as: the process of delivering-feeding-adjusting according to the feedback, the present invention is not limited to the division of a single operation or a cycle of M operations, and each embodiment based on the above description should be considered as being within the protection scope of the present invention.

In general, in an embodiment of the present invention, the condition for terminating the execution of the M operations may correspond to achievement of a predetermined timing requirement, for example, in an embodiment, the seventh data signal may be set as a pulse signal aligned with a rising edge or a falling edge of the third clock signal, and the eighth data signal may represent a data signal obtained by the memory chip using the pulse signal to acquire the memory clock, where if the seventh data signal is aligned with the rising edge of the third clock signal, the condition for terminating the execution may be: the received eighth data signal is changed from 0 to 1; if the seventh data signal is aligned with the falling edge of the third clock signal, the termination condition may be: the received eighth data signal is changed from 1 to 0.

Since the third clock signal lags behind the write data clock by K clock cycles, if the write data generated according to the write data clock is required to be advanced by K clock cycles relative to the memory clock when reaching the memory chip, the seventh data signal generated according to the third clock signal should be required to be aligned with the memory clock when reaching the memory chip. On the other hand, when the eighth data signal obtained by the memory chip collecting the memory clock according to the seventh data signal received by the memory chip changes from 0 to 1, it can be considered that the pulse signal as the seventh data signal captures a rising edge of the eighth data signal, and when the eighth data signal changes from 1 to 0, it can be considered that the pulse signal captures a falling edge of the eighth data signal. Therefore, if the rising edges of the seventh data signal and the third clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the rising edge of the memory clock when the seventh data signal reaches the memory chip, that is, the eighth data signal is changed from 0 to 1, and if the falling edges of the seventh data signal and the third clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the falling edge of the memory clock when the seventh data signal reaches the memory chip, that is, the eighth data signal is changed from 1 to 0.

In particular, for DDR3, in some embodiments of the present invention, the write level function provided by the DDR3 memory may be utilized, and in this scenario, the DDR3 memory may be first placed in the write level mode, and the write data strobe signal (write DQS) is used as the third clock signal, so as to perform the above-mentioned M operations.

Further, in the embodiment of the present invention, since the adjustment of the write data clock and/or the third clock signal in the adjustment unit may reflect the phase shift of the write data clock as the second clock signal, the phase difference between the first clock signal and the second clock signal according to the selection in the selection unit 604 may also be obtained according to the adjustment completed by the above-mentioned M operations. Wherein, optionally,

the processing device may further include: an initialization unit configured to use a clock signal aligned with a system clock as an initial value of a write data clock or a third clock signal;

the adjusting unit may include: the delay module is used for delaying the write data clock or the third clock signal for 1/L clock cycles as the adjusted write data clock or the third clock signal, and L is a positive integer;

the processing device may further include: a calculating module, configured to obtain the phase difference according to the following formula when a clock signal aligned with a system clock is used as a write data clock: Δ ═ M/L × T; when a clock signal aligned with the system clock is taken as the third clock signal, the phase difference is obtained according to the following equation: Δ ═ (M/L-K) × T; where Δ represents the phase difference and T represents the clock period.

In the above scenario, the larger the value of L is, the smaller the adjustment amount of the write data clock or the third clock signal in a single operation is, the more accurate the calibration of the write data clock or the third clock signal is, the closer the timing between the write data clock and the memory clock is to the preset timing requirement, and on the other hand, the more accurate the phase difference Δ obtained according to the calibration is, so that the more accurate the processing apparatus of the data signal controls the timing margin on the transmission path of the data signal across the clock domain.

The present invention is further explained by providing a preferred embodiment, but it should be noted that the preferred embodiment is only for better describing the present invention and should not be construed as unduly limiting the present invention.

Example 3

According to an embodiment of the present invention, there is also provided an apparatus for processing a data signal implemented by hardware logic, as shown in fig. 7, the apparatus may include:

1) registers REG1, REG2, REG3, REG4, REG5, REG6, and REG 7;

2) selectors MUX1, MUX2, and MUX 3;

fig. 7 may be referred to for connection relationships between the devices, which is not described in detail herein.

As shown in fig. 7, in an embodiment of the present invention, the clock inputs of REG1 and REG2 may both be clock signal clk1, where clk1 may be the first clock signal as described in embodiment 2. The data input of REG1 may be data signal dq1, the data output may be data signal dq3, and dq3 may be regarded as the data signal obtained by dq1 acquiring via clk1, so that dq3 is synchronized with clk1, where dq3 may be used as the third data signal as described in embodiment 2. Similarly, the data input of REG2 may be data signal dq2, the data output may be data signal dq4, and dq4 may be regarded as the data signal obtained by dq2 acquiring via clk1, so that dq4 is synchronized with clk2, where dq4 may be used as the fourth data signal as described in embodiment 2.

The acquisition of the data signal synchronized with the first clock signal may be achieved by REG1 and/or REG2, whereas the acquisition of the second clock signal, which the acquisition unit needs to perform as described in embodiment 2, may be simply achieved through one terminal, for example, the terminal identified with clk2 on the left side in fig. 7, for the input of the clock signal clk2, where clk2 may serve as the second clock signal as described in embodiment 2.

Further, in the embodiment of the present invention, the selective capture operation required to be performed by the selection unit as described in embodiment 2 may be implemented by REG3, REG4, REG5, and REG6, and selectors MUX1 and MUX 2.

As shown in fig. 7, the clock inputs of REG3, REG4, REG5, and REG6 may all be clock signal clk2, where clk2 may serve as the second clock signal as described in embodiment 2. The data inputs of REG3 and REG6 may be dq3, and the data inputs of REG4 and REG5 may be dq4, so that REG3, REG4, REG5, and REG6 may all function to acquire data signal dq3 or dq4 located in the clock domain of clk1 to obtain a data signal located in the clock domain of clk2, that is, to realize clock domain crossing transmission of the data signal.

Specifically, as shown in fig. 7, the clock inputs of REG3 and REG4 are clk2 directly, that is, using the rising edge of clk2 for acquisition, and the clock inputs of REG5 and REG6 are each input to clk2 through an inverter, that is, using the falling edge of clk2 for acquisition, as to which of the rising edge and the falling edge of clk2 is specifically used for acquisition, may be accomplished through a selector MUX1 and MUX2, wherein the low level inputs of MUX1 and MUX2 may correspond to the acquisition mode using the rising edge of clk2, the high level input may correspond to the acquisition mode using the falling edge of clk2, the control input may be used to input an electrical signal pm corresponding to the phase difference between clk1 and clk2, where the phase difference is located at (T/2, T) which is the first preset interval as described in embodiment 2, pm may be low level, and further the rising edge of 2 may be used to acquire the data signal corresponding to clk1, when the phase difference is at (0, T/2) which is the second preset interval as described in embodiment 2, pm may be high, and the falling edge of clk2 may be used to acquire the data signal corresponding to clk 1.

Through the above selective acquisition manner, the timing margins of the data signals dq1 and dq2 on the clock domain crossing transmission path can be ensured, so as to improve the accuracy of data transmission.

Further, as shown in fig. 7, after the data signal in the clock domain of clk1 is collected by REG3, REG4, or REG5, the collected data signal may be collected again, where pm is low when the phase difference is in the first preset interval, the data signal obtained by collecting dq3 by REG3 may be collected again by REG6 using the falling edge of clk2 to obtain dq5 of the fifth data signal as described in embodiment 2, and the data signal obtained by collecting dq4 by REG4 using the rising edge of clk2 may be collected again by REG7 to obtain the sixth data signal dq6 as described in embodiment 2. Of course, the processing unit as described in embodiment 2 may also directly output the data signal obtained by first collecting clk2, for example, as shown in fig. 7, when the phase difference is in the second preset interval, pm is high level, and dq3 directly passes through REG6, and obtains the fifth data signal dq5 in the second data signal as described in embodiment 2 after one collection of the falling edge of clk2, which is not limited by the invention.

The invention in fact gives a hardware implementation of the third processing module as described in example 2, by means of a circuit as shown in fig. 7, while the fourth processing module corresponds to a symmetrical implementation of the third processing module, without the invention being described in more detail here. Among them, as an optimized design, in the embodiment of the present invention, REG6 is used as a part of the selection unit and the processing unit as described in embodiment 2 respectively under different situations, thereby saving at least one register, and increasing the processing speed of the processing device while reducing the loss, and it is noted that such equivalents or modifications to the embodiment of the present invention should be considered to be within the protection scope of the present invention.

It should be noted that, in the embodiment of the present invention, whether the hardware logic circuit is formed by REG1, REG3, MUX1, and REG6, or the hardware logic circuit is formed by REG2, REG4, REG5, MUX2, and REG7, each of which may be regarded as a specific implementation of the processing apparatus described in embodiment 2, wherein timing margins on clock domain crossing transmission paths of dq3 to dq5, and dq2 to dq4 may be respectively guaranteed. However, considering the double speed transmission requirement of DDR, dq3 or dq1 and dq4 or dq2 can be further combined together to be output as one-way data, specifically, as shown in fig. 7, the combination of dq4 and dq5 can be realized by a selector MUX3, where a high level input of MUX3 can be the data output of REG6, a low level input of MUX3 can be the data output of REG7, and a control input can be clk2, so that when clk2 is high level, MUX3 or processing device can output dq5, and when clk2 is low level, MUX3 or processing device can output dq6, which satisfies the requirement of DDR for data transmission and gives a feasible hardware implementation of the first output unit as described in embodiment 2, while the second output unit is symmetrical to the first output unit, this invention is not described.

Further, in the embodiment of the present invention, the processing apparatus shown in fig. 7 may be used as a part of a physical PHY module of a memory controller, and since the processing apparatus has a simple structure and a small delay, the processing speed of the memory controller using the PHY module of the processing apparatus is significantly increased compared to the existing memory controller or a memory controller implemented by software logic and having the same function. Specifically, clk1 may be a system clock, clk2 may be a memory clock, dq1 may be one path of data for DDR data transfer, dq2 may be the other path of data, and an output of MUX3 may be memory write data for memory transfer, where the write data is formed by combining data contents of dq1 and dq2, a data transfer rate of the write data is twice a frequency of the system clock, and the processing apparatus provided by the embodiment of the present invention may ensure that a timing margin on a transmission path across clock domains is greater than or equal to half a clock cycle, thereby improving accuracy of data transfer.

It should be noted that the foregoing embodiments are only used for understanding the technical solution of the present invention, and should not be construed as constituting any unnecessary limitation to the present invention, for example, in the processing apparatus shown in fig. 7, more registers may be added on the transmission path to achieve the purpose of performing one-beat or multi-beat registration on the data signal, and similar embodiments do not affect the implementation of the technical solution of the present invention and the implementation of the technical effect thereof, and the present invention is not limited thereto. It should be understood that similar extensions and extensions of the present invention are contemplated as falling within the scope of the present invention.

From the above description, it can be seen that the present invention achieves the following technical effects:

1) the method selects the mode between the rising edge and the falling edge of the second clock signal according to the phase difference between the first clock signal and the second clock signal to acquire the first data signal corresponding to the first clock signal so as to obtain the second clock signal which corresponds to the second clock signal and meets the requirement on the timing margin, thereby realizing the control of the timing margin of the data signal on the transmission path of the cross-clock domain transmission;

2) through reasonable arrangement of the first preset interval and the second preset interval, the design requirement for clock domain crossing transmission of the data signals can be met, and the clock domain crossing transmission reliability of the data signals is improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.