CN103729320A - Method for implementing CY7C68013 communication on basis of FPGA (field programmable gate array) - Google Patents

The invention relates to a method for implementing CY7C68013 communication on the basis of an FPGA (field programmable gate array). The method is used for communicating the FPGA with a USB (universal serial bus) chip CY7C68013, a fifo (first in first out) device is added into the FPGA for caching data, and accordingly loss of the data can be prevented; a function of transmitting data with high priorities in a prior manner is realized under the control of a state machine; an internal circuit of the FPGA comprises an FPGA interface module and a modulation, demodulation and data processing module; the FPGA interface module internally comprises three data interfaces and is used for communicating the FPGA with the chip CY7C68013, the FPGA and the chip CY7C68013 are communicated with each other via data ports of the chip CY7C68013, and 16bit data are transmitted between the FPGA and the chip CY7C68013 in each communication procedure. The method has the advantages that transmission of other data can be assuredly suspended under the control of the state machine in the FPGA and chip CY7C68013 communication procedures if the data with the high priorities arrive and transmission conditions are met, so that the important data with the high priorities can be assuredly transmitted in first time, the data are cached by the aid of fifo device, and loss of the data with low priorities can be assuredly prevented in transmission waiting procedures.

A kind of method that realizes CY7C68013 communication based on FPGA

Technical field

The present invention relates to the equipment such as communication, observing and controlling, particularly a kind of method that realizes many CY7C68013 communications based on FPGA.

Background technology

At present, along with the development of the communication technology, communication, each circuit board of measuring and controlling equipment circuit and the data transmission of usb interface are in an increasingly wide range of applications.The CY7C68013 chip of USB chip of the present invention based on CYPRESS company.Because USB chip only has the data-interface of one group of 16bit, for the transmission of several data (data, order etc.), have data jamming or transmit a certain data always and cause the problems such as other loss of datas.So not only can waste a large amount of time and wait for useful emergence message, also likely cause loss of data, the speed of communication and efficiency all can reduce greatly.

Summary of the invention

In view of the problem that present technology exists, the invention provides a kind of technical scheme that realizes CY7C68013 communication based on FPGA, the transmission that is able to realize data by the control of state machine has the object of priority.

The present invention realizes by such technical scheme: a kind of method that realizes CY7C68013 communication based on FPGA, for communicating by letter between FPGA and USB chip CY7C68013, it is characterized in that, at the inner fifo(first in first out that increases of FPGA) for data cached, prevent loss of data; The control of mated condition machine, realizes the function of the high high priority data of priority transmission;

FPGA internal circuit comprises FPGA interface module and modulation /demodulation, data processing module;

The inside of described FPGA interface module comprises three data-interfaces, and for communicating by letter of FPGA and CY7C68013 chip, the two communicates by the FPDP of CY7C68013 chip, each communications 16bit data;

Communication interface between FPGA and CY7C68013 chip adopts as gives a definition:

CY_DATA[15:0]: data path;

FLAGB: the full Status Flag of CY7C68013 chip internal fifo;

FLAGC: CY7C68013 chip internal fifo dummy status sign;

SLWR_N: write control signal, Low level effective;

PKTEND_N: write data complement mark, Low level effective;

SLRD_N: read control signal, Low level effective;

SLOE_N: exportable sign, Low level effective;

ADR[1:0]: the address ram of CY7C68013 chip internal;

Described CY7C68013 chip operation is under slave fifo pattern, and usb interface module is mainly by control circuit, and state machine forms, and wherein control circuit is for generation of read-write control signal; State machine is used for controlling execution and transmits and receive data;

PGA interface module, by three data-interfaces and CY7C68013 chip communication, has respectively three kinds of data to need transmission: A: the data that sent to CY7C68013 chip by FPGA; B: sent to the order of CY7C68013 chip by FPGA; C: sent to the order of FPGA by CY7C68013 chip.Their priority is: BCA;

PGA interface module control sequential comprises:

I part is for working as FPGA to CY info fifo non-NULL, and inner corresponding ram is pointed in the address of CY7C68013 chip and this ram is discontented, transmits the order that is sent to CY7C68013 chip by FPGA.Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete;

II part is non-full for working as CY to FPGA info fifo, and the corresponding ram non-NULL of CY7C68013 chip, and now FPGA to CY info fifo is empty, transmits the order that is sent to FPGA by CY7C68013 chip.Now SLRD_N signal is low level, reads effectively, and SLOE_N signal drags down a clock period than SLRD_N signal is Zao simultaneously, guarantees the satisfied sequential requirement by CY7C68013 chip;

III part is for working as FPGA to CY data fifo non-NULL, and FPGA to CY info fifo is empty, and CY to FPGA info fifo is for full, and the corresponding ram of CY7C68013 chip is discontented, transmits the data that sent to CY7C68013 chip by FPGA.Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete.

Advantage of the present invention is, in communication system, in the process of FPGA and CY7C68013 chip communication, by the control of state machine, can guarantee when the higher data of priority arrive and reach transmission conditions, suspend other data of transmission, the higher data of priority of prioritised transmission, to guarantee that the significant data that priority is higher can transmit in the very first time, use fifo to carry out buffer memory to data simultaneously, guarantee that the lower data of priority can not lose waiting in process waiting for transmission.

Accompanying drawing explanation

Fig. 1. data transmission general illustration;

Fig. 2. interface module control sequential schematic diagram;

Fig. 3. data transmission state transition diagram.

Embodiment

For a more clear understanding of the present invention, describe in conjunction with the accompanying drawings and embodiments the present invention in detail:

As shown in Figure 1 to Figure 3, CY7C68013 chip need to be configured to slave fifo pattern.By reading and writing data as 16bit data of the each transmission of data-interface.

The interface definition of FPGA and CY7C68013 chip is as follows:

CY_DATA[15:0]: data path;

FLAGB: the full Status Flag of CY7C68013 chip internal fifo;

FLAGC: CY7C68013 chip internal fifo dummy status sign;

SLWR_N: write control signal, Low level effective;

PKTEND_N: write data complement mark, Low level effective;

SLRD_N: read control signal, Low level effective;

SLOE_N: exportable sign, Low level effective;

ADR[1:0]: the address ram of CY7C68013 chip internal;

As shown in Figure 1, FPGA is mainly comprised of two parts: three fifo IP, and the data that enter code of the present invention for buffer memory, prevent because the higher data of transmission priority cause the loss of data that priority is lower; Steering logic, is used for producing read-write and controls the contents such as sequential, the priority of data transmission of communicating by letter of FPGA and CY7C68013 chip.

The present invention has three kinds of data needs transmission: A: the data that sent to CY7C68013 chip by FPGA; B: sent to the order of CY7C68013 chip by FPGA; C: sent to the order of FPGA by CY7C68013 chip.Their priority is: BCA.

As shown in Figure 2, be logic control circuit part.PGA interface module control sequential comprises:

I part is for working as FPGA to CY info fifo non-NULL, and inner corresponding ram is pointed in the address of CY7C68013 chip and this ram is discontented, transmits the order that is sent to CY7C68013 chip by FPGA.Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete.II part is non-full for working as CY to FPGA info fifo, and the corresponding ram non-NULL of CY7C68013 chip, and now FPGA to CY info fifo is empty, transmits the order that is sent to FPGA by CY7C68013 chip.Now SLRD_N signal is low level, reads effectively, and SLOE_N signal drags down a clock period than SLRD_N signal is Zao simultaneously, guarantees the satisfied sequential requirement by CY7C68013 chip.III part is for working as FPGA to CY data fifo non-NULL, and FPGA to CY info fifo is empty, and CY to FPGA info fifo is for full, and the corresponding ram of CY7C68013 chip is discontented, transmits the data that sent to CY7C68013 chip by FPGA.Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete.

As shown in Figure 3, be state machine transition diagram.Ten states, comprise an idle altogether.By detecting the full state of sky of each fifo, reach and make state machine redirect, realize according to the priority transmission data of BCA mentioned above.

According to the above description, in conjunction with art technology, can realize the solution of the present invention.

1. a method that realizes CY7C68013 communication based on FPGA, for communicating by letter between FPGA and USB chip CY7C68013, is characterized in that, at the inner fifo(first in first out that increases of FPGA) for data cached, prevent loss of data; The control of mated condition machine, realizes the function of the high high priority data of priority transmission;

FPGA internal circuit comprises FPGA interface module and modulation /demodulation, data processing module;

The inside of described FPGA interface module comprises three data-interfaces, and for communicating by letter of FPGA and CY7C68013 chip, the two communicates by the FPDP of CY7C68013 chip, each communications 16bit data;

Communication interface between FPGA and CY7C68013 chip adopts as gives a definition:

CY_DATA[15:0]: data path;

FLAGB: the full Status Flag of CY7C68013 chip internal fifo;

FLAGC: CY7C68013 chip internal fifo dummy status sign;

SLWR_N: write control signal, Low level effective;

PKTEND_N: write data complement mark, Low level effective;

SLRD_N: read control signal, Low level effective;

SLOE_N: exportable sign, Low level effective;

ADR[1:0]: the address ram of CY7C68013 chip internal;

Described CY7C68013 chip operation is under slave fifo pattern, and usb interface module is mainly by control circuit, and state machine forms, and wherein control circuit is for generation of read-write control signal; State machine is used for controlling execution and transmits and receive data;

PGA interface module, by three data-interfaces and CY7C68013 chip communication, has respectively three kinds of data to need transmission: A: the data that sent to CY7C68013 chip by FPGA; B: sent to the order of CY7C68013 chip by FPGA; C: sent to the order of FPGA by CY7C68013 chip; Their priority is: BCA;

PGA interface module control sequential comprises:

I part is for working as FPGA to CY info fifo non-NULL, and inner corresponding ram is pointed in the address of CY7C68013 chip and this ram is discontented, transmits the order that is sent to CY7C68013 chip by FPGA; Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete;

II part is non-full for working as CY to FPGA info fifo, and the corresponding ram non-NULL of CY7C68013 chip, and now FPGA to CY info fifo is empty, transmits the order that is sent to FPGA by CY7C68013 chip; Now SLRD_N signal is low level, reads effectively, and SLOE_N signal drags down a clock period than SLRD_N signal is Zao simultaneously, guarantees the satisfied sequential requirement by CY7C68013 chip;

III part is for working as FPGA to CY data fifo non-NULL, and FPGA to CY info fifo is empty, and CY to FPGA info fifo is for full, and the corresponding ram of CY7C68013 chip is discontented, transmits the data that sent to CY7C68013 chip by FPGA; Now SLWR_N is low level, and with effect, after data transmission completes, PKTEND_N signal is that low level represents that data transmission is complete.