CN103744807A - Memory card access control system based on programmable logic device - Google Patents

Refer to Fig. 1, the configuration diagram of a kind of storage card access control system based on programmable logic device (PLD) that it is the embodiment of the present invention.As shown in Figure 1, the storage card

10 based on programmable logic device (PLD) of the present embodiment comprises: programmable logic device (PLD) 11,

13 and PORT COM 15.Wherein, programmable logic device (PLD) 11 comprises

111 and embedded software core processor 113.Programmable logic device (PLD) 11 can be field programmable gate array (Field Programmable Gate Array, FPGA) device etc., embedded

113 can be 16 or 32 reduced instruction set computers (RSIC) soft-core processor, such as 32 RSIC NiosII series soft-core processors etc.;

13 is for the storage card of pegging graft, for example, for the SD card of pegging graft (Secure Digital Memory Card, safe digital card), mmc card (Multimedia Card, multimedia card), CF card (Compact Flash, compact flash card) or TF card (TransFLash) etc., PORT

15 is such as being network interface or USB mouth etc.It should be noted that, each functional module herein be not used for limiting for example the present invention.

Hold above-mentionedly,

13 is electrically connected to the

111 of programmable logic device (PLD) 11, and PORT COM 15 is electrically connected to the

111 of programmable logic device (PLD) 11.One of invention thought of the present invention is: embedded

113 is responsible for being plugged in the transmission of access control order of storage card of

13, the reception of command response signals and check and startup and control hardware

111 complete the data transmission between storage card and PORT

15, its

111 not direct and programmable logic device (PLD) 11 is carried out data transmission (being also the not between transmission of write/read data of storage card), therefore can eliminate the speed bottle-neck based on microcontroller+FPGA access storage card in prior art.

For ease of understanding, FPGA device, Nios II series soft-core processor and the SD card storage card access control system based on programmable logic device (PLD) of giving an example to describe in detail the embodiment of the present invention as programmable logic device (PLD) 11, embedded

113 and storage card will be usingd below.

Particularly, the

111 of Nios II series soft-core processor and FPGA device coordinates the access control realizing SD card, and data rate can be up to 25MB/S.Under data-transmission mode, Nios II series soft-core processor is responsible for starting and control data transmission, between Nios II series soft-core processor and the

111 of FPGA, do not carry out data transmission, directly by the

111 starting and control FPGA, complete the data transmission between SD card and PORT

15.

Please also refer to Fig. 1 and Fig. 2, between SD card and

15, add double-port RAM or fifo buffer (FIFO) to do data buffer storage 1110.The

111 of FPGA is responsible for the download transmission of access control order, data transmission and CRC (Cyclic Redundancy Check, CRC) that the reception of command response signals is uploaded, carried out between SD card and PORT

15 calculate and verification.For example double-port RAM 1112 is done access control command download and command response signals is uploaded between Nios II series soft-core processor and the

111 of FPGA, to utilize the second data buffer storage.Certainly, the second data buffer storage also can adopt fifo buffer to reach identical or close function and effect.

After SD card is plugged in

13 and powers on, first carry out initial configuration, complete SD card and through card certification mode (card identification mode), finally enter into data-transmission mode (data transfer mode) by unactivated state (inactive state).Under data-transmission mode:

(1) Nios II series soft-core processor sends the access control orders such as read/write data to the double-port RAM 1112 of the

111 of FPGA, by the

111 of FPGA, send access control order to SD card formation logic access settling signal, whether Nios II series soft-core processor is inquired about this logical access settling signal by GPIO interface and is completed or overtime to confirm that access control order transmits.

(2) after the access control orders such as read/write data that the

111 of SD clamping receipts FPGA transmits, for the access control order that receives of response generates command response signals and is sent to the double-port RAM 1112 in the

111 of FPGA, the

111 of FPGA can be accessed settling signal by formation logic, and the command response signals receiving is carried out to CRC check to generate CRC check status signal, whether Nios II series soft-core processor is inquired about this logical access settling signal by GPIO interface correct to confirm the CRC check state of command response message to confirm whether command response signals reception completes and inquire about CRC check status signal, and whether confirm that CRC check receives corresponding Bit (position) value of the command response signals that command response signals and check receive after correct from double-port RAM 1112 correct.

(3), after Nios II series soft-core processor passes through the verifying correctness of command response signals, start and the

111 of controlling FPGA is carried out the data transmission between SD card and PORT COM 15.In data transmission procedure, if write data to SD card, the

111 of FPGA is obtained data from PORT

15 and is stored to data buffer storage 1110 and calculates CRC, and data and 16 CRC+ position of rests are sent to SD card, formation logic access settling signal; If from SD card read data, the

111 of FPGA is taken out data to data buffer storage 1110 and calculates CRC, 16 CRC+ position of rests of reception and carry out CRC check from SD card, after CRC proofreaies and correct correctly, send data to PORT

15, the

111 of FPGA can production CRC check status signal and logical access settling signals in addition.Whether Nios II series soft-core processor can confirm whether the transmission of SD card data or reception complete, inquire about CRC check status signal by GPIO interface query logic access settling signal correct to confirm CRC check state.In addition,, if polylith (block) read/write operation, Nios II series soft-core processor also needs to send the command response signals that stops transmission command acceptance inspection SD card.

1. the storage card access control system based on programmable logic device (PLD), is characterized in that, comprising:

Programmable logic device (PLD), comprises hardware logic part and embedded software core processor;

Memory card slot, is electrically connected to the described hardware logic part of described programmable logic device (PLD) and for the storage card of pegging graft;

PORT COM, is electrically connected to the hardware logic part of described programmable logic device (PLD);

Wherein, described embedded software core processor for send access control order to described hardware logic part to send described storage card to, partly to receive that described storage card responds described access control order and the command response signals that provides the described command response signals receiving is carried out verifying correctness and started and control described hardware logic and partly carry out the data transmission between described storage card and described PORT COM from described hardware logic.

2. the storage card access control system based on programmable logic device (PLD) as claimed in claim 1, is characterized in that, described hardware logic partly comprises data buffer storage, is arranged between described memory card slot and described PORT COM.

3. the storage card access control system based on programmable logic device (PLD) as claimed in claim 2, is characterized in that, described data buffer storage is double-port RAM or fifo buffer.

4. the storage card access control system based on programmable logic device (PLD) as claimed in claim 1, is characterized in that, described hardware logic partly comprises the second data buffer storage, for the download of described access control order and uploading of described command response signals.

5. the storage card access control system based on programmable logic device (PLD) as claimed in claim 1, is characterized in that, described hardware logic part is also calculated and verification for CRC.

6. the storage card access control system based on programmable logic device (PLD) as claimed in claim 1, is characterized in that, described programmable logic device (PLD) is FPGA device.

7. the storage card access control system based on programmable logic device (PLD) as claimed in claim 6, is characterized in that, described embedded software core processor is 16 or 32 reduced instruction set computer soft-core processors.

8. the storage card access control system based on programmable logic device (PLD) as claimed in claim 1, is characterized in that, described memory card slot be used for pegging graft SD card, mmc card, CF card or TF card.

9. the storage card access control system based on programmable logic device (PLD), is characterized in that, comprising:

Programmable logic device (PLD), comprises hardware logic part and embedded software core processor;

Memory card slot, is electrically connected to the described hardware logic part of described programmable logic device (PLD) and for the storage card of pegging graft;

PORT COM, is electrically connected to the hardware logic part of described programmable logic device (PLD);

Wherein, when described storage card is plugged in described memory card slot and is operated in data-transmission mode, described embedded software core processor is responsible for the access control of described storage card but and between described hardware logic part, is not transmitted the write/read data of described storage card.

10. the storage card access control system based on programmable logic device (PLD) as claimed in claim 9, is characterized in that, described programmable logic device (PLD) is FPGA device.