CN103916122B - Configurable voltage-controlled oscillator applied to FPGA - Google Patents

一种应用于FPGA的可配置压控振荡器。该压控振荡器的核心部分为一个环形振荡器，该环形振荡器具有额外的数字控制信号用对振荡中心频率进行控制。利用FPGA的配置信息对控制信号进行配置，可以调节压控振荡器的中心频率，使得该压控振荡器的输出频率可以在极大的范围内连续调节。

A configurable voltage-controlled oscillator for FPGA applications. The core part of the voltage-controlled oscillator is a ring oscillator, and the ring oscillator has an additional digital control signal to control the oscillation center frequency. The control signal is configured by using the configuration information of the FPGA, and the center frequency of the voltage-controlled oscillator can be adjusted, so that the output frequency of the voltage-controlled oscillator can be continuously adjusted within a very large range.

一种应用于FPGA的可配置压控振荡器A Configurable Voltage Controlled Oscillator Applied in FPGA

技术领域technical field

本发明涉及一种压控振荡器，特别是一种应用于FPGA中的频率范围较宽的可配置压控振荡器。The invention relates to a voltage-controlled oscillator, in particular to a configurable voltage-controlled oscillator with a wide frequency range applied in FPGA.

背景技术Background technique

压控振荡器(以下简称VCO)本质上是一种振荡器，震荡频率受控制电压控制并可在一定的范围内调节是VCO与普通振荡器的区别。这一特性使得VCO在锁相环(以下简称PLL)中有着广泛的应用。A voltage-controlled oscillator (hereinafter referred to as VCO) is essentially an oscillator. The oscillation frequency is controlled by a control voltage and can be adjusted within a certain range, which is the difference between a VCO and an ordinary oscillator. This feature makes the VCO widely used in phase-locked loops (hereinafter referred to as PLLs).

图1是典型PLL结构示意图，其工作原理如下：鉴频鉴相器比较参考时钟与反馈钟的频率与相位关系，电荷泵与低通滤波器调节控制电压，调节VCO的振荡频率，保证输出时钟与参考时钟有精确的频率与相位关系。一般来说，PLL可工作的频率范围受VCO的工作频率范围限制。Figure 1 is a schematic diagram of a typical PLL structure, and its working principle is as follows: the frequency and phase detector compares the frequency and phase relationship between the reference clock and the feedback clock, the charge pump and the low-pass filter adjust the control voltage, adjust the oscillation frequency of the VCO, and ensure the output clock Have a precise frequency and phase relationship with the reference clock. Generally, the operating frequency range of the PLL is limited by the operating frequency range of the VCO.

现场可编程逻辑门阵列(以下简称FPGA)中集成了大量的可编程逻辑资源，必须使用PLL保证时钟质量、提高系统整体性能。另一方面，不同的用户可能需要FPGA工作在不同的时钟频率之下，因此需要PLL可以在极宽的频率范围内可靠地工作。然而，传统的VCO仅可以在某一个特定的频率附近进行调节，限制了PLL可以应用的范围与场合。本发明的VCO主要集成在FPGA中，利用FPGA的可编程特性，将振荡频率的可调节范围极大的扩展，使得PLL可以在极宽的频率范围内可靠的工作。Field Programmable Logic Gate Array (hereinafter referred to as FPGA) integrates a large number of programmable logic resources, and PLL must be used to ensure clock quality and improve overall system performance. On the other hand, different users may require the FPGA to work at different clock frequencies, thus requiring the PLL to work reliably over a wide frequency range. However, the traditional VCO can only be adjusted around a specific frequency, which limits the application range and occasions of the PLL. The VCO of the present invention is mainly integrated in the FPGA, and the adjustable range of the oscillation frequency is greatly expanded by utilizing the programmable feature of the FPGA, so that the PLL can work reliably in an extremely wide frequency range.

发明内容Contents of the invention

本发明的技术解决问题是：克服现有技术的不足，提供了一种应用于FPGA的可配置压控振荡器器。The technical problem of the present invention is to overcome the deficiencies of the prior art and provide a configurable voltage-controlled oscillator applied to FPGA.

本发明的技术解决方案是：Technical solution of the present invention is:

一种应用于FPGA的可配置压控振荡器器，包括：NMOS管M1、M2、M3、M4、M11、M12、M13、M14、M31、M32、M42、PMOS管M21、M22、M23、M41、电容C43、施密特反相器G51和与非门G61；A configurable voltage-controlled oscillator applied to FPGA, including: NMOS transistors M1, M2, M3, M4, M11, M12, M13, M14, M31, M32, M42, PMOS transistors M21, M22, M23, M41, Capacitor C43, Schmidt inverter G51 and NAND gate G61;

NMOS管M1、M2、M3、M4的源极接地，栅极接外部输入的频率控制电压V_control，漏极分别接NMOS管M11、M12、M13、M14的源极；The sources of the NMOS transistors M1, M2, M3, and M4 are grounded, the gates are connected to the external input frequency control voltage V _control , and the drains are respectively connected to the sources of the NMOS transistors M11, M12, M13, and M14;

NMOS管M11、M12、M13、M14的栅极接配置信号D_control，漏极与PMOS管M21的栅极、PMOS管M21的漏极、PMOS管M22的栅极以及PMOS管M23的栅极连接在一起；The gates of the NMOS transistors M11, M12, M13, and M14 are connected to the configuration signal D _control , and the drains are connected to the gate of the PMOS transistor M21, the drain of the PMOS transistor M21, the gate of the PMOS transistor M22, and the gate of the PMOS transistor M23. Together;

PMOS管M21的源极接电源，PMOS管M22的源极接电源，PMOS管M23的源极接电源，PMOS管M23的漏极接PMOS管M41的源极，NMOS管M31的源极接地，NMOS管M31的栅极、NMOS管M31的漏极、PMOS管M22的漏极、NMOS管M32的栅极连接在一起；The source of the PMOS transistor M21 is connected to the power supply, the source of the PMOS transistor M22 is connected to the power supply, the source of the PMOS transistor M23 is connected to the power supply, the drain of the PMOS transistor M23 is connected to the source of the PMOS transistor M41, the source of the NMOS transistor M31 is grounded, and the NMOS transistor M31 is connected to the source. The gate of the transistor M31, the drain of the NMOS transistor M31, the drain of the PMOS transistor M22, and the gate of the NMOS transistor M32 are connected together;

NMOS管M32的源极接地，漏极接NMOS管M42的源极；PMOS管M41的栅极与NMOS管M42的栅极连接，同时，PMOS管M41的栅极还与与非门G61的输出端连接在一起；The source of the NMOS transistor M32 is grounded, and the drain is connected to the source of the NMOS transistor M42; the gate of the PMOS transistor M41 is connected to the gate of the NMOS transistor M42, and at the same time, the gate of the PMOS transistor M41 is also connected to the output terminal of the NAND gate G61 connected;

PMOS管M41的漏极与NMOS管M42的漏极连接，同时，PMOS管M41的漏极还通过电容C43接地，PMOS管M41的漏极还通过施密特反相器G51连接到与非门G61的一个输出端，PMOS管M41的漏极连接施密特反相器G51的输入端；与非门G61的另一个输入端连接使能信号EN，与非门G61的输出既为所述整个可配置压控振荡器器的输出时钟CLK_OUT。The drain of the PMOS transistor M41 is connected to the drain of the NMOS transistor M42, and at the same time, the drain of the PMOS transistor M41 is grounded through the capacitor C43, and the drain of the PMOS transistor M41 is also connected to the NAND gate G61 through the Schmitt inverter G51 One output end of the PMOS transistor M41 is connected to the input end of the Schmitt inverter G51; the other input end of the NAND gate G61 is connected to the enable signal EN, and the output of the NAND gate G61 is both the entire available Configure the output clock CLK_OUT of the VCO.

频率控制电压V_control与配置信号D_control共同控制电容C43充放电速率，控制输出时钟CLK_OUT的频率。The frequency control voltage V _control and the configuration signal D _control jointly control the charge and discharge rate of the capacitor C43 and control the frequency of the output clock CLK_OUT.

本发明与现有技术相比的优点在于：The advantage of the present invention compared with prior art is:

本发明利用FPGA的可编程特性，通过配置信息改变压控振荡器VCO的硬件工作条件来实现输出频率范围的扩展。与传统的VCO相比，本发明的VCO拥有更宽的频率调节范围。The invention utilizes the programmable characteristic of FPGA to change the hardware working conditions of the voltage-controlled oscillator VCO through configuration information to realize the extension of the output frequency range. Compared with the traditional VCO, the VCO of the present invention has a wider frequency adjustment range.

附图说明Description of drawings

图1为传统的PLL结构示意图；FIG. 1 is a schematic diagram of a traditional PLL structure;

图2为使用本发明VCO的PLL结构示意图；FIG. 2 is a schematic diagram of a PLL structure using a VCO of the present invention;

图3为本发明VCO电路原理示意图；Fig. 3 is the principle schematic diagram of VCO circuit of the present invention;

图4为本发明VCO工作时各节点电压波形示意图。FIG. 4 is a schematic diagram of voltage waveforms of each node when the VCO of the present invention is working.

具体实施方式detailed description

本发明的VCO引入了额外的控制信号，利用FPGA的配置信息进行控制，通过改变VCO的硬件工作条件来实现输出频率调节范围的扩展。The VCO of the present invention introduces additional control signals, is controlled by FPGA configuration information, and expands the output frequency adjustment range by changing the hardware working conditions of the VCO.

一种使用本发明的PLL电路如图2所示。当使用图2的VCO时，根据配置信息的不同，VCO的输出频率可以分别在一系列区间内调节，每个小区间的可调范围与图1中VCO相当。使用图2所示VCO的PLL的输出频率范围是所有区间的总合，这样频率调整区间借助配置特性得到了扩展。A PLL circuit using the present invention is shown in FIG. 2 . When using the VCO in Figure 2, the output frequency of the VCO can be adjusted in a series of intervals according to different configuration information, and the adjustable range of each cell is equivalent to that of the VCO in Figure 1. The output frequency range of the PLL using the VCO shown in Figure 2 is the sum of all intervals, so that the frequency adjustment interval is extended by means of configuration features.

图3所示为本发明所设计的压控振荡器的电路。其中包括NMOS管M1、M2、M3、M4，NMOS管M11、M12、M13、M14，PMOS管M21、M22、M23，NMOS管M31、M32，PMOS管M41，NMOS管M42，电容C43，施密特反相器G51，与非门G61。Fig. 3 shows the circuit of the voltage-controlled oscillator designed by the present invention. These include NMOS tubes M1, M2, M3, M4, NMOS tubes M11, M12, M13, M14, PMOS tubes M21, M22, M23, NMOS tubes M31, M32, PMOS tubes M41, NMOS tubes M42, capacitors C43, Schmidt Inverter G51, NAND gate G61.

连接关系如图3所示。NMOS管M1、M2、M3、M4的源极接地，栅极接外部输入的频率控制电压V_control，漏极分别接NMOS管M11、M12、M13、M14的源极；The connection relationship is shown in Figure 3. The sources of the NMOS transistors M1, M2, M3, and M4 are grounded, the gates are connected to the external input frequency control voltage V _control , and the drains are respectively connected to the sources of the NMOS transistors M11, M12, M13, and M14;

NMOS管M11、M12、M13、M14的栅极接配置信号D_control，漏极与PMOS管M21的栅极、PMOS管M21的漏极、PMOS管M22的栅极以及PMOS管M23的栅极连接在一起；The gates of the NMOS transistors M11, M12, M13, and M14 are connected to the configuration signal D _control , and the drains are connected to the gate of the PMOS transistor M21, the drain of the PMOS transistor M21, the gate of the PMOS transistor M22, and the gate of the PMOS transistor M23. Together;

PMOS管M21的源极接电源，PMOS管M22的源极接电源，PMOS管M23的源极接电源，PMOS管M23的漏极接PMOS管M41的源极，NMOS管M31的源极接地，NMOS管M31的栅极、NMOS管M31的漏极、PMOS管M22的漏极、NMOS管M32的栅极连接在一起；The source of the PMOS transistor M21 is connected to the power supply, the source of the PMOS transistor M22 is connected to the power supply, the source of the PMOS transistor M23 is connected to the power supply, the drain of the PMOS transistor M23 is connected to the source of the PMOS transistor M41, the source of the NMOS transistor M31 is grounded, and the NMOS transistor M31 is connected to the source. The gate of the transistor M31, the drain of the NMOS transistor M31, the drain of the PMOS transistor M22, and the gate of the NMOS transistor M32 are connected together;

NMOS管M32的源极接地，漏极接NMOS管M42的源极；PMOS管M41的栅极与NMOS管M42的栅极连接，同时，PMOS管M41的栅极还与与非门G61的输出端连接在一起；The source of the NMOS transistor M32 is grounded, and the drain is connected to the source of the NMOS transistor M42; the gate of the PMOS transistor M41 is connected to the gate of the NMOS transistor M42, and at the same time, the gate of the PMOS transistor M41 is also connected to the output terminal of the NAND gate G61 connected;

PMOS管M41的漏极与NMOS管M42的漏极连接，同时，PMOS管M41的漏极还通过电容C43接地，PMOS管M41的漏极还通过施密特反相器G51连接到与非门G61的一个输入端，PMOS管M41的漏极连接施密特反相器G51的输入端；与非门G61的另一个输入端连接使能信号EN，与非门G61的输出即为所述整个可配置压控振荡器器的输出时钟CLK_OUT。The drain of the PMOS transistor M41 is connected to the drain of the NMOS transistor M42, and at the same time, the drain of the PMOS transistor M41 is grounded through the capacitor C43, and the drain of the PMOS transistor M41 is also connected to the NAND gate G61 through the Schmitt inverter G51 One input terminal of the PMOS transistor M41 is connected to the input terminal of the Schmitt inverter G51; the other input terminal of the NAND gate G61 is connected to the enable signal EN, and the output of the NAND gate G61 is the entire programmable Configure the output clock CLK_OUT of the VCO.

与非门G61的输出既是整个电路的输出，记为CLK_OUT；记连接PMOS管M41的漏极、NMOS管M42的漏极、电容C43的一端、施密特反相器G51输入端的节点为N1；N2节点为施密特反相器G51的输出和与非门G61的一个输入端之间的节点。The output of the NAND gate G61 is the output of the entire circuit, which is recorded as CLK_OUT; the node connected to the drain of the PMOS transistor M41, the drain of the NMOS transistor M42, one end of the capacitor C43, and the input end of the Schmitt inverter G51 is N1; The N2 node is a node between the output of the Schmitt inverter G51 and one input terminal of the NAND gate G61.

PMOS管M41、NMOS管M42的功能类似一个反相器，其输入是PMOS管M41与NMOS管M42的栅极，输出是PMOS管M41与NMOS管M42的漏极，其电流驱动强度受PMOS管M23与NMOS管M32控制。EN为1时，与非门G61的功能相当于一个反相器，与PMOS管M41与NMOS管M42、施密特反相器G51组成了一个3级环振，实现振荡器的功能。EN使能后顺序发生如下事件：CLK_OUT由1变为0，N1缓慢的由0上升为1，N2由1变为0，CLK_OUT由0变为1，N1缓慢的由1下降为0，N2由0变为1。之后不断重复该过程，直到EN变为0环路停止振荡，电路回到初始状态。The functions of the PMOS transistor M41 and the NMOS transistor M42 are similar to an inverter, the input of which is the gate of the PMOS transistor M41 and the NMOS transistor M42, the output is the drain of the PMOS transistor M41 and the NMOS transistor M42, and its current driving strength is determined by the PMOS transistor M23 Controlled with NMOS tube M32. When EN is 1, the function of the NAND gate G61 is equivalent to an inverter, together with the PMOS transistor M41, the NMOS transistor M42, and the Schmidt inverter G51 form a three-stage ring oscillator to realize the function of the oscillator. After EN is enabled, the following events occur in sequence: CLK_OUT changes from 1 to 0, N1 slowly rises from 0 to 1, N2 changes from 1 to 0, CLK_OUT changes from 0 to 1, N1 slowly decreases from 1 to 0, N2 changes from 0 becomes 1. Afterwards, this process is repeated until EN becomes 0, the loop stops oscillating, and the circuit returns to the initial state.

N1电压改变的速率由电容C43充放电速度确定，而电容C43充电电流大小受PMOS管M23控制，放电电流大小受NMOS管M32控制。PMOS管M21、M22、M23与NMOS管M31、M32分别组成电流镜，电容C43充放电电流最终由NMOS管M1、M2、M3、M4与NMOS管M11、M12、M13、M14的工作状态确定。D_control为4位宽信号，每一位分别确定NMSO管M11、M12、M13、M14是否允许电流通过，决定了VCO工作的频率区间；V_control决定NMOS管M1、M2、M3、M4中每个NMOS管中电流的大小，使VCO的输出频率可以在某个区间内连续调节。V_control与D_control最终决定电容C43充放电速率，也就决定了VCO的振荡周期。为便于说明，本发明取D_control为4位宽信号，可以控制4条支路的通、断。D_control可以为任意位宽信号，每位控制一条支路。The rate at which the N1 voltage changes is determined by the charge and discharge speed of the capacitor C43, while the charge current of the capacitor C43 is controlled by the PMOS transistor M23, and the discharge current is controlled by the NMOS transistor M32. PMOS tubes M21, M22, M23 and NMOS tubes M31, M32 form a current mirror respectively, and the charging and discharging current of capacitor C43 is finally determined by the working states of NMOS tubes M1, M2, M3, M4 and NMOS tubes M11, M12, M13, M14. D _control is a 4-bit wide signal, and each bit determines whether the NMSO tubes M11, M12, M13, and M14 allow current to pass through, and determines the frequency range where the VCO works; V _control determines each of the NMOS tubes M1, M2, M3, and M4. The magnitude of the current in the NMOS tube enables the output frequency of the VCO to be continuously adjusted within a certain range. V _control and D _control ultimately determine the charge and discharge rate of the capacitor C43, which also determines the oscillation period of the VCO. For ease of description, the present invention takes D _control as a 4-bit wide signal, which can control the on and off of four branches. D _control can be a signal with any bit width, and each bit controls a branch.

图4所示为D_control不同时VCO振荡频率范围，VCO可工作的振荡频率为各分立区间的总和。注意，为保证振荡频率区间连续，不同D_control指定的振荡频率区间必须有重叠。Figure 4 shows the VCO oscillation frequency range when D _control is different, and the VCO's workable oscillation frequency is the sum of each discrete interval. Note that in order to ensure the continuity of the oscillation frequency interval, the oscillation frequency intervals specified by different D _control must overlap.