CN104008082A - Converter of 1553B bus remote terminal (RT) node and controller area network (CAN) bus - Google Patents

The invention provides a converter of a 1553B bus remote terminal (RT) node and a controller area network (CAN) bus and aims to provide a flexible and reliable converter capable of rapidly connecting a 1553bus and the CAN bus. According to the technical scheme of the converter, a digital signal processor (DSP) chip accesses an intellectual property (IP) core of a 1553B RT of a field programmable gate array (FPGA) and a CAN protocol chip through addresses, data and control signal lines, receives an interrupt signal produced by the IP core of the 1553B RT of the FPGA and the CAN protocol chip, dispatches a control software operation platform to read and configure 1553B bus RT node parameters and CAN bus node parameters, and achieves conversion of the 1553B bus RT node and the CAN node on a data application layer. According to an FPGA chip, a mode of the IP core of the 1553B RT is used as a 1553B bus protocol controller, and a 1553B interface drives a transformer circuit to access a 1553B bus network to link a physical layer of a 1553B bus; the CAN protocol chip is combined with a CAN isolation drive circuit to access a CAN bus network.

The converter of 1553B bus RT node and CAN bus

Technical field

The present invention relates in a kind of technical field of information processing the converter about 1553B bus RT node and CAN bus.

Background technology

In control system, normal employing simultaneously has the 1553B bus of higher reliability and CAN bus to carry out apparatus interconnection, although adopt the 1553B bus of the asynchronous operation of instruction/response mode and two Redundancy Design, there is more high reliability, compare CAN bus cost higher.CAN bus belongs to a kind of industrial bus, has higher cost performance.A lot of commercial units are all provided with CAN bus interface, due to the needs of control mode and mode of intelligence transmission conversion, in some TT&C system, often have the bus conversion between 1553B bus and CAN bus.Due to the excellent performance of CAN bus in its automobile electronic system, increasing user's concern and approval have been subject to.

These two kinds of buses are all the buses that transfer rate is high, reliability is high, real-time performance is good, but they all exist certain deficiency.Arbitrary data transfer of 1553B bus is all by the host node beginning of giving an order, from node is received order, resolve and carry out, corresponding state is fed back to host node simultaneously, this reduces the data transmission rate on network greatly, and make master node control very busy, and in lower end, occur that when abnormal, data can not be uploaded immediately, the transmission command that must wait for host node, dirigibility is poor.And CAN bus is many main competing buses, can better address this problem.But CAN bus also exists a lot of deficiencies, for example it cannot equally with 1553B bus provide a more definite response time, and there is no two redundancies or the design of many redundancy structures, and this makes the reliability of CAN bus and real-time be not so good as 1553B.But 1553B bus hardware cost is very high, it under the same terms, is the hundred times of CAN bus, for test macro, be difficult to bear, therefore in TT&C system, for controlling, adopt 1553B buses more, for test, adopt CAN bus, and information interaction between the two has just become the key of whole system, thereby impelled the birth of prior art 1553B and CAN bus transition card.Prior art 1553B and CAN bus transition card adopt ARM9 processor as intermediate conversion platform, RTLinux operating system is as scheduling, the information realizing between 1553B bus and CAN bus by upper level applications is changed, by transition card, expand LCD interface and serial ports, realize the real-time monitoring of translation data.But how in FPGA, to design a higher asynchronous FIFO of reliability and realize the 1553B bus of high speed 4Mb/s and the conversion of the CAN bus interconnection of 1Mb/s, reduce metastable state probability of happening, also do not solve completely at present.The frame structure of 1553B bus has 2 kinds, and command word and status word share a kind of frame structure in fact, and these two kinds of frames are only synchronous head differences.In the frame of 1553B, starting 3 is synchronization bit, and data word is upper jumping edge, and command word and status word are negative edge, 4～19 is data bit, the data for transmitting in data word, and in command word and status word, be order or mode bit, last position is parity check bit.And in CAN bus, only have a kind of frame structure, be only, whether frame is expanded in employing, wherein frame is initial is comprised of single aobvious position, and arbitration is comprised of identifier and RTR position, 12 altogether, controlling filed retains position by 2 and 4 DLC positions form, data fields is comprised of 0 to 8 word, 8 of each words, and CRC field is comprised of CRC sequence and the 1 bit-identify position of 15, ACK field is defined symbol by 1 ACK gap and an ACK and is formed, and last frame end is comprised of 7 continuous recessive positions.Visible, not only frame structure is different with CAN bus for 1553B, order system is different, and the conversion method between different 1553B and CAN bus is also different, therefore the conversion between 1553B and CAN bus is not only the conversion of frame structure, also relate to the parsing of ordering between two systems, therefore the conversion regime of two kinds of buses is realized more flexibly needs certain technical support.

Summary of the invention

The present invention is directed to the weak point that above-mentioned prior art exists, propose a kind of more flexibly, reliability is higher, can make the remote terminal RT node converter of 1553B bus and CAN bus more efficiently that is connected of 1553B bus and CAN bus.

Above-mentioned purpose of the present invention can reach by following measures, the converter of a kind of 1553B bus RT node and CAN bus, comprise digital signal processing dsp chip, pin-saving chip Flash, on-site programmable gate array FPGA chip and CAN protocol chip, it is characterized in that: dsp chip is directly accessed Flash pin-saving chip by RS422 bus interface, pass through address, IP kernel and the CAN protocol chip of the 1553B remote terminal RT of data and control signal wire access FPGA, receive the IP kernel of 1553B remote terminal RT and the look-at-me of CAN protocol chip generation of FPGA, dsp chip scheduling controlling software running platform reads, configures 1553B bus RT node parameter, CAN bus node parameter, in data application layer, complete the conversion of 1553B bus RT node and CAN bus, and the configuration parameter of two kinds of buses of pin-saving chip Flash and the storage of format transformation data, the IP kernel pattern of the remote terminal RT of fpga chip employing 1553B is as 1553B bus protocol controller, by 1553B interface driver transformer circuit access 1553B bus network, the Physical layer of link 1553B bus, CAN protocol chip is as CAN bus protocol controller, by CAN isolated drive circuit access CAN bus network.

The present invention has following beneficial effect than prior art.

The present invention with the equipment of CAN bus interface with remote terminal (Remote Terminal, RT) mode of node accesses 1553B bus system, completes 1553B bus more quick with being connected of CAN bus with 1553B bus RT node and the converter of CAN bus.The present invention adopts dsp chip as bus data conversion and scheduling controlling software running platform, completes the conversion of 1553B bus RT node and CAN bus in data application layer.The 1553B remote terminal RT module I P core of FPGA, the start bit, the check bit that complete 1553B produce, the encapsulation of the 1553B protocol layers such as repeat-back.By 1553B interface driving circuit and transformer circuit, be linked to the Physical layer of 1553B bus.CAN protocol chip, as CAN bus protocol controller, completes the encapsulation of the CAN protocol layers such as heading, check bit, response bits.By CAN isolated drive circuit, be linked to the Physical layer of CAN bus.

User is sent to the present invention such as 1553B bus parameter (as RT address, subaddressing etc.), CAN bus parameter (as baud rate, frame format etc.) and data transfer method parameter and is saved in Flash pin-saving chip by RS422.Start the present invention, by dsp software operation, read parameter, configuration 1553B bus RT node parameter and CAN bus node parameter, and the conversion between the enterprising row bus of market demand, the pilot lamp of controlling by DSP and RS422 interface are shown and communication, have been realized the real-time monitoring of translation data.Change in a word parameter configuration files of the present invention, can complete multiple 1553B bus RT node to the conversion of CAN bus apparatus, without former communication software is done and changed.

Accompanying drawing explanation

Figure below further illustrates the present invention in conjunction with the accompanying drawings and embodiments, but does not therefore limit the present invention among affiliated scope of embodiments.

Fig. 1 is the remote terminal RT node of 1553B bus of the present invention and the theory of constitution schematic diagram of CAN bus converter.

Fig. 2 is remote terminal RT node and the CAN bus converter dsp software process flow diagram of 1553B bus of the present invention.

Embodiment

Consult Fig. 1.The remote terminal RT node of 1553B bus and CAN bus converter, comprise dsp chip, Flash pin-saving chip, fpga chip and CAN protocol chip.DSP, as bus data conversion and scheduling controlling software running platform, completes the conversion of 1553B bus RT node and CAN bus in data application layer.The external a plurality of pilot lamp of dsp chip and RS422 interface, can [a1] directly access Flash pin-saving chip, IP kernel and the CAN protocol chip of 1553B remote terminal RT by home address, data and the addressable FPGA of control signal wire, can receive the IP kernel of 1553B remote terminal RT of FPGA and the look-at-me that CAN protocol chip produces simultaneously.1553B remote terminal RT module I P core will produce interruption to dsp chip after receiving 1553B bus data, the start bit, the check bit that complete 1553B produce, the encapsulation of the 1553B protocol layers such as repeat-back, by the Physical layer of 1553B interface driving circuit transformer circuit link 1553B bus, access 1553B bus network simultaneously; CAN bus apparatus is isolated the Physical layer of change-over circuit link CAN bus by CAN, CAN protocol chip is as CAN bus protocol controller, complete the encapsulation of the CAN protocol layers such as heading, check bit, response bits, and after receiving corresponding data, produce interruption to DSP, the reading out data of having no progeny during DSP receives, according to frame ID identification code judged result, carry out Data Format Transform, by the RT address comprising in frame ID identification code and subaddressing and data, write the 1553B remote terminal RT module I P core of corresponding FPGA.

The IP kernel pattern of the remote terminal RT of fpga chip employing 1553B is as 1553B bus protocol controller, by 1553B interface driving circuit and transformer circuit access 1553B bus network, the Physical layer of link 1553B bus; CAN protocol chip is as CAN bus protocol controller, by CAN isolated drive circuit access CAN bus network.The 1553B remote terminal RT module I P core of FPGA, in conjunction with 1553B interface driving circuit and transformer circuit, completes the encapsulation of 1553B protocol layer and the Physical layer link of 1553B bus.CAN protocol chip, in conjunction with CAN isolated drive circuit, completes encapsulation and the Physical layer link of CAN bus protocol layer.CAN protocol chip produces and interrupts to dsp chip after receiving CAN bus data.

Fpga chip adopts RT module I P core as 1553B bus protocol controller, by 1553B interface driving circuit and transformer circuit access 1553B bus network, the data that DSP will be able to be sent send to 1553B bus after encapsulating by 1553B protocol layer, the Data Analysis encapsulation that also can receive 1553B bus extracts valid data, by producing interrupt notification DSP, reads.

CAN protocol chip is as CAN bus protocol controller, by CAN isolated drive circuit access CAN bus network, the data that DSP will be able to be sent send to CAN bus after encapsulating by CAN protocol layer, the Data Analysis encapsulation that also can receive CAN bus extracts valid data, by producing interrupt notification DSP, reads.

DSP thes contents are as follows data-switching between 1553B bus and CAN bus shown in table:

Consult Fig. 2.Bus data conversion and the scheduling controlling running software of dsp operation have been the cores of the conversion of 1553B bus RT node and CAN bus.

Whole software is mainly two flow processs, and data that receive for 1553B bus transfer CAN bus data to, and another data that receive for CAN bus transfer 1553B bus data to.

1553B bus reception data are converted to CAN bus data flow process and are: 1553B bus sends data to the remote terminal RT of appointment, by the 1553B remote terminal RT module I P core of FPGA, receive after corresponding data and produce and interrupt to DSP, during DSP receives, have no progeny and read complete data, according to bus converted contents, surely generate frame ID identification code and the data layout of corresponding CAN bus, if data are greater than 4 words, in frame ID identification code, generate corresponding subpackage sequence number and subpackage sum, and data need to be carried out to repeatedly subpackage and send to CAN bus, until data are sent, finally relevant transitional information is transmitted and reached real-time monitoring by pilot lamp and RS422.

CAN bus reception data are converted to 1553B bus data flow process and are: CAN protocol chip produces and interrupts to DSP after receiving corresponding data, the reading out data of having no progeny during DSP receives, according to frame ID identification code, judge whether to need group bag, if need group bag, wait for and receive complete data.After pending data reception is complete, carry out Data Format Transform, by the RT address comprising in frame ID identification code and subaddressing and data, write the 1553B remote terminal RT module I P core of corresponding FPGA.