CN104051344B - Semiconductor arrangement and formation thereof - Google Patents

A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.

半导体布置及其形成Semiconductor layout and its formation

技术领域technical field

本发明总的来说涉及半导体领域，更具体地，涉及一种半导体布置及其形成方法。The present invention generally relates to the field of semiconductors, and more particularly, to a semiconductor arrangement and a method for forming the same.

背景技术Background technique

在诸如晶体管的半导体器件中，当将足够电压或偏压施加至器件的栅极时，电流流过源极区和漏极区之间的沟道区。当电流流过沟道区时，器件通常被认为处于“接通”状态，并且当电流不流过沟道区时，器件通常被认为处于“关闭”状态。In a semiconductor device such as a transistor, when a sufficient voltage or bias is applied to the gate of the device, current flows through the channel region between the source and drain regions. When current is flowing through the channel region, the device is generally considered to be in the "on" state, and when current is not flowing through the channel region, the device is generally considered to be in the "off" state.

发明内容Contents of the invention

根据本发明的一个方面，提供了一种半导体制造方法，包括：形成具有第一工作电压的多个第一晶体管，多个第一晶体管包括在衬底的第一晶体管区域之上的多个第一栅极结构、邻近多个第一栅极结构的多个低压浅阱、以及邻近多个第一栅极结构的多个低压口袋注入区；以及邻近多个第一晶体管形成具有第二工作电压的多个第二晶体管。形成多个第二晶体管包括：在多个第一栅极结构之上、在第一晶体管区域之上并且在多个第二栅极结构之上形成第一高压光刻胶，多个第二栅极结构在衬底的第二晶体管区域之上，使得暴露邻近多个第二栅极结构的衬底的多个高压注入区和多个第二栅极结构的多个第二栅极顶部；以第一高能量执行高压LDD注入，以将第一高压掺杂物注入到多个高压注入区中，从而形成邻近多个第二栅极结构的多个高压浅阱；以及以第二高能量执行高压口袋注入，以将第二高压掺杂物注入到多个高压注入区中，从而形成邻近多个第二栅极结构的多个高压口袋注入区。According to one aspect of the present invention, there is provided a semiconductor manufacturing method, comprising: forming a plurality of first transistors having a first operating voltage, the plurality of first transistors including a plurality of first transistors over a first transistor region of a substrate A gate structure, a plurality of low voltage shallow wells adjacent to the first gate structures, and a plurality of low voltage pocket implant regions adjacent to the first gate structures; and a second operating voltage formed adjacent to the first transistors multiple second transistors. Forming the plurality of second transistors includes: forming a first high voltage photoresist over the plurality of first gate structures, over the first transistor region and over the plurality of second gate structures, the plurality of second gate structures a pole structure over the second transistor region of the substrate such that the plurality of high voltage implant regions of the substrate adjacent to the plurality of second gate structures and the plurality of second gate tops of the plurality of second gate structures are exposed; performing a high voltage LDD implant at a first high energy to implant a first high voltage dopant into a plurality of high voltage implant regions, thereby forming a plurality of high voltage shallow wells adjacent to a plurality of second gate structures; and performing at a second high energy High voltage pocket implantation for implanting a second high voltage dopant into the plurality of high voltage implantation regions, thereby forming a plurality of high voltage pocket implantation regions adjacent to the plurality of second gate structures.

优选地，形成多个第一晶体管包括：在第二晶体管区域之上并且在多个第二栅极结构之上形成低压光刻胶，使得暴露多个第一栅极结构和邻近多个第一栅极结构的衬底的多个低压注入区；以第一低能量执行低压LDD注入，以将第一电压掺杂物注入到多个低压注入区中，从而形成多个低压浅阱；以及以第二低能量执行低压口袋注入，以将第二低压掺杂物注入到多个低压注入区中，从而形成多个低压口袋注入区。Preferably, forming the plurality of first transistors includes: forming a low voltage photoresist over the second transistor region and over the plurality of second gate structures, exposing the plurality of first gate structures and the adjacent plurality of first gate structures. a plurality of low-voltage implantation regions of the substrate of the gate structure; performing low-voltage LDD implantation with a first low energy, so as to implant the first voltage dopant into the plurality of low-voltage implantation regions, thereby forming a plurality of low-voltage shallow wells; and The low-voltage pocket implantation is performed at a second low energy to implant the second low-voltage dopant into the plurality of low-voltage implantation regions, thereby forming a plurality of low-voltage pocket implantation regions.

优选地，该方法包括：在衬底之上形成第一层栅极介电材料；从衬底的第一晶体管区域去除第一层栅极介电材料，使得高压栅极电介质的第一部分留在衬底的第二晶体管区域之上；在衬底之上并且在高压栅极电介质的第一部分之上形成第二层栅极介电材料，使得低压栅极电介质留在衬底的第一晶体管区域之上，并且高压栅极电介质留在衬底的第二晶体管区域之上，其中，高压栅极电介质包括第一部分和来自第二层栅极介电材料的第二部分；在低压栅极电介质和高压栅极电介质之上形成栅电极材料层；以及图案化层栅电极材料层、低压栅极电介质和高压栅极电介质，以同时形成多个第一栅极结构和多个第二栅极结构。Preferably, the method comprises: forming a first layer of gate dielectric material over the substrate; removing the first layer of gate dielectric material from the first transistor region of the substrate such that a first portion of the high voltage gate dielectric remains over the second transistor region of the substrate; forming a second layer of gate dielectric material over the substrate and over the first portion of the high voltage gate dielectric such that the low voltage gate dielectric remains in the first transistor region of the substrate and a high voltage gate dielectric is left over the second transistor region of the substrate, wherein the high voltage gate dielectric includes a first portion and a second portion from a second layer of gate dielectric material; between the low voltage gate dielectric and forming a layer of gate electrode material over the high voltage gate dielectric; and patterning the layer of gate electrode material, the low voltage gate dielectric, and the high voltage gate dielectric to simultaneously form a plurality of first gate structures and a plurality of second gate structures.

优选地，该方法包括：在多个第一栅极结构、多个第二栅极结构和衬底之上形成侧壁材料层；以及图案化侧壁材料层，以同时形成邻近多个第一栅极结构的多个第一侧壁隔离物和邻近第二栅极结构的多个第二侧壁隔离物。Preferably, the method includes: forming a sidewall material layer over the plurality of first gate structures, the plurality of second gate structures and the substrate; and patterning the sidewall material layer to simultaneously form adjacent to the plurality of first gate structures. A plurality of first sidewall spacers of the gate structure and a plurality of second sidewall spacers adjacent to the second gate structure.

优选地，执行低压口袋注入包括：通过所选额定电压，注入在器件制造中使用的剂量。Preferably, performing the low voltage pocket implant comprises: injecting a dose used in device fabrication via a selected nominal voltage.

优选地，多个第一晶体管与多个第二晶体管的类型不同。Preferably, the plurality of first transistors is of a different type than the plurality of second transistors.

优选地，执行高压LDD注入包括：注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。Preferably, performing high voltage LDD implantation includes: implanting at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.

优选地，执行高压口袋注入包括：注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。Preferably, performing high voltage pocket implantation includes: implanting at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon.

根据本发明的另一方面，提供了一种半导体制造方法，包括：在衬底的第一晶体管区域和衬底的第二晶体管区域之上形成第一高压光刻胶；图案化第一高压光刻胶，以形成第一晶体管区域之上的高压光刻胶和第二晶体管区域之上的多个高压残留光刻胶，使得暴露邻近多个高压残留光刻胶的衬底的多个高压注入区；以第一高能量执行高压LDD注入，以将第一高压掺杂物注入到多个高压注入区中，从而形成邻近多个高压残留光刻胶的多个高压浅阱；以及以第二高能量执行高压口袋注入，以将第二高压掺杂物注入到多个高压注入区中，从而形成邻近多个高压残留光刻胶的多个高压口袋注入区。According to another aspect of the present invention, there is provided a semiconductor manufacturing method, comprising: forming a first high voltage photoresist over a first transistor region of a substrate and a second transistor region of a substrate; patterning the first high voltage photoresist resist to form a high voltage photoresist over the first transistor region and a plurality of high voltage residual photoresist over the second transistor region such that multiple high voltage implants of the substrate adjacent to the plurality of high voltage residual photoresist are exposed region; performing a high voltage LDD implant with a first high energy to implant a first high voltage dopant into a plurality of high voltage implanted regions, thereby forming a plurality of high voltage shallow wells adjacent to a plurality of high voltage residual photoresist; and with a second A high voltage pocket implant is performed at high energy to implant a second high voltage dopant into the plurality of high voltage implant regions, thereby forming a plurality of high voltage pocket implant regions adjacent to the plurality of high voltage residual photoresist.

优选地，该方法包括：形成第一晶体管区域中的多个第一栅极结构和第二晶体管区域中的多个第二栅极结构；在多个第一栅极结构和多个第二栅极结构之上形成第一低压光刻胶；图案化第一低压光刻胶，以在第二晶体管区域之上和多个第二栅极结构之上形成低压光刻胶，使得暴露多个第一栅极结构和邻近多个第一栅极结构的衬底的多个低压注入区；以第一低能量执行低压LDD注入，以将第一低压掺杂物注入到多个低压注入区中，从而形成邻近多个第一栅极结构的多个低压浅阱；以及以第二低能量执行低压口袋注入，以将第二低压掺杂物注入到多个低压注入区中，从而形成邻近多个第一栅极结构的多个低压口袋注入区。Preferably, the method includes: forming a plurality of first gate structures in the first transistor region and a plurality of second gate structures in the second transistor region; Forming a first low voltage photoresist over the electrode structure; patterning the first low voltage photoresist to form a low voltage photoresist over the second transistor region and over the plurality of second gate structures, so that the plurality of first gate structures are exposed a gate structure and a plurality of low voltage implanted regions adjacent to the substrate of the plurality of first gate structures; performing a low voltage LDD implant with a first low energy to implant a first low voltage dopant into the plurality of low voltage implanted regions, thereby forming a plurality of low voltage shallow wells adjacent to the plurality of first gate structures; A plurality of low voltage pocket implant regions of the first gate structure.

优选地，该方法包括：在衬底之上形成第一层栅极介电材料；从衬底的第一晶体管区域去除第一层栅极介电材料，使得高压栅极电介质的第一部分留在衬底的第二晶体管区域之上；在衬底之上并且在高压栅极电介质的第一部分之上形成第二层栅极介电材料，使得低压栅极电介质留在衬底的第一晶体管区域之上，并且高压栅极电介质留在衬底的第二晶体管区域之上，其中，高压栅极电介质包括第一部分和来自第二层栅极介电材料的第二部分；在低压栅极电介质之上和高压栅极电介质之上形成一层栅电极材料；以及图案化栅电极材料层、低压栅极电介质和高压栅极电介质，以同时形成多个第一栅极结构和多个第二栅极结构。Preferably, the method comprises: forming a first layer of gate dielectric material over the substrate; removing the first layer of gate dielectric material from the first transistor region of the substrate such that a first portion of the high voltage gate dielectric remains over the second transistor region of the substrate; forming a second layer of gate dielectric material over the substrate and over the first portion of the high voltage gate dielectric such that the low voltage gate dielectric remains in the first transistor region of the substrate and a high voltage gate dielectric is left over the second transistor region of the substrate, wherein the high voltage gate dielectric includes a first portion and a second portion from a second layer of gate dielectric material; between the low voltage gate dielectric forming a layer of gate electrode material on and over the high voltage gate dielectric; and patterning the layer of gate electrode material, low voltage gate dielectric, and high voltage gate dielectric to simultaneously form a plurality of first gate structures and a plurality of second gates structure.

优选地，该方法包括：在多个第一栅极结构、多个第二栅极结构和衬底之上形成侧壁材料层；以及图案化侧壁材料层，以同时形成邻近多个第一栅极结构的多个第一侧壁隔离物和邻近多个第二栅极结构的多个第二侧壁隔离物。Preferably, the method includes: forming a sidewall material layer over the plurality of first gate structures, the plurality of second gate structures and the substrate; and patterning the sidewall material layer to simultaneously form adjacent to the plurality of first gate structures. A plurality of first sidewall spacers of the gate structure and a plurality of second sidewall spacers adjacent to the plurality of second gate structures.

优选地，执行低压口袋注入包括：通过所选额定电压，注入在器件制造中使用的剂量。Preferably, performing the low voltage pocket implant comprises: injecting a dose used in device fabrication via a selected nominal voltage.

优选地，多个低压口袋注入区与多个高压口袋注入区的类型不同。Preferably, the plurality of low pressure pocket injection regions is of a different type than the plurality of high pressure pocket injection regions.

优选地，执行高压LDD注入包括：注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种；和/或执行高压口袋注入包括：注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。Preferably, performing high-voltage LDD implantation includes: implanting at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon; and/or performing high-voltage pocket implantation includes: implanting boron, phosphorus, arsenic, antimony , boron, boron fluoride, nitrogen or carbon.

优选地，执行高压LDD注入包括：以基本垂直于衬底的表面的角度注入第一高压掺杂物；和/或执行高压口袋注入包括：以基本垂直于衬底的表面的角度注入第二高压掺杂物。Preferably, performing the high-voltage LDD implantation includes: implanting a first high-voltage dopant at an angle substantially perpendicular to the surface of the substrate; and/or performing the high-voltage pocket implantation includes: implanting a second high-voltage dopant at an angle substantially perpendicular to the surface of the substrate adulterant.

根据本发明的又一方面，提供了一种注入掺杂物的方法，包括：在栅极结构之上沉积光刻胶，栅极结构位于衬底之上；图案化光刻胶，使得光刻胶在栅极结构的部分顶面而不是所有顶面之上，使得光刻胶的光刻胶宽度小于栅极结构的栅极结构宽度；以及在光刻胶在栅极结构之上时，将第一掺杂物注入到衬底中，以邻近栅极结构在衬底中形成第一掺杂区。According to yet another aspect of the present invention, there is provided a method for implanting dopants, comprising: depositing a photoresist over a gate structure, the gate structure being located on a substrate; patterning the photoresist such that the photolithography The glue is on some but not all of the top surfaces of the gate structures so that the photoresist has a photoresist width smaller than the gate structure width of the gate structures; and when the photoresist is on top of the gate structures, the The first dopant is implanted into the substrate to form a first doped region in the substrate adjacent to the gate structure.

优选地，该方法包括：在光刻胶在栅极结构之上时，将第二掺杂物注入到衬底中，以邻近栅极结构在衬底中形成第二掺杂区。Preferably, the method comprises: implanting a second dopant into the substrate while the photoresist is over the gate structure to form a second doped region in the substrate adjacent to the gate structure.

优选地，注入第一掺杂物包括：注入磷、砷、硼、氮或碳中的至少一种；和/或注入第二掺杂物包括：注入磷、砷、硼、氮或碳中的至少一种。Preferably, implanting the first dopant includes: implanting at least one of phosphorus, arsenic, boron, nitrogen or carbon; and/or implanting the second dopant includes: implanting phosphorus, arsenic, boron, nitrogen or carbon at least one.

优选地，注入第一掺杂物包括：以基本垂直于衬底的顶面的角度注入第一掺杂物；和/或注入第一掺杂物包括：以基本不垂直于衬底的顶面的角度注入第一掺杂物。Preferably, implanting the first dopant includes: implanting the first dopant at an angle substantially perpendicular to the top surface of the substrate; and/or implanting the first dopant includes: implanting the first dopant at an angle substantially not perpendicular to the top surface of the substrate The first dopant is implanted at an angle of .

附图说明Description of drawings

当阅读附图时，通过以下详细说明最好地理解本发明的多个方面。注意，根据工业中的标准实践，多种部件不按比例绘制。实际上，为了论述的清楚起见，多种部件的尺寸可以任意地增大或减小。Aspects of the invention are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

图1是示出根据一些实施例的半导体制造方法的流程图。FIG. 1 is a flowchart illustrating a semiconductor manufacturing method according to some embodiments.

图2是示出根据一些实施例的半导体制造方法的流程图。FIG. 2 is a flowchart illustrating a semiconductor manufacturing method according to some embodiments.

图3是根据一些实施例的半导体布置的图解。Figure 3 is an illustration of a semiconductor arrangement according to some embodiments.

图4是根据一些实施例的半导体布置的图解。Figure 4 is an illustration of a semiconductor arrangement according to some embodiments.

图5是根据一些实施例的半导体布置的图解。Figure 5 is an illustration of a semiconductor arrangement according to some embodiments.

图6是根据一些实施例的半导体布置的图解。Figure 6 is an illustration of a semiconductor arrangement according to some embodiments.

图7是根据一些实施例的半导体布置的图解。Figure 7 is an illustration of a semiconductor arrangement according to some embodiments.

图8是根据一些实施例的半导体布置的图解。Figure 8 is an illustration of a semiconductor arrangement according to some embodiments.

图9是根据一些实施例的半导体布置的图解。Figure 9 is an illustration of a semiconductor arrangement according to some embodiments.

图10是根据一些实施例的半导体布置的图解。Figure 10 is an illustration of a semiconductor arrangement according to some embodiments.

图11是根据一些实施例的半导体布置的图解。Figure 11 is an illustration of a semiconductor arrangement according to some embodiments.

图12是根据一些实施例的半导体布置的图解。Figure 12 is an illustration of a semiconductor arrangement according to some embodiments.

图13是根据一些实施例的半导体布置的图解。Figure 13 is an illustration of a semiconductor arrangement according to some embodiments.

图14是根据一些实施例的半导体布置的图解。Figure 14 is an illustration of a semiconductor arrangement according to some embodiments.

图15是根据一些实施例的半导体布置的图解。Figure 15 is an illustration of a semiconductor arrangement according to some embodiments.

图16是根据一些实施例的半导体布置的图解。Figure 16 is an illustration of a semiconductor arrangement according to some embodiments.

图17是根据一些实施例的半导体布置的图解。Figure 17 is an illustration of a semiconductor arrangement according to some embodiments.

图18是根据一些实施例的半导体布置的图解。Figure 18 is an illustration of a semiconductor arrangement according to some embodiments.

图19是根据一些实施例的半导体布置的图解。Figure 19 is an illustration of a semiconductor arrangement according to some embodiments.

图20是根据一些实施例的半导体布置的图解。Figure 20 is an illustration of a semiconductor arrangement according to some embodiments.

图21是根据一些实施例的半导体布置的图解。Figure 21 is an illustration of a semiconductor arrangement according to some embodiments.

图22是根据一些实施例的半导体布置的图解。Figure 22 is an illustration of a semiconductor arrangement according to some embodiments.

图23是根据一些实施例的半导体布置的图解。Figure 23 is an illustration of a semiconductor arrangement according to some embodiments.

图24是根据一些实施例的半导体布置的图解。Figure 24 is an illustration of a semiconductor arrangement according to some embodiments.

图25是根据一些实施例的半导体布置的图解。Figure 25 is an illustration of a semiconductor arrangement according to some embodiments.

图26是根据一些实施例的半导体布置的图解。Figure 26 is an illustration of a semiconductor arrangement according to some embodiments.

具体实施方式detailed description

以下公开提供用于实现所提供的主题的不同部件的多个不同实施例或实例。以下描述组件和布置的特定实例，以简化本公开。当然，这些仅是实例并且不用于限制。例如，以下说明书中的第一特征在第二部件之上或上形成可以包括第一和第二部件直接接触的实施例，并且还可以包括可以在第一和第二部件之间形成附加部件，使得第一和第二部件可以不直接接触的实施例。另外，本公开可以在多个实例中可以重复参考数字和/或字母。该重复用于简单和清楚的目的，并且其本身不指示所论述的多个实施例和/或结构之间的关系。The following disclosure provides a number of different embodiments, or examples, of different components for implementing the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the description below, a first feature formed on or over a second component may include embodiments where the first and second components are in direct contact, and may also include that an additional component may be formed between the first and second components, An embodiment such that the first and second components may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or structures discussed.

而且，诸如“在...之下”、“之下”、“下面”、“之上”、“上面”等的空间相对术语可以在此被用于容易说明，以描述如图中所示的一个元件或部件与另一个元件或部件的关系。除了在图中所示的定向之外，空间相对术语旨在包括正在使用或操作的器件的不同定向。装置可以另外被定向(旋转90度或者为其他定向)，并且在此使用的空间相对描述符被另外相应地解释。Also, spatially relative terms such as "under", "under", "under", "over", "above", etc. may be used herein for ease of explanation, to describe The relationship of one element or part to another element or part. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein otherwise interpreted accordingly.

在此提供用于形成半导体布置的一个或多个技术和由此形成的结构。One or more techniques for forming semiconductor arrangements and structures formed thereby are provided herein.

图1示出根据一些实施例的半导体制造的第一方法100，并且在图3至图15中示出在多个制造阶段的由此形成的一个或多个结构。根据一些实施例，诸如在图15中所示，半导体布置300包括位于第一晶体管区域321a中的多个第一晶体管332a和位于衬底302之上的第二晶体管区域321b中的多个第二晶体管332b，多个第一晶体管具有第一工作电压且邻近具有大于第一工作电压的第二工作电压的多个第二晶体管332b。将想到，在此描述的不同区域中形成其多个晶体管和部件、元件等，并且为了简单起见，仅在图中示出其单个实例。线399示出第一晶体管332a通常与第二晶体管332b电隔离或去耦。在一些实施例中，多个第一晶体管332a包括多个第一栅极结构330a和邻近多个第一栅极结构330a的多个第一侧壁隔离物309a。在一些实施例中，多个第一源极漏极区344a在邻近多个第一栅极结构330a的衬底302中。在一些实施例中，多个低压口袋注入区328a邻近多个第一源极漏极区344a，使得多个低压口袋注入区328a在多个第一栅极结构330a下面比多个第一源极漏极区344a延伸得更远。在一些实施例中，多个第二晶体管332b包括多个第二栅极结构330b和邻近多个第二栅极结构330b的多个第二侧壁隔离物309b。在一些实施例中，多个第二源极漏极区344b在邻近多个第二栅极结构330b的衬底302中。在一些实施例中，多个高压口袋注入区328b邻近多个第二源极漏极区344b，使得多个高压口袋注入区328b在多个第二栅极结构330b下面比多个第二源极漏极区344b延伸得更远。在一个实施例中，多个第一晶体管332a包括低压器件或中压器件中的至少一个。在一些实施例中，多个第二晶体管332b包括中压器件或高压器件中的至少一个。在一些实施例中，多个第一晶体管332a是不同类型，诸如，不同于多个第二晶体管332b的器件电压类型。在一些实施例中，低压器件具有小于约1.5V的工作电压。在一些实施例中，中压器件具有在约3.3V至约10V之间的工作电压。在一些实施例中，高压器件具有在约30V以上的工作电压。在一些实施例中，根据第一方法100形成的半导体布置300具有比不根据第一方法100形成的布置更薄的栅电极。在一个实施例中，多个第一晶体管332a和多个第二晶体管332b被形成为单个CMOS制造处理的一部分而不需要附加掩模。FIG. 1 illustrates a first method 100 of semiconductor fabrication in accordance with some embodiments, and one or more structures formed thereby are shown at various stages of fabrication in FIGS. 3-15 . According to some embodiments, such as shown in FIG. Transistor 332b, a plurality of first transistors having a first operating voltage and adjacent to a plurality of second transistors 332b having a second operating voltage greater than the first operating voltage. It will be appreciated that multiple transistors and components, elements, etc. thereof are formed in the different regions described herein, and for simplicity only a single instance thereof is shown in the figures. Line 399 shows that first transistor 332a is generally electrically isolated or decoupled from second transistor 332b. In some embodiments, the plurality of first transistors 332a includes a plurality of first gate structures 330a and a plurality of first sidewall spacers 309a adjacent to the plurality of first gate structures 330a. In some embodiments, the plurality of first source-drain regions 344a are in the substrate 302 adjacent to the plurality of first gate structures 330a. In some embodiments, the plurality of low-voltage pocket implant regions 328a are adjacent to the plurality of first source-drain regions 344a, such that the plurality of low-voltage pocket implant regions 328a are lower than the plurality of first source regions under the plurality of first gate structures 330a. Drain region 344a extends further. In some embodiments, the plurality of second transistors 332b includes a plurality of second gate structures 330b and a plurality of second sidewall spacers 309b adjacent to the plurality of second gate structures 330b. In some embodiments, the plurality of second source-drain regions 344b are in the substrate 302 adjacent to the plurality of second gate structures 330b. In some embodiments, the plurality of high voltage pocket implant regions 328b are adjacent to the plurality of second source drain regions 344b such that the plurality of high voltage pocket implant regions 328b are under the plurality of second gate structures 330b than the plurality of second source electrodes Drain region 344b extends further. In one embodiment, the plurality of first transistors 332a includes at least one of a low voltage device or a medium voltage device. In some embodiments, the plurality of second transistors 332b includes at least one of a medium voltage device or a high voltage device. In some embodiments, the plurality of first transistors 332a are of a different type, such as a different device voltage type than the plurality of second transistors 332b. In some embodiments, the low voltage device has an operating voltage of less than about 1.5V. In some embodiments, the medium voltage device has an operating voltage between about 3.3V and about 10V. In some embodiments, the high voltage device has an operating voltage above about 30V. In some embodiments, the semiconductor arrangement 300 formed according to the first method 100 has a thinner gate electrode than an arrangement not formed according to the first method 100 . In one embodiment, the plurality of first transistors 332a and the plurality of second transistors 332b are formed as part of a single CMOS fabrication process without the need for additional masks.

根据一些实施例，在方法100的102中，在衬底302的第一晶体管区域321a之上形成多个第一栅极结构330a，并且在衬底302的第二晶体管区域321b之上形成多个第二栅极结构330b，如图7所示。转到图3，在图7之前，根据一些实施例在衬底302的顶面302a之上形成第一层栅极介电材料304。在一些实施例中，衬底302包括硅或锗中的至少一种。根据一些实施例，衬底302包括外延层、绝缘体上硅(SOI)结构、晶圆、或由晶圆形成的管芯中的至少一个。在一些实施例中，第一层栅极介电材料304包括氧化物或氮化物中的至少一种。在一些实施例中，第一层栅极介电材料304具有约至约之间的第一厚度303a。在一些实施例中，诸如通过蚀刻，从第一晶体管区域321a之上的衬底302的顶面302a去除第一层栅极介电材料304，使得高压栅极电介质304b的第一部分304b1留在衬底302的第二晶体管区域321b之上，如图4所示。在一些实施例中，在衬底302的顶面302a之上并且在高压栅极电介质304b的第一部分304b1之上形成第二层栅极介电材料305，使得低压栅极电介质304a留在衬底302的第一晶体管区域231a之上，并且高压栅极电介质304b留在衬底302的第二晶体管区域321b之上，如图5所示。在一些实施例中，第二层栅极介电材料305包括氧化物或氮化物中的至少一种。在一些实施例中，第二层栅极介电材料305具有约至约之间的第二厚度303b，使得低压栅极电介质304a具有第二厚度303b。在一些实施例中，高压栅极电介质304b包括第一部分304b1和来自第二层栅极介电材料305的第二部分304b2。在一些实施例中，高压栅极电介质304b具有约至约之间的第三厚度303c，其中，第三厚度303c通常等于第一厚度303a和第二厚度303b的总和。在一些实施例中，在低压栅极电介质304a和高压栅极电介质304b之上形成一层栅电极材料310，如图6所示。在一些实施例中，该层栅电极材料310具有基本均匀的厚度。在一些实施例中，该层栅电极材料310包括多晶硅或金属中的至少一种。在一些实施例中，该层栅电极材料310、低压栅极电介质304a和高压栅极电介质304b被图案化，以同时形成第一晶体管区域321a中的多个第一栅极结构330a和第二晶体管区域321b中的多个第二栅极结构330b，如图7所示。在一些实施例中，多个第一栅极结构330a的相应栅极结构具有第一宽度340a，并且多个第二栅极结构330b的相应栅极结构具有第二宽度340b。在一些实施例中，第二宽度340b大于第一宽度340a。在一些实施例中，多个低压注入区311a邻近第一晶体管区域321a中的多个第一栅极结构330a。在一些实施例中，多个高压注入区311b邻近第二晶体管区域321b中的多个第二栅极结构330b。According to some embodiments, at 102 of the method 100, a plurality of first gate structures 330a are formed over the first transistor region 321a of the substrate 302, and a plurality of gate structures 330a are formed over the second transistor region 321b of the substrate 302 The second gate structure 330b is as shown in FIG. 7 . Turning to FIG. 3 , prior to FIG. 7 , a first layer of gate dielectric material 304 is formed over top surface 302 a of substrate 302 according to some embodiments. In some embodiments, substrate 302 includes at least one of silicon or germanium. According to some embodiments, the substrate 302 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from the wafer. In some embodiments, the first layer of gate dielectric material 304 includes at least one of oxide or nitride. In some embodiments, the first layer of gate dielectric material 304 has about to about Between the first thickness 303a. In some embodiments, the first layer of gate dielectric material 304 is removed from the top surface 302a of the substrate 302 above the first transistor region 321a, such as by etching, such that the first portion 304b1 of the high voltage gate dielectric 304b remains on the substrate. Above the second transistor region 321b of the bottom 302, as shown in FIG. 4 . In some embodiments, a second layer of gate dielectric material 305 is formed over the top surface 302a of the substrate 302 and over the first portion 304b1 of the high voltage gate dielectric 304b such that the low voltage gate dielectric 304a remains on the substrate. 302 over the first transistor region 231a, and a high voltage gate dielectric 304b remains over the second transistor region 321b of the substrate 302, as shown in FIG. In some embodiments, the second gate dielectric material 305 includes at least one of oxide or nitride. In some embodiments, the second layer of gate dielectric material 305 has about to about The second thickness 303b between them makes the low voltage gate dielectric 304a have the second thickness 303b. In some embodiments, the high voltage gate dielectric 304b includes a first portion 304b1 and a second portion 304b2 from the second layer of gate dielectric material 305 . In some embodiments, the high voltage gate dielectric 304b has about to about Between the third thickness 303c, wherein the third thickness 303c is generally equal to the sum of the first thickness 303a and the second thickness 303b. In some embodiments, a layer of gate electrode material 310 is formed over the low voltage gate dielectric 304a and the high voltage gate dielectric 304b, as shown in FIG. 6 . In some embodiments, the layer of gate electrode material 310 has a substantially uniform thickness. In some embodiments, the layer of gate electrode material 310 includes at least one of polysilicon or metal. In some embodiments, the layer of gate electrode material 310, the low voltage gate dielectric 304a, and the high voltage gate dielectric 304b are patterned to simultaneously form a plurality of first gate structures 330a and second transistors in the first transistor region 321a A plurality of second gate structures 330b in the region 321b, as shown in FIG. 7 . In some embodiments, a corresponding gate structure of the plurality of first gate structures 330a has a first width 340a, and a corresponding gate structure of the plurality of second gate structures 330b has a second width 340b. In some embodiments, the second width 340b is greater than the first width 340a. In some embodiments, the plurality of low voltage injection regions 311a are adjacent to the plurality of first gate structures 330a in the first transistor region 321a. In some embodiments, the plurality of high voltage injection regions 311b are adjacent to the plurality of second gate structures 330b in the second transistor region 321b.

根据一些实施例，在方法100的104中，在多个第二栅极结构330b和第二晶体管区域321b之上形成低压光刻胶308a，由此暴露多个第一栅极结构330a和多个低压注入区311a，如图9所示。转到图8，根据一些实施例，在图9之前，诸如通过在多个第一栅极结构330a、多个第二栅极结构330b以及衬底302之上进行沉积而形成第一低压光刻胶308。在一些实施例中，第一低压光刻胶308被图案化，以形成低压光刻胶308a，如图9所示。According to some embodiments, at 104 of the method 100, a low voltage photoresist 308a is formed over the plurality of second gate structures 330b and the second transistor regions 321b, thereby exposing the plurality of first gate structures 330a and the plurality of The low-pressure injection region 311a is shown in FIG. 9 . Turning to FIG. 8 , prior to FIG. 9 , according to some embodiments, a first low-voltage lithographic pattern is formed, such as by deposition over the plurality of first gate structures 330a, the plurality of second gate structures 330b, and the substrate 302. Glue 308. In some embodiments, the first low-voltage photoresist 308 is patterned to form a low-voltage photoresist 308a, as shown in FIG. 9 .

根据一些实施例，在方法100的106中，执行低压LDD注入，以将第一低压掺杂物318a注入到多个低压注入区311a中，以形成多个低压浅阱314a，如图10所示。在一些实施例中，第一低压掺杂物318a包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第一低压掺杂物318a。在一些实施例中，对半导体布置300执行第一退火，使得多个低压浅阱314a在多个第一栅极结构330a下面迁移。在一些实施例中，低压光刻胶308a防止第一低压掺杂物318a进入低压光刻胶308a下面的区域中。在一些实施例中，通过所选额定电压，以在器件制造中使用的第一角度注入第一低压掺杂物318a。According to some embodiments, in step 106 of the method 100, a low-voltage LDD implant is performed to implant a first low-voltage dopant 318a into a plurality of low-voltage implanted regions 311a to form a plurality of low-voltage shallow wells 314a, as shown in FIG. 10 . In some embodiments, the first low voltage dopant 318a includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the first low voltage dopant 318a is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, a first anneal is performed on the semiconductor arrangement 300 such that the plurality of low voltage shallow wells 314a migrate under the plurality of first gate structures 330a. In some embodiments, the low voltage photoresist 308a prevents the first low voltage dopant 318a from entering into the region below the low voltage photoresist 308a. In some embodiments, the first low voltage dopant 318a is implanted at a first angle used in device fabrication with a selected nominal voltage.

根据一些实施例，在方法100的108中，执行低压口袋注入，以将第二低压掺杂物318b注入到多个低压注入区311a中，以形成多个低压口袋注入区328a，如图11所示。在一些实施例中，第二低压掺杂物318b包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第二低压掺杂物318b。在一些实施例中，低压光刻胶308a防止第二低压掺杂物318b进入低压光刻胶308a下面的区域中。在一些实施例中，通过所选额定电压，以在器件制造中使用的第二角度注入第二低压掺杂物。在一些实施例中，多个低压口袋注入区328a至少部分地在多个第一栅极结构330a下面。在一些实施例中，对半导体布置300执行第二退火，使得多个低压浅阱314a和多个低压口袋注入区328a在多个第一栅极结构330a下面迁移。在一些实施例中，诸如通过酸洗或蚀刻中的至少一个，从多个第二栅极结构330b和第二晶体管区域321b去除低压光刻胶308a，如图12所示。According to some embodiments, in 108 of the method 100, a low-voltage pocket implant is performed to implant a second low-voltage dopant 318b into the plurality of low-voltage implant regions 311a to form a plurality of low-voltage pocket implant regions 328a, as shown in FIG. 11 Show. In some embodiments, the second low voltage dopant 318b includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the second low voltage dopant 318b is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, the low voltage photoresist 308a prevents the second low voltage dopant 318b from entering the region below the low voltage photoresist 308a. In some embodiments, with the selected nominal voltage, the second low voltage dopant is implanted at a second angle used in device fabrication. In some embodiments, the plurality of low voltage pocket implant regions 328a at least partially underlies the plurality of first gate structures 330a. In some embodiments, the second anneal is performed on the semiconductor arrangement 300 such that the plurality of low voltage shallow wells 314 a and the plurality of low voltage pocket implant regions 328 a migrate under the plurality of first gate structures 330 a. In some embodiments, the low voltage photoresist 308a is removed from the plurality of second gate structures 330b and the second transistor region 321b, such as by at least one of pickling or etching, as shown in FIG. 12 .

根据一些实施例，在方法100的110中，在多个第一栅极结构330a之上、在衬底的第一晶体管区域321a之上形成高压光刻胶331a，并且在多个第二栅极结构330b之上形成多个高压残留光刻胶331b，从而暴露衬底302的多个高压注入区311b和多个第二栅极结构330b的多个第二顶部326，如图13所示。在一些实施例中，通过诸如通过在多个第一栅极结构330a、多个第二栅极结构330b以及衬底302之上沉积形成第一高压光刻胶(未示出)并且诸如通过酸洗或蚀刻中的至少一个图案化第一高压光刻胶，形成高压光刻胶331a和多个高压残留光刻胶331b。在一些实施例中，多个高压残留光刻胶331b在多个第二栅极顶部326之间，其中，多个高压残留光刻胶331b与第一栅极边缘329a相距第一距离324a，并且与第二栅极边缘329b相距第二距离324b。在一些实施例中，第一距离324a和第二距离324b是不同距离。在一些实施例中，第一距离324a等于第二距离324b。在一些实施例中，第一距离324a在约30nm至约90nm之间，或者第二距离324b在约30nm至约90nm之间。According to some embodiments, at 110 of the method 100, a high voltage photoresist 331a is formed over the plurality of first gate structures 330a, over the first transistor region 321a of the substrate, and over the plurality of second gate structures 330a. A plurality of high voltage residual photoresist 331b is formed on the structure 330b, thereby exposing the plurality of high voltage injection regions 311b of the substrate 302 and the plurality of second tops 326 of the plurality of second gate structures 330b, as shown in FIG. 13 . In some embodiments, a first high voltage photoresist (not shown) is formed such as by depositing over the plurality of first gate structures 330a, the plurality of second gate structures 330b and the substrate 302 and such as by acid At least one of washing or etching patterns the first high voltage photoresist to form a high voltage photoresist 331a and a plurality of high voltage residual photoresists 331b. In some embodiments, the plurality of high voltage residual photoresist 331b is between the plurality of second gate tops 326, wherein the plurality of high voltage residual photoresist 331b is a first distance 324a from the first gate edge 329a, and The second distance 324b is from the second gate edge 329b. In some embodiments, the first distance 324a and the second distance 324b are different distances. In some embodiments, the first distance 324a is equal to the second distance 324b. In some embodiments, the first distance 324a is between about 30 nm and about 90 nm, or the second distance 324b is between about 30 nm and about 90 nm.

根据一些实施例，在方法100的112中，执行高压LDD注入，以将第一高压掺杂物318c注入到多个高压注入区311b中，以形成多个高压浅阱314b，如图13中所示。在一些实施例中，第一高压掺杂物318c包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第一高压掺杂物318c。在一些实施例中，对半导体布置300执行第三退火，使得多个高压浅阱314b在多个第二栅极结构330b下面迁移。在一些实施例中，高压光刻胶331a防止第一高压掺杂物318c进入高压光刻胶331a下面的区域中。在一些实施例中，多个高压残留光刻胶331b类似地保护多个第二栅极结构不受第一高压掺杂物318c影响。在一些实施例中，通过所选额定电压，以在器件制造中使用的第三角度注入第一高压掺杂物318c。According to some embodiments, in 112 of the method 100, a high voltage LDD implant is performed to implant a first high voltage dopant 318c into a plurality of high voltage implant regions 311b to form a plurality of high voltage shallow wells 314b, as shown in FIG. 13 Show. In some embodiments, the first high voltage dopant 318c includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the first high voltage dopant 318c is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, a third anneal is performed on the semiconductor arrangement 300 such that the plurality of high voltage shallow wells 314b migrate under the plurality of second gate structures 330b. In some embodiments, the high voltage photoresist 331a prevents the first high voltage dopant 318c from entering the region below the high voltage photoresist 331a. In some embodiments, the plurality of high voltage residual photoresists 331b similarly protect the plurality of second gate structures from the first high voltage dopant 318c. In some embodiments, the first high voltage dopant 318c is implanted at a third angle used in device fabrication with a selected nominal voltage.

根据一些实施例，在方法100的114中，执行高压口袋注入，以将第二高压掺杂物318d注入到多个高压注入区311b中，以形成多个高压口袋注入区318b，如图14所示。在一些实施例中，第二高压掺杂物318d包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第二高压掺杂物318d。在一些实施例中，高压光刻胶331a防止第二高压掺杂物318d进入高压光刻胶331a下面的区域中。在一些实施例中，多个高压残留光刻胶331b类似地保护多个第二栅极结构330b不受第二高压掺杂物318d影响。在一些实施例中，通过所选额定电压，以在器件制造中使用的第四角度注入第二高压掺杂物318d。在一些实施例中，多个高压口袋注入区328b至少部分地在多个第二栅极结构330b下面。在一些实施例中，对半导体布置300执行第四退火，使得多个高压浅阱314b和多个高压口袋注入区328b在多个第二栅极结构330b下面迁移。在一些实施例中，诸如通过酸洗或蚀刻中的至少一种，从多个第二栅极结构330b、多个第一栅极结构330a和第一晶体管区域321a去除高压光刻胶331a和多个高压残留光刻胶331b，如图15所示。According to some embodiments, in 114 of the method 100, a high voltage pocket implant is performed to implant a second high voltage dopant 318d into the plurality of high voltage implant regions 311b to form a plurality of high voltage pocket implant regions 318b, as shown in FIG. 14 Show. In some embodiments, the second high voltage dopant 318d includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the second high voltage dopant 318d is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, the high voltage photoresist 331a prevents the second high voltage dopant 318d from entering into the region below the high voltage photoresist 331a. In some embodiments, the plurality of high voltage residual photoresists 331b similarly protect the plurality of second gate structures 330b from the second high voltage dopant 318d. In some embodiments, the second high voltage dopant 318d is implanted at a fourth angle used in device fabrication with the selected nominal voltage. In some embodiments, the plurality of high voltage pocket implant regions 328b at least partially underlies the plurality of second gate structures 330b. In some embodiments, a fourth anneal is performed on the semiconductor arrangement 300 such that the plurality of high voltage shallow wells 314b and the plurality of high voltage pocket implant regions 328b migrate under the plurality of second gate structures 330b. In some embodiments, the high voltage photoresist 331a and the plurality of second gate structures 330b, the plurality of first gate structures 330a, and the first transistor region 321a are removed, such as by at least one of pickling or etching. a high voltage residual photoresist 331b, as shown in FIG. 15 .

在一些实施例中，在多个第一栅极结构330a、多个第二栅极结构330b和衬底302之上形成一层侧壁材料(未示出)。在一些实施例中，该层侧壁材料包括氮化物。在一些实施例中，该层侧壁材料被图案化，以同时形成邻近多个第一栅极结构330a的多个第一侧壁隔离物309a以及邻近多个第二栅极结构330b的多个第二侧壁隔离物309b。In some embodiments, a layer of sidewall material (not shown) is formed over the plurality of first gate structures 330 a , the plurality of second gate structures 330 b and the substrate 302 . In some embodiments, the layer of sidewall material includes nitride. In some embodiments, the layer of sidewall material is patterned to simultaneously form the plurality of first sidewall spacers 309a adjacent to the plurality of first gate structures 330a and the plurality of adjacent second gate structures 330b. The second sidewall spacer 309b.

在一些实施例中，根据一些实施例，与相应图案化的光刻胶(未示出)关联地执行低压深阱注入，以将第三低压掺杂物(未示出)注入到多个低压浅阱314a中，以形成第一源极漏极区344a，如图15所示。在一些实施例中，第三低压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第三低压掺杂物。在一些实施例中，根据一些实施例，与相应图案化的光刻胶(未示出)关联地执行高压深阱注入，以将第三高压掺杂物(未示出)注入到多个高压浅阱314b中，以形成第二源极漏极区344b，如图15所示。在一些实施例中，第三高压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第三高压掺杂物。In some embodiments, a low-voltage deep well implant is performed in association with a correspondingly patterned photoresist (not shown) to implant a third low-voltage dopant (not shown) into the plurality of low-voltage In the shallow well 314a, a first source-drain region 344a is formed, as shown in FIG. 15 . In some embodiments, the third low voltage dopant includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the third low voltage dopant is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, a high voltage deep well implant is performed in association with a correspondingly patterned photoresist (not shown) to implant a third high voltage dopant (not shown) into the plurality of high voltage In the shallow well 314b, a second source-drain region 344b is formed, as shown in FIG. 15 . In some embodiments, the third high voltage dopant includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the third high voltage dopant is implanted at a dose and energy used in device fabrication with a selected nominal voltage.

假定在一些实施例中，第一距离324a不等于第二距离324b，诸如由于相对于多个第二栅极结构330b对准或形成多个高压残留光刻胶331b的不准确，多个高压浅阱314b、多个高压口袋注入区328b或多个第二源极漏极区344b中的至少一个关于相应的第二栅极结构330b不对称。根据一些实施例，第二栅极结构的一侧上的第二源极漏极区的尺寸不同于第二栅极结构的另一个侧上的第二源极漏极区的尺寸。根据一些实施例，与当第二晶体管被反相偏置时相比，当第二晶体管被正向偏置时，在第二栅极结构周围注入的掺杂物的这种不对称产生不同特征曲线。Assuming that in some embodiments, the first distance 324a is not equal to the second distance 324b, such as due to inaccuracies in aligning or forming the plurality of high voltage residual photoresist 331b relative to the plurality of second gate structures 330b, the plurality of high voltage shallow At least one of the well 314b, the plurality of high voltage pocket implant regions 328b or the plurality of second source drain regions 344b is asymmetric about the corresponding second gate structure 330b. According to some embodiments, the size of the second source-drain region on one side of the second gate structure is different from the size of the second source-drain region on the other side of the second gate structure. According to some embodiments, this asymmetry of implanted dopants around the second gate structure produces different characteristics when the second transistor is forward biased compared to when the second transistor is reverse biased. curve.

图2示出根据一些实施例的半导体制造的第二方法200，并且图16至26中示出在多个制造阶段处由此形成的一个或多个结构。根据一些实施例，诸如图26中所示，半导体布置400包括位于第一晶体管区域421a中的多个第一晶体管432a和位于衬底402之上的第二晶体管区域421b中的多个第二晶体管432b，所述多个第一晶体管具有第一工作电压且邻近具有大于第一工作电压的第二工作电压的多个第二晶体管432b。将想到，在此描述的不同区域中形成其多个晶体管和特征、元件等，并且为了简单起见，仅示出其单个实例。线499示出第一晶体管432a通常与第二晶体管432b电隔离或去耦。在一些实施例中，多个第一晶体管432a包括多个第一栅极结构430a和邻近多个第一栅极结构430a的多个第一侧壁隔离物409a。在一些实施例中，多个第一源极漏极区444a在邻近多个第一栅极结构430a的衬底402中。在一些实施例中，多个低压口袋注入区428a邻近多个第一源极漏极区444a，使得多个低压口袋注入区428a在多个第一栅极结构430a下面比多个第一源极漏极区444a延伸得更远。在一些实施例中，多个第二晶体管432b包括多个第二栅极结构430b和邻近多个第二栅极结构430b的多个第二侧壁隔离物409b。在一些实施例中，多个第二源极漏极区444b在邻近多个第二栅极结构430b的衬底402中。在一些实施例中，多个高压口袋注入区428b邻近多个第二源极漏极区444b，使得多个高压口袋注入区428b在多个第二栅极结构430b下面比多个第二源极漏极区444b延伸得更远。在一些实施例中，多个第一晶体管432a包括低压器件或中压器件中的至少一个。在一些实施例中，多个第二晶体管432b包括中压器件或高压器件中的至少一个。在一些实施例中，多个第一晶体管432a是不同类型的，诸如，不同于多个第二晶体管432b的器件电压类型。在一些实施例中，低压器件具有小于约1.5V的工作电压。在一些实施例中，中压器件具有在约3.3V至约10V之间的工作电压。在一些实施例中，高压器件具有约30V以上的工作电压。在一些实施例中，根据第二方法200形成的半导体布置400具有比不根据第二方法200形成的布置更薄的栅电极。在一些实施例中，多个第一晶体管432a和多个第二晶体管432b被形成为单个CMOS制造处理的一部分，而不需要附加掩模。FIG. 2 illustrates a second method 200 of semiconductor fabrication in accordance with some embodiments, and one or more structures thus formed at various stages of fabrication are illustrated in FIGS. 16-26 . According to some embodiments, such as shown in FIG. 26 , the semiconductor arrangement 400 includes a plurality of first transistors 432a located in a first transistor region 421a and a plurality of second transistors located in a second transistor region 421b above the substrate 402 432b, the plurality of first transistors have a first operating voltage and are adjacent to a plurality of second transistors 432b having a second operating voltage greater than the first operating voltage. It is contemplated that various transistors and features, elements, etc. thereof are formed in different regions described herein, and for simplicity only a single instance thereof is shown. Line 499 shows that first transistor 432a is generally electrically isolated or decoupled from second transistor 432b. In some embodiments, the plurality of first transistors 432a includes a plurality of first gate structures 430a and a plurality of first sidewall spacers 409a adjacent to the plurality of first gate structures 430a. In some embodiments, the plurality of first source-drain regions 444a are in the substrate 402 adjacent to the plurality of first gate structures 430a. In some embodiments, the plurality of low-voltage pocket implant regions 428a is adjacent to the plurality of first source-drain regions 444a, such that the plurality of low-voltage pocket implant regions 428a are lower than the plurality of first source regions under the plurality of first gate structures 430a. Drain region 444a extends further. In some embodiments, the plurality of second transistors 432b includes a plurality of second gate structures 430b and a plurality of second sidewall spacers 409b adjacent to the plurality of second gate structures 430b. In some embodiments, the plurality of second source-drain regions 444b are in the substrate 402 adjacent to the plurality of second gate structures 430b. In some embodiments, the plurality of high voltage pocket implant regions 428b are adjacent to the plurality of second source drain regions 444b such that the plurality of high voltage pocket implant regions 428b are under the plurality of second gate structures 430b than the plurality of second source electrodes Drain region 444b extends further. In some embodiments, the plurality of first transistors 432a includes at least one of a low voltage device or a medium voltage device. In some embodiments, the plurality of second transistors 432b includes at least one of a medium voltage device or a high voltage device. In some embodiments, the plurality of first transistors 432a are of a different type, such as a different device voltage type than the plurality of second transistors 432b. In some embodiments, the low voltage device has an operating voltage of less than about 1.5V. In some embodiments, the medium voltage device has an operating voltage between about 3.3V and about 10V. In some embodiments, the high voltage device has an operating voltage above about 30V. In some embodiments, the semiconductor arrangement 400 formed according to the second method 200 has a thinner gate electrode than an arrangement not formed according to the second method 200 . In some embodiments, the plurality of first transistors 432a and the plurality of second transistors 432b are formed as part of a single CMOS fabrication process without the need for additional masks.

根据一些实施例，在方法200的202中，在衬底402的第一晶体管区域421a和衬底402的第二晶体管区域421b之上形成第一高压光刻胶431，如图16中所示。在一些实施例中，衬底402包括硅或锗中的至少一种。根据一些实施例，衬底402包括外延层、绝缘体上硅(SOI)结构、晶圆、或由晶圆形成的管芯中的至少一种。According to some embodiments, in 202 of method 200 , a first high voltage photoresist 431 is formed over the first transistor region 421 a of the substrate 402 and the second transistor region 421 b of the substrate 402 , as shown in FIG. 16 . In some embodiments, substrate 402 includes at least one of silicon or germanium. According to some embodiments, the substrate 402 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from the wafer.

根据一些实施例，在方法200的204中，图案化第一高压光刻胶431，以在第一晶体管区域421a之上形成高压光刻胶431a并且在第二晶体管区域421b之上形成多个高压残留光刻胶431b，从而暴露邻近多个高压残留光刻胶431b的衬底402的多个高压注入区411b，如图17中所示。在一些实施例中，多个高压残留光刻胶431b具有约350nm至约450nm之间的第一残留光刻胶宽度413。According to some embodiments, in 204 of method 200, the first high voltage photoresist 431 is patterned to form the high voltage photoresist 431a over the first transistor region 421a and to form a plurality of high voltage photoresists over the second transistor region 421b. The photoresist 431b is left, thereby exposing the plurality of high voltage implant regions 411b of the substrate 402 adjacent to the plurality of high voltage remaining photoresist 431b, as shown in FIG. 17 . In some embodiments, the plurality of high voltage residual photoresist 431b has a first residual photoresist width 413 between about 350 nm and about 450 nm.

根据一些实施例，在方法200的206中，执行高压LDD注入，以将第一高压掺杂物418a注入到多个高压注入区411b中，以形成多个高压浅阱414b，如图17所示。在一些实施例中，第一高压掺杂物418a包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第一高压掺杂物418a。在一些实施例中，对半导体布置400执行第一退火，使得多个高压浅阱414b在多个高压残留光刻胶431b下面迁移。在一些实施例中，高压光刻胶431a防止第一高压掺杂物418a进入高压光刻胶431a下面的衬底402的区域中。在一些实施例中，多个高压残留光刻胶431b类似地防止衬底402免受第一高压掺杂物418a影响。在一些实施例中，以入射到衬底402的表面402a的第一角度，注入第一高压掺杂物418a，其中，第一角度基本垂直于衬底402的表面402a。在一些实施例中，第一角度包括通过所选额定电压在器件制造中使用的角度。According to some embodiments, in step 206 of the method 200, a high voltage LDD implant is performed to implant a first high voltage dopant 418a into a plurality of high voltage implanted regions 411b to form a plurality of high voltage shallow wells 414b, as shown in FIG. 17 . In some embodiments, the first high voltage dopant 418a includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the first high voltage dopant 418a is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, the first anneal is performed on the semiconductor arrangement 400 such that the plurality of high voltage shallow wells 414b migrate under the plurality of high voltage residual photoresist 431b. In some embodiments, the high voltage photoresist 431a prevents the first high voltage dopant 418a from entering into regions of the substrate 402 below the high voltage photoresist 431a. In some embodiments, the plurality of high voltage residual photoresists 431b similarly protect the substrate 402 from the first high voltage dopant 418a. In some embodiments, the first high voltage dopant 418a is implanted at a first angle of incidence to the surface 402a of the substrate 402 , wherein the first angle is substantially normal to the surface 402a of the substrate 402 . In some embodiments, the first angle includes an angle used in device fabrication with a selected voltage rating.

根据一些实施例，在方法200的208中，执行高压口袋注入，以将第二高压掺杂物418b注入到多个高压注入区411b中，以形成多个高压口袋注入区428b，如图18所示。在一些实施例中，第二高压掺杂物418b包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第二高压掺杂物418b。在一些实施例中，高压光刻胶431a防止第二高压掺杂物418b进入高压光刻胶431a下面的衬底402的区域中。在一些实施例中，多个高压残留光刻胶431b类似地防止衬底402免受第二高压掺杂物418b影响。在一些实施例中，以入射到衬底402的表面402a的第二角度注入第二高压掺杂物418b，其中，第二角度基本垂直于衬底402的表面402a。在一些实施例中，第二角度包括通过所选额定电压在器件制造中使用的角度。在一些实施例中，多个高压口袋注入区428b至少部分地在多个高压残留光刻胶431b下面。在一些实施例中，对半导体布置400执行第二退火，使得多个高压浅阱414b和多个高压口袋注入区428b在多个高压残留光刻胶431b下面迁移。在一些实施例中，诸如通过酸洗或蚀刻中的至少一种，去除高压光刻胶431a和多个高压残留光刻胶431b，如图19所示。According to some embodiments, in 208 of the method 200, a high voltage pocket implant is performed to implant a second high voltage dopant 418b into the plurality of high voltage implant regions 411b to form a plurality of high voltage pocket implant regions 428b, as shown in FIG. 18 Show. In some embodiments, the second high voltage dopant 418b includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the second high voltage dopant 418b is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, the high voltage photoresist 431a prevents the second high voltage dopant 418b from entering into the region of the substrate 402 below the high voltage photoresist 431a. In some embodiments, the plurality of high voltage residual photoresist 431b similarly protects the substrate 402 from the second high voltage dopant 418b. In some embodiments, the second high voltage dopant 418b is implanted at a second angle of incidence to the surface 402a of the substrate 402 , wherein the second angle is substantially normal to the surface 402a of the substrate 402 . In some embodiments, the second angle includes the angle used in device fabrication with the selected voltage rating. In some embodiments, the plurality of high voltage pocket implant regions 428b at least partially underlies the plurality of high voltage residual photoresist 431b. In some embodiments, the second anneal is performed on the semiconductor arrangement 400 such that the plurality of high voltage shallow wells 414b and the plurality of high voltage pocket implant regions 428b migrate under the plurality of high voltage residual photoresist 431b. In some embodiments, the high voltage photoresist 431a and the plurality of high voltage residual photoresists 431b are removed, such as by at least one of pickling or etching, as shown in FIG. 19 .

根据一些实施例，在方法200的210中，在衬底402的第一晶体管区域421a之上形成多个第一栅极结构430a，并且在衬底402的第二晶体管区域421b之上形成多个第二栅极结构430b，使得多个第二栅极结构430b邻近多个低压浅阱414b，如图23所示。转到图19，根据一些实施例，在图23之前，以与以上关于第一层栅极介电材料304描述的相同方式(例如如图3所示)，在衬底402之上形成第一层栅极介电材料404。在一些实施例中，以与以上诸如图4所示的关于第一层栅极介电材料304描述的相同方式，从衬底402的第一晶体管区域431a去除第一层栅极介电材料404，如图20所示。在一些实施例中，以与以上诸如图5所示的关于低压栅极电介质304a和高压栅极电介质304b的形成描述的相同方式，在第一层栅极介电材料404之上形成第二层栅极介电材料405，以形成低压栅极电介质404a和高压栅极电介质404b，如图21所示。在一些实施例中，以与以上诸如图6所示的关于该层栅电极材料310描述的相同方式，在低压栅极电介质404a和高压栅极电介质404b之上形成一层栅电极材料410，如图22所示。在一些实施例中，图案化该层栅电极材料410、低压栅极电介质404a和高压栅极电介质404b，以同时形成第一晶体管区域421a中的多个第一栅极结构430a和第二晶体管区域421b中的多个第二栅极结构430b，如图23所示。在一些实施例中，多个第一栅极结构430a的相应栅极结构具有第一宽度440a，并且多个第二栅极结构430b的相应栅极结构具有第二宽度440b。在一些实施例中，第二宽度440b大于第一宽度440a。在一些实施例中，第二宽度440b大于第一残留光刻胶宽度413，使得多个高压浅阱414b中的至少一些或多个高压口袋注入区428b中的至少一些中的至少一个在多个第二栅极结构430b下面。According to some embodiments, in 210 of the method 200, a plurality of first gate structures 430a are formed over the first transistor region 421a of the substrate 402, and a plurality of gate structures 430a are formed over the second transistor region 421b of the substrate 402 The second gate structure 430b, such that the plurality of second gate structures 430b are adjacent to the plurality of low voltage shallow wells 414b, as shown in FIG. 23 . Turning to FIG. 19 , according to some embodiments, prior to FIG. 23 , a first layer of gate dielectric material 304 is formed over the substrate 402 in the same manner as described above with respect to the first layer of gate dielectric material 304 (eg, as shown in FIG. 3 ). layer gate dielectric material 404 . In some embodiments, the first layer of gate dielectric material 404 is removed from the first transistor region 431a of the substrate 402 in the same manner as described above with respect to the first layer of gate dielectric material 304 such as shown in FIG. , as shown in Figure 20. In some embodiments, a second layer is formed over the first layer of gate dielectric material 404 in the same manner as described above with respect to the formation of low voltage gate dielectric 304a and high voltage gate dielectric 304b such as shown in FIG. gate dielectric material 405 to form a low voltage gate dielectric 404a and a high voltage gate dielectric 404b, as shown in FIG. 21 . In some embodiments, a layer of gate electrode material 410 is formed over low voltage gate dielectric 404a and high voltage gate dielectric 404b in the same manner as described above with respect to the layer of gate electrode material 310, such as shown in FIG. Figure 22 shows. In some embodiments, the layer of gate electrode material 410, the low voltage gate dielectric 404a, and the high voltage gate dielectric 404b are patterned to simultaneously form the plurality of first gate structures 430a in the first transistor region 421a and the second transistor region A plurality of second gate structures 430b in 421b, as shown in FIG. 23 . In some embodiments, a corresponding gate structure of the plurality of first gate structures 430a has a first width 440a, and a corresponding gate structure of the plurality of second gate structures 430b has a second width 440b. In some embodiments, the second width 440b is greater than the first width 440a. In some embodiments, the second width 440b is greater than the first residual photoresist width 413 such that at least some of the plurality of high voltage shallow wells 414b or at least one of at least some of the plurality of high voltage pocket implant regions 428b are within the plurality of Below the second gate structure 430b.

根据一些实施例，在方法200的212中，在多个第二栅极结构430b和第二晶体管区域421b之上形成低压光刻胶408a，从而暴露多个第一栅极结构430a和邻近多个第一栅极结构430a的多个低压注入区411a，如图24所示。在一些实施例中，根据一些实施例，在多个第一栅极结构430a、多个第二栅极结构430b以及衬底402之上形成第一低压光刻胶(未示出)。在一些实施例中，图案化第一低压光刻胶，以形成低压光刻胶408a。According to some embodiments, at 212 of method 200, a low voltage photoresist 408a is formed over the plurality of second gate structures 430b and the second transistor regions 421b, thereby exposing the plurality of first gate structures 430a and the adjacent plurality of A plurality of low voltage injection regions 411a of the first gate structure 430a are shown in FIG. 24 . In some embodiments, a first low voltage photoresist (not shown) is formed over the plurality of first gate structures 430a, the plurality of second gate structures 430b, and the substrate 402, according to some embodiments. In some embodiments, the first low-voltage photoresist is patterned to form low-voltage photoresist 408a.

根据一些实施例，在方法200的214中，执行低压LDD注入，以将第一低压掺杂物418c注入到多个低压注入区411a中，以形成多个低压浅阱414a，如图24所示。在一些实施例中，第一低压掺杂物418c包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第一低压掺杂物418c。在一些实施例中，对半导体布置400执行第三退火，使得多个低压浅阱414a在多个第一栅极结构430a下面迁移。在一些实施例中，低压光刻胶408a防止第一低压掺杂物418c进入低压光刻胶408a下面的区域。在一些实施例中，通过所选额定电压，以在器件制造中使用的第三角度，注入第一低压掺杂物418c。According to some embodiments, in 214 of the method 200, a low-voltage LDD implant is performed to implant a first low-voltage dopant 418c into a plurality of low-voltage implanted regions 411a to form a plurality of low-voltage shallow wells 414a, as shown in FIG. 24 . In some embodiments, the first low voltage dopant 418c includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the first low voltage dopant 418c is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, a third anneal is performed on the semiconductor arrangement 400 such that the plurality of low voltage shallow wells 414a migrate under the plurality of first gate structures 430a. In some embodiments, the low voltage photoresist 408a prevents the first low voltage dopant 418c from entering the region below the low voltage photoresist 408a. In some embodiments, the first low voltage dopant 418c is implanted at a third angle used in device fabrication with a selected nominal voltage.

根据一些实施例，在方法200的216中，执行低压口袋注入，以将第二低压掺杂物418d注入到多个低压注入区411a中，以形成多个低压口袋注入区428a，如图25所示。在一些实施例中，第二低压掺杂物418d包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第二低压掺杂物418d。在一些实施例中，低压光刻胶408a防止第二低压掺杂物418d进入低压光刻胶408a下面的区域中。在一些实施例中，通过所选额定电压，以在器件制造中使用的第四角度注入第二低压掺杂物418d。在一些实施例中，多个低压口袋注入区428a至少部分地在多个第一栅极结构430a下面。在一些实施例中，对半导体布置400执行第四退火，使得多个低压浅阱414a和多个低压口袋注入区428a在多个第一栅极结构430a下面迁移。在一些实施例中，诸如通过酸洗或蚀刻中的至少一种，从多个第二栅极结构430a和衬底402去除低压光刻胶408a，如图26所示。According to some embodiments, in 216 of the method 200, a low-voltage pocket implant is performed to implant a second low-voltage dopant 418d into the plurality of low-voltage implant regions 411a to form a plurality of low-voltage pocket implant regions 428a, as shown in FIG. Show. In some embodiments, the second low voltage dopant 418d includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the second low voltage dopant 418d is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, the low voltage photoresist 408a prevents the second low voltage photoresist 418d from entering the region below the low voltage photoresist 408a. In some embodiments, the second low voltage dopant 418d is implanted at a fourth angle used in device fabrication with the selected nominal voltage. In some embodiments, the plurality of low voltage pocket implant regions 428a at least partially underlies the plurality of first gate structures 430a. In some embodiments, a fourth anneal is performed on the semiconductor arrangement 400 such that the plurality of low voltage shallow wells 414a and the plurality of low voltage pocket implant regions 428a migrate under the plurality of first gate structures 430a. In some embodiments, the low voltage photoresist 408a is removed from the plurality of second gate structures 430a and the substrate 402 , such as by at least one of pickling or etching, as shown in FIG. 26 .

在一些实施例中，在多个第一栅极结构430a、多个第二栅极结构430b和衬底402之上形成一层侧壁材料(未示出)。在一些实施例中，该层侧壁材料包括氮化物。在一些实施例中，图案化该层侧壁材料，以同时形成邻近多个第一栅极结构430a的多个第一侧壁隔离物409a和邻近多个第二栅极结构430b的多个第二侧壁隔离物409b。In some embodiments, a layer of sidewall material (not shown) is formed over the plurality of first gate structures 430 a , the plurality of second gate structures 430 b and the substrate 402 . In some embodiments, the layer of sidewall material includes nitride. In some embodiments, the layer of sidewall material is patterned to simultaneously form the plurality of first sidewall spacers 409a adjacent to the plurality of first gate structures 430a and the plurality of first sidewall spacers 409a adjacent to the plurality of second gate structures 430b. Two side wall spacers 409b.

在一些实施例中，根据一些实施例，与相应图案化的光刻胶(未示出)关联地执行低压深阱注入，以将第三低压掺杂物(未示出)注入到多个低压浅阱414a中，以形成第一源极漏极区444a，如图26所示。在一些实施例中，第三低压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量注入第三低压掺杂物。在一些实施例中，根据一些实施例，与相应图案化的光刻胶(未示出)关联地执行高压深阱注入，以将第三高压掺杂物(未示出)注入到多个高压浅阱414b中，以形成第二源极漏极区444b，如图26所示。在一些实施例中，第三高压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。在一些实施例中，通过所选额定电压，以在器件制造中使用的剂量和能量，注入第三高压掺杂物。In some embodiments, a low-voltage deep well implant is performed in association with a correspondingly patterned photoresist (not shown) to implant a third low-voltage dopant (not shown) into the plurality of low-voltage In the shallow well 414a, a first source-drain region 444a is formed, as shown in FIG. 26 . In some embodiments, the third low voltage dopant includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the third low voltage dopant is implanted at a dose and energy used in device fabrication with a selected nominal voltage. In some embodiments, a high voltage deep well implant is performed in association with a correspondingly patterned photoresist (not shown) to implant a third high voltage dopant (not shown) into the plurality of high voltage In the shallow well 414b, a second source and drain region 444b is formed, as shown in FIG. 26 . In some embodiments, the third high voltage dopant includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, or carbon. In some embodiments, the third high voltage dopant is implanted at a dose and energy used in device fabrication with a selected nominal voltage.

在一些实施例中，假定在形成多个高压浅阱414b和多个高压口袋注入区428b之后，在多个高压浅阱414b和多个高压口袋注入区428b之上形成多个第二栅极结构430b，多个高压浅阱414b、多个高压口袋注入428b或多个第二源极漏极区444b中的至少一个关于相应的第二栅极结构430b不对称。根据一些实施例，第二栅极结构相对于第二栅极结构一侧上的高压浅阱、高压口袋注入区或第二源极漏极区中的至少一个的重叠度不同于第二栅极结构相对于第二栅极结构另一侧上的高压浅阱、高压口袋注入区或第二源极漏极区中的至少一个的重叠度。根据一些实施例，与当第二晶体管被反向偏置时相比，当第二晶体管被正向偏置时，在第二栅极结构周围注入的掺杂物的这种不对称产生不同特征曲线。In some embodiments, it is assumed that after forming the plurality of high voltage shallow wells 414b and the plurality of high voltage pocket implant regions 428b, a plurality of second gate structures are formed over the plurality of high voltage shallow wells 414b and the plurality of high voltage pocket implant regions 428b 430b, at least one of the plurality of high voltage shallow wells 414b, the plurality of high voltage pocket implants 428b, or the plurality of second source drain regions 444b is asymmetric about the corresponding second gate structure 430b. According to some embodiments, the degree of overlap of the second gate structure with respect to at least one of the high-voltage shallow well, the high-voltage pocket implant region, or the second source-drain region on one side of the second gate structure is different from that of the second gate structure. The degree of overlap of the structure with respect to at least one of the high voltage shallow well, the high voltage pocket implant region, or the second source drain region on the other side of the second gate structure. According to some embodiments, this asymmetry of implanted dopants around the second gate structure produces different characteristics when the second transistor is forward biased compared to when the second transistor is reverse biased. curve.

根据一些实施例，一种半导体制造方法包括：形成具有第一工作电压的多个第一晶体管，多个第一晶体管包括在衬底的第一晶体管区域之上的多个第一栅极结构、邻近多个第一栅极结构的多个低压浅阱、以及邻近第一栅极结构的多个低压口袋注入区。根据一些实施例，半导体制造方法进一步包括：邻近多个第一晶体管形成具有第二工作电压的多个第二晶体管。在一些实施例中，形成多个第二晶体管包括：在多个第一栅极结构之上、在第一晶体管区域之上并且在多个第二栅极结构之上形成第一高压光刻胶，并且多个第二栅极结构在衬底的第二晶体管区域之上，从而暴露邻近多个第二栅极结构的衬底的多个高压注入区和多个第二栅极结构的多个第二栅极顶部。在一些实施例中，形成多个第二晶体管进一步包括：以第一高能量执行高压LDD注入，以将第一高压掺杂物注入到多个高压注入区中，以形成邻近多个第二栅极结构的多个高压浅阱，并且以第二高能量执行高压口袋注入，以将第二高压掺杂物注入到多个高压注入区中，以形成邻近多个第二栅极结构的多个高压口袋注入区。According to some embodiments, a semiconductor manufacturing method includes: forming a plurality of first transistors having a first operating voltage, the plurality of first transistors including a plurality of first gate structures over a first transistor region of a substrate, A plurality of low voltage shallow wells adjacent to the first gate structures, and a plurality of low voltage pocket implant regions adjacent to the first gate structures. According to some embodiments, the semiconductor manufacturing method further includes forming a plurality of second transistors having a second operating voltage adjacent to the plurality of first transistors. In some embodiments, forming the plurality of second transistors includes: forming a first high voltage photoresist over the plurality of first gate structures, over the first transistor region, and over the plurality of second gate structures , and the plurality of second gate structures are over the second transistor region of the substrate, thereby exposing the plurality of high voltage implant regions of the substrate adjacent to the plurality of second gate structures and the plurality of the plurality of second gate structures the top of the second gate. In some embodiments, forming the plurality of second transistors further includes: performing high-voltage LDD implantation with a first high energy, so as to implant the first high-voltage dopant into the plurality of high-voltage implantation regions to form adjacent to the plurality of second gates. A plurality of high-voltage shallow wells of the electrode structure, and perform a high-voltage pocket implantation with a second high energy to implant a second high-voltage dopant into the plurality of high-voltage implanted regions to form a plurality of adjacent to the plurality of second gate structures High pressure pocket injection area.

根据一些实施例，一种半导体制造方法包括：在衬底的第一晶体管区域和衬底的第二晶体管区域之上形成第一高压光刻胶，并且图案化第一高压光刻胶，以形成第一晶体管区域之上的高压光刻胶和第二晶体管区域之上的多个高压残留光刻胶，从而暴露邻近多个高压残留光刻胶的衬底的多个高压注入区。根据一些实施例，半导体制造方法进一步包括：以第一高能量执行高压LDD注入，以将第一高压掺杂物注入多个高压注入区中，以形成邻近多个高压残留光刻胶的多个高压浅阱，并且以第二高能量执行高压口袋注入，以将第二高压掺杂物注入到多个高压注入区中，以形成邻近多个高压残留光刻胶的多个高压口袋注入区。According to some embodiments, a semiconductor manufacturing method includes: forming a first high voltage photoresist over a first transistor region of a substrate and a second transistor region of a substrate, and patterning the first high voltage photoresist to form The high voltage photoresist over the first transistor region and the plurality of high voltage residual photoresists over the second transistor region thereby exposing a plurality of high voltage implant regions of the substrate adjacent to the plurality of high voltage residual photoresists. According to some embodiments, the semiconductor manufacturing method further includes: performing a high voltage LDD implant at a first high energy to implant a first high voltage dopant into the plurality of high voltage implant regions to form a plurality of high voltage residual photoresist adjacent to the plurality of high voltage shallow well, and perform high voltage pocket implantation with a second high energy to implant a second high voltage dopant into the plurality of high voltage implant regions to form a plurality of high voltage pocket implant regions adjacent to the plurality of high voltage residual photoresist.

根据一些实施例，注入掺杂物的方法包括：在栅极结构之上沉积光刻胶，栅极结构在衬底之上；图案化光刻胶，使得光刻胶在栅极结构的顶面的一部分之上而不是所有部分之上，使得光刻胶的光刻胶宽度小于栅极结构的栅极结构宽度；以及在光刻胶在栅极结构之上时，将第一掺杂物注入衬底中，以在邻近栅极结构的衬底中形成第一掺杂区。According to some embodiments, the method of implanting dopants includes: depositing photoresist over the gate structure, the gate structure is over the substrate; patterning the photoresist such that the photoresist is on the top surface of the gate structure over a portion but not all of the portion such that the photoresist has a photoresist width less than the gate structure width of the gate structure; and when the photoresist is over the gate structure, implanting the first dopant In the substrate, a first doped region is formed in the substrate adjacent to the gate structure.

以上概述了多个实施例的特征，使得本领域技术人员可以更好地理解本公开的多个方面。本领域技术人员将想到，它们可以容易地使用本公开作为用于设计或修改用于实现与在此介绍的实施例相同的目的和/或实现与其相同的优点的其他处理和结构的基础。本领域技术人员还将认识到，这样的等效结构不脱离本公开的精神和范围，并且它们可以在不脱离本公开的精神和范围的情况下，在此作出多种改变、替换和更改。The foregoing summarizes features of various embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

在此提供实施例的多种操作。描述一些或所有操作的顺序应该不被解释为暗示这些操作必须是顺序依赖的。将想到具有本说明书的益处的可选排序。而且，将理解，不是所有操作都必须出现在在此提供的每个实施例中。而且，将理解，不是所有操作在一些实施例中都是必须的。Various operations of the embodiments are provided herein. The order in which some or all operations are described should not be interpreted as implying that these operations must be order-dependent. Alternative orderings will be envisioned with the benefit of this specification. Also, it will be understood that not all operations need to be present in every embodiment provided herein. Also, it will be appreciated that not all operations are necessary in some embodiments.

将想到，在一些实施例中，例如，为了简单和容易理解的目的，在此描述的层、特征、元件等通过关于另一个的特定尺寸被示出，诸如，结构尺寸或定向，并且其实际尺寸基本不同于图中所示的尺寸。另外，例如，多种技术存在用于形成在此所述的层、特征、元件等，诸如，蚀刻技术、注入技术、掺杂技术、旋涂技术、诸如磁控管或离子束溅射的溅射技术、诸如热生长的生长技术、或者诸如化学气相沉积(CVD)、物理气相沉积(PVD)、等离子体增强化学气相沉积(PECVD)、或原子层沉积(ALD)的沉积技术。It will be appreciated that in some embodiments, for example, for simplicity and ease of understanding, layers, features, elements, etc., described herein are shown with particular dimensions relative to one another, such as structural dimensions or orientations, and their actual Dimensions differ substantially from those shown in the drawings. In addition, for example, various techniques exist for forming the layers, features, elements, etc. described herein, such as etching techniques, implantation techniques, doping techniques, spin coating techniques, sputtering such as magnetron or ion beam sputtering. radiation techniques, growth techniques such as thermal growth, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

而且，在此使用“示例性”意味着用作实例、例子、例证等，并且不必须有利。如在本申请中使用的，“或者”是指包含性“或者”而不是排他性“或者”。另外，除非另外或者从上下文清楚地指示是单数形式，在本申请和所附权利要求中使用的“一个(a)”和“一个(an)”通常被解释为是指“一个或多个”。而且，A和B等中的至少一个通常是指A或B或者A和B。而且，在某种意义上，使用“包括(include)”、“具有(having)”、“具有(has)”、“具有(with)”或其变体，这样的术语以类似于术语“包括(comprising)”的方式为包含性的。而且，除非另外指出，“第一”、“第二”等不旨在暗示时间方面、空间方面、排序等。而是，这样的术语仅用作用于特征、元件、项等的标识符、名称等。例如，第一元件和第二元件通常对应于元件A和元件B或者两个不同或者两个相同元件或同一元件。Also, use of "exemplary" herein means serving as an example, instance, illustration, etc., and not necessarily advantageous. As used in this application, "or" means an inclusive "or" rather than an exclusive "or". Additionally, as used in this application and the appended claims, "a" and "an" are generally construed to mean "one or more" unless otherwise indicated or the context clearly indicates a singular form. . Also, at least one of A and B etc. usually means A or B or A and B. Also, in a sense, the use of "include", "having", "has", "with" or variations thereof, such terms are used in a manner similar to the term "including (comprising)" is inclusive. Also, "first," "second," etc. are not intended to imply temporal aspects, spatial aspects, ordering, etc. unless otherwise indicated. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, and the like. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.

而且，虽然关于一个或多个实现示出和描述了本公开，但是基于本说明书和附图的读取和理解，等效更改和修改对于本领域技术人员将发生。本公开包括所有这样的修改和更改，并且仅由以下权利要求的范围限制。特别是关于由上述组件(例如，元件、资源等)执行的多种功能，除非另外指出，即使在结构上不等效于所公开的结构，用于描述这样的组件的术语旨在对应于执行所描述的组件的指定功能的任何组件(例如，功能上等效)。另外，虽然已经关于多种实现中的仅一种描述了本公开的特定特征，但是当可能期望并且有利于任何给定或特定应用时，这样的特征可以与其他实现的一个或多个其他特征结合。Moreover, while the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to those skilled in the art upon a reading and understanding of this specification and the accompanying drawings. The present disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. Especially with respect to the various functions performed by the above-described components (eg, elements, resources, etc.), unless otherwise indicated, terminology used to describe such components is intended to correspond to the implementation Any component that is a specified function of (eg, functionally equivalent to) a described component. In addition, although certain features of the present disclosure have been described with respect to only one of various implementations, such features may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application. combined.