CN104242914B - Based on the multi-functional expansible programmable logic unit structure quickly connected - Google Patents

The present invention relates to a kind of based on the multi-functional expansible programmable logic unit structure quickly connected, it includes at least one set of programmable logic cells body, and the programmable logic cells body includes the generator input control module for being used for the function generator and control function generator output form for receiving input signal；The output end of function generator is connected with adder Module, the output end of the adder Module, the output end of function generator are connected with look-up table output control module, the look-up table output control module is connected with DFF input control modules, the DFF input control modules are connected with sequential memory module, sequential memory module is connected with DFF output control modules, and exports programmed logic output by the DFF output modules.Logical resource of the present invention and path are abundant, and configurability is strong, and speed is fast, and flexibly, multi-functional function fulfillment capability is wide for Path selection.

Based on the multi-functional expansible programmable logic unit structure quickly connected

Technical field

The present invention relates to a kind of logical unit structure, it is especially a kind of based on it is multi-functional it is expansible quickly connect it is programmable Logical unit structure, belongs to the technical field of PLD.

Background technology

PLD, by Software tool, exploitation, emulation and test, rapidly by design programming into device, Substantial amounts of non-repeatability engineering cost and circuit R＆D cycle are saved, while PLD is depositing based on repetition configuration Storage technology, it is only necessary to re-download programming, you can complete the modification of circuit.PLD has the construction cycle short, into This is low, and risk is small, and integrated level is high, and flexibility is big, and is easy to the advantages of electronic system maintenance and upgrading, therefore receives vast end Hold product user favor, become the main flow of IC chip, and be widely used in various fields as communicate, control, Video, information processing, electronics, internet, automobile and Aero-Space etc..

PLD, mainly comprising programmable logic cells, Digital Signal Processing DSP, memory cell BRAM with And some high-speed interfaces, clock module and IP kernel etc., and programmable logic cells are most basic and core in PLD The structure of the heart, it is repeated to be distributed in the devices by array, and with the increase of chip application scale, and enter ten million gate leve battle array Row, thus programmable logic cells design be whole device key, its performance decides the performance of whole chip, such as work( Can, operational capability may be programmed flexibility, completion rate, area, speed and power consumption etc..The present invention propose it is a kind of it is new can Programmed logic cellular construction, the structure is based on look-up table, and the combinational logic of auxiliary multi signal input and abundant path are defeated Go out resource, and wide logic the Fast Carry Logic, and strong with configurability, speed is fast, Path selection flexibly, multi-functional letter The advantages of number fulfillment capability is wide.

The content of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art expansible quickly to connect based on multi-functional there is provided one kind The programmable logic unit structure connect, its logical resource and path are enriched, and configurability is strong, and speed is fast, and Path selection is flexible, Multi-functional function fulfillment capability is wide.

The technical scheme provided according to the present invention, it is described based on the multi-functional expansible programmable logic cells quickly connected Structure, including at least one set of programmable logic cells body, the programmable logic cells body include being used to receive input signal The generator input control module of function generator and the control function generator output form；The output of function generator End is connected with adder Module, the output end of the adder Module, the output end of function generator and look-up table output control Module is connected, and the look-up table output control module is connected with DFF input control modules, the DFF input control modules and when Sequence memory module is connected, and sequential memory module is connected with DFF output control modules, and exports volume by the DFF output modules Journey logic is exported.

Programmable logic unit structure is connected and composed by the programmable logic cells body of even number set, adjacent FPGA Connected between cell cube by width input look-up table logic module, the input of the wide input look-up table logic module connects respectively Receive the output signal of two FPGA cell cubes, the selection end and function generator of wide input look-up table logic module it is corresponding Output end is connected, and the output end of wide input look-up table logic module is connected with the input of look-up table output control module.

The function generator includes the one or five input look-up table means 1A and the two or five input look-up table means 1B, hair Raw device input control module includes the one or three input selector and the two or three input selector；

One or five input look-up table means 1A O5 output ends are connected with an input of the one or two input selector, and second Five input searching modul 1B O5 output ends are connected with another input of the one or two input selector, the two or five input look-up table Module 1B the 5th signal input part is connected with the output end of the one or three input selector, the input of the one or three input selector Input signal A5, input signal A6 and carry signal CIN, the selection end and the two or three of the one or two input selector are received respectively The output end connection of input selector, the input of the two or three input selector receives configuration signal logic " 1 ", input letter respectively Number A6 and logic carry signal LEI.

The adder Module includes first adder and the two or two input selector, the two or two input selector An input be connected with the one or five input look-up table means 1A O3 output ends, another input of the two or two input selector Input signal A5 is received, the output end of the two or two input selector is used as a positional operand of first adder, the one or two input The output end of selector as first adder another positional operand；First adder connects with adder carry logic chain CIN Connect, the output end of first adder is connected with the input of look-up table output control module.

The look-up table output control module includes the one or six input selector 7A and the two or six input selector 7B, the One or six input selector 7A input, the two or six input selector 7B input are defeated with the one or two input selector respectively Go out end, the output end of first adder, the two or five input look-up table 1B O5 output ends connection, and the one or six input selector 7A Input, the two or six input selector 7B input also receive input signal AX, input signal AY.

Input, the two or the six input selector 7B input of one or the six input selector 7A is also respectively connected with width Input the output end connection of look-up table logic module.

The DFF input control modules include the three or two input selector 8A and the four or two input selector 8B；3rd A two input selector 8A input is connected with the one or six input selector 7A output end, the four or two input selector 8B's One input is connected with the two or six input selector 7B output end, the three or two input selector 8A another input, the 4th Two input selector 8B another input and the DFF carry-outs of previous stage are connected.

Another input of three or the two input selector 8A receives the DFF of previous stage by the three or three input selector Carry-out；The output end of three or three input selector is connected with the three or two input selector 8A input, the three or three input The input of selector receives input signal AY, static input initial value logical zero/1 and previous stage DFF carry-outs.

The sequential memory module includes the first DFF triggers 9A and the 2nd DFF trigger 9B, the DFF outputs control Molding block includes the five or two input selector 10A and the six or two input selector 10B；First DFF triggers 9A D ends and the Three or two input selector 8A output end connection, the first DFF triggers 9A Q ends and the one of the five or two input selector 10A defeated Enter end connection, the five or two input selector 10A another input is connected with the one or six input selector 7A output end；Second DFF triggers 9B D ends are connected with the four or two input selector 8B output end, the 2nd DFF triggers 9B Q ends and the six or two Input selector 10B input connection, the six or two input selector 10B another input and the two or six input selector 7B output end connection.

Advantages of the present invention：Include at least one set of programmable logic cells body in programmable logic unit structure, may be programmed Logical unit structure can need to be configured to various functions form according to user, configurability it is strong, flexibility is high, wherein entering Position chain logic, can not directly be cascaded by peripheral wiring resource, is rapidly realized wider logical function, saved by internal Interconnection resources, with abundant path export resource, connected up for user flexibility.

Brief description of the drawings

Fig. 1 is the circuit structure diagram of programmable logic cells of the present invention.

Fig. 2 is programmable logic cells group LUTA of the present invention circuit structure diagram.

Fig. 3 is the circuit structure diagram of the wide look-up table logic of programmable logic cells of the present invention.

Fig. 4 is the output control module circuit structure diagram of programmable logic cells of the present invention.

Fig. 5 is the circuit structure diagram of the trigger DFF chains of programmable logic cells of the present invention.

Embodiment

With reference to specific drawings and examples, the invention will be further described.

As shown in Figure 1：In order to which the combinational logic and abundant path of realizing auxiliary multi signal input export resource, raising can Allocative abilities, the present invention includes at least one set of programmable logic cells body, and the programmable logic cells body includes being used to receive The function generator of input signal and the generator input control module of the control function generator output form；Function is sent out The output end of raw device is connected with adder Module, the output end of the adder Module, the output end of function generator and lookup Table output control module is connected, and the look-up table output control module is connected with DFF input control modules, the DFF inputs control Molding block is connected with sequential memory module, and sequential memory module is connected with DFF output control modules, and is exported by the DFF Module output programmed logic output.

Further, programmable logic unit structure is connected and composed by the programmable logic cells body of even number set, adjacent Connected between programmable logic cells body by width input look-up table logic module, the width inputs the defeated of look-up table logic module Enter the output signal that end receives two FPGA cell cubes respectively, the selection end and function hair of wide input look-up table logic module The corresponding output end connection of raw device, the output end and the input of look-up table output control module of wide input look-up table logic module Connection.

Specifically, four groups of programmable logic cells bodies are shown in Fig. 1, four groups of programmable logic cells bodies are respectively Structure in LUTA, LUTB, LUTC and LUTD, four groups of programmable logic cells bodies is identical, using use five input look-up tables as Example, the one or five input look-up table means 1A, the two or five input look-up table means 1B, the are included in programmable logic cells body LUTA One adder 2, the one or two input selector 3, the one or three input selector 4, the input choosing of the two or three input selector the 5, the 2nd 2 Select device 6, the one or six input selector 7A, the two or six input selector 7B, the three or two input selector 8A, the four or two input selection Device 8B, the first DFF triggers 9A, the 2nd DFF triggers 9B, the five or two input selector 10A and the six or two input selector 10B.The output end formation O6_A output ends of one or two input selector 3.

Searched for including the three or five input look-up table means 11A, the four or five input in programmable logic cells body LUTB Table module 11B, second adder 12, the seven or two input selector 13, the four or three input selector 14, the five or three input selector 15th, the eight or two input selector 16, the three or six input selector 17A, the four or six input selector 17B, the 9th 2 input selection Device 18A, the 12nd input selector 18B, the 3rd DFF triggers 19A, the 4th DFF triggers 19B, the 11st input selection Device 20A and the 12nd input selector 20B.The output end of seven or two input selector 13 can form O6_B output ends.

Searched for including the five or five input look-up table means 21A, the six or five input in programmable logic cells body LUTC Table module 21B, the 3rd adder 22, the 13rd input selector 23, the input selection of the six or three input selector the 24, the 7th 3 It is device 25, the 14th input selector 26, the five or six input selector 27A, the seven or six input selector 27B, the 14th defeated Enter selector 28A, the 15th input selector 28B, the 5th DFF triggers 29A, the 6th DFF triggers 29B, the 17th Input selector 30A and the 18th input selector 30B.The output end of 13rd input selector 23 can form O6_C Output end.

Include the Seventh Five-Year Plan input look-up table means 31A, the eight or five input look-up table for programmable logic cells body LUTD Module 31B, the 4th adder 32, the 19th input selector 33, the eight or three input selector 34, the 9th 3 input selector 35th, the 22nd input selector 36, the seven or six input selector 37A, the eight or six input selector 37B, the 21st input Selector 38A, the 22nd input selector 38B, the 7th DFF triggers 39A, the 8th DFF triggers 39B, the 23rd Two input selector 40A and the 24th input selector 40B.The output end of 19th input selector 33 can be formed O6_D output ends.

Programmable logic cells body LUTA receives input signal A1 ~ A6, AX and AY, programmable logic cells body LUTA's Output signal is AQ1, AQ2, O6_A.Programmable logic cells body LUTB receives input signal B1 ~ B6, BX and BY, may be programmed Logic unit body LUTB output signal is BQ1, BQ2, O6_B, programmable logic cells body LUTC receive input signal C1 ~ C6, CX and CY, programmable logic cells body LUTC output signal are CQ1, CQ2 and O6_C, programmable logic cells body LUTD Input signal D1 ~ D6, DX and DY is received, programmable logic cells body LUTD output signal is DQ1, DQ2 and O6_D；It is right DFF triggers in each programmable logic cells body, each DFF triggers also need to connection trigger control signal SR, CE and clock signal clk.

By taking programmable logic cells body LUTA as an example, the function generator include the one or five input look-up table means 1A with And the two or five input look-up table means 1B, generator input control module include the one or three input selector 4 and the 2nd 3 it is defeated Enter selector 5；

One or five input look-up table means 1A O5 output ends are connected with an input of the one or two input selector 3, the Two or five input searching modul 1B O5 output ends are connected with another input of the one or two input selector 3, and the two or five input is looked into Table module 1B the 5th signal input part is looked for be connected with the output end of the one or three input selector 4, the one or three input selector 4 Input receives input signal A5, input signal A6 and excites carry signal CIN, the choosing of the one or two input selector 3 respectively Select end to be connected with the output end of the two or three input selector 5, the input of the two or three input selector 5 receives configuration signal respectively Logical one, input signal A6 and logic carry signal LEI.

The adder Module includes the input selector 6 of first adder 2 and the 2nd 2, the two or the two input selection One input of device 6 is connected with the one or five input look-up table means 1A O3 output ends, the two or two input selector 6 it is another defeated Enter end and receive input signal A5, the output end of the two or two input selector 6 as first adder 2 a positional operand, first The output end of two input selectors 3 as first adder 2 another positional operand；First adder 2 is patrolled with adder carry Chain CIN connections are collected, the output end of first adder 2 is connected with the input of look-up table output control module.

In the embodiment of the present invention, by selecting the one or three input selector 4 to control, the A5 inputs of selection input signal are right Two or three input selector 5 selection control, selection signal A6 inputs are defeated by the one or five input look-up table means 1A and the two or five Enter look-up table means 1B and be configured as one six input look-up table, that is, obtain six input look-up table LUT6（Six inputs are respectively A1, A2, A3, A4, A5, A6）.

By selecting the one or three input selector 4 to control, selection input signal A5 inputs, to the two or three input selector The one or five input look-up table means 1A in 5 selection controls, selection input signal logical one input, function generator and the Two or five input look-up table means 1B are configured as five look-up tables of two identical five inputs, i.e. LUT5（Two it is identical five input Input signal is respectively A1, A2, A3, A4, A5）；By selecting the one or three input selector 4 to control, selection input signal A6 Input, selects the two or three input selector 5 to control, selects input signal logical one, and the one or five in function generator is defeated Enter the inputs of look-up table means 1A and the two or five look-up table means 1B and be configured as two with identical four input, one different defeated Five input look-up table, the i.e. LUT5A entered（The input signal of five input look-up tables is respectively A1, A2, A3, A4, A6）And LUT5B （The input signal of five input look-up tables is respectively A1, A2, A3, A4, A5）, therefore function generator can be according to the need of user Ask, flexibly configured, realize different power functions.

One or five input look-up table basic module 1A output end O3, input signal A5 in programmable logic cells body LUTA Be connected with the input of the two or two input selector 6, the output signal of the two or two input selector 6 as first adder 2 wherein One positional operand；The output signal of one or two input selector 3 as first adder 2 another operand.One or two input The input selector 6 of selector 3 and the 2nd 2 and carry signal CIN, an adder Module is constituted with first adder 2, The adder Module can realize that the complete of one digit number adds, subtraction and multiplication function.

One or three input selector 4 is selected to control, selection adder carry logic chain CIN inputs, by the two or five Input look-up table means 1B enter line function configuration, constitute one one based on the built-in adder inside look-up table, be referred to as Second adder.

The look-up table output control module includes the one or six input selector 7A and the two or six input selector 7B, the One or six input selector 7A input, the two or six input selector 7B input respectively with the one or two input selector 3 Output end, the output end of first adder 2, the two or five input look-up table 1B O5 output ends connection, and the one or six input selection Device 7A input, the two or six input selector 7B input also receive input signal AX, input signal AY.

In the embodiment of the present invention, the one or six input selector 7A and the two or six input selector 7B input signal are complete It is identical, two identical path outputs are constructed, is selected for user, enhances configurability.

The DFF input control modules include the three or two input selector 8A and the four or two input selector 8B；3rd A two input selector 8A input is connected with the one or six input selector 7A output end, the four or two input selector 8B's One input is connected with the two or six input selector 7B output end, the three or two input selector 8A another input, the 4th Two input selector 8B another input and the DFF carry-outs of previous stage are connected.

Further, another input of the three or the two input selector 8A is received by the three or three input selector 47 The DFF carry-outs of previous stage；The output end of three or three input selector 47 connects with the three or two input selector 8A input Connect, the input of the three or three input selector 47 receives input signal AY, static input initial value logical zero/1 and previous stage DFF carry-outs.

For programmable logic cells body LUTB, programmable logic cells body LUTC and programmable logic cells body LUTD Interior, an input of corresponding two input selector of DFF input control modules and the DFF carry-outs of previous stage are connected, specifically Ground is, the four or two input selector 8B another input and the first DFF triggers 9A Q in programmable logic cells body LUTA End connection；A 9th 2 input selector 18A input and programmable logic cells body in programmable logic cells body LUTB 2nd DFF triggers 9B Q ends connection, the 12nd input selector 18B an input and programmable logic cells in LUTA 3rd DFF triggers 19A Q ends connection in body LUTB.15th input selector 28A in programmable logic cells body LUTC An input be connected with the Q ends of the 4th DFF triggers 19B in programmable logic cells body LUTB, the 16th input selection A device 28B input is connected with the Q ends of the 5th DFF triggers 29A in programmable logic cells body LUTC, FPGA list A the 21st input selector 38A input is touched with the 6th DFF in programmable logic cells body LUTC in first body LUTD Send out device 29B Q ends connection, a 22nd input selector 38B input and in programmable logic cells body LUTD the Seven DFF triggers 39A Q ends connection.

The sequential memory module includes the first DFF triggers 9A and the 2nd DFF trigger 9B, the DFF outputs control Molding block includes the five or two input selector 10A and the six or two input selector 10B；First DFF triggers 9A D ends and the Three or two input selector 8A output end connection, the first DFF triggers 9A Q ends and the one of the five or two input selector 10A defeated Enter end connection, the five or two input selector 10A another input is connected with the one or six input selector 7A output end；Second DFF triggers 9B D ends are connected with the four or two input selector 8B output end, the 2nd DFF triggers 9B Q ends and the six or two Input selector 10B input connection, the six or two input selector 10B another input and the two or six input selector 7B output end connection.

In the embodiment of the present invention, the first DFF triggers 9A, the 2nd DFF triggers 9B CE ends are connected with CE signals, and first DFF triggers 9A, the 2nd DFF triggers 9B CK ends are connected with the output end of the 31st input selector 48, and the 30th Two inputs of one or two input selectors 48 are respectively CLK signal and CLK inversion signal, according to outside selection signal, really The output of fixed 24th input selector 48, so as to enter the input of row clock signal into DFF triggers.First DFF Trigger 9A, the 2nd DFF triggers 9B SR ends are connected with outside SR signals.

When there is multigroup FPGA group cell cube, then programmable logic cells body in programmable logic unit structure Quantity is even number, when there is multiple programmable logic cells bodies, is connected by width input look-up table logic module, to realize more The look-up table of width input.

For programmable logic cells body LUTA, programmable logic cells body LUTB, programmable logic cells body LUTC with And for programmable logic cells body LUTD, wide input look-up table logic module includes the 25th input selector 41, the 26 input selectors 42, the 27th input selector 43, the 28th input selector the 44, the 29th The input selector 46 of input selector 45 and the 32nd.

One end of 25th input selector 41 is connected with the output end of the one or two input selector 3, and the 25th The other end of two input selectors 41 is connected with the output end of the seven or two input selector 13, the 25th input selector 41 Selection end be connected with input signal AX, the output end of the 25th input selector 41 is with the one or six input selector 7A's The input connection of input, the two or six input selector 7B input and the 27th input selector 43.

One input of the 26th input selector 42 is connected with the output end of the 18th input selector 33, the Another input of 26 input selectors 42 is connected with the output end of the 13rd input selector 23, and the 26th The selection end of input selector 42 is connected with input signal CX, the output end of the 26th input selector 42 and the five or six defeated Enter the input connection of selector 27A input and the six or six input selector 27B, the 26th input selector 42 Another input of the output end also with the 27th input selector 43 be connected.The choosing of 27th input selector 43 Select end be connected with input signal BX, the output end of the 27th input selector 43 and with the 28th input selector 44 Input connection, another input of the 28th input selector 44 is connected with wide lookup function carry chain O8, the The selection end of 28 input selectors 44 is connected with input signal BY.

The output end of 28th input selector 44 is connected with an input of the 29th input selector 45, Another input of 29th input selector 45 is connected with the output end of the 27th input selector 43, and the 20th The output end of 92 input selectors 45 and the three or six input selector 17A input and the four or six input selector 17B Input connection.

One input of the 32nd input selector 46 is connected with the output end of the 28th input selector 44, the Another input of 32 input selectors 46 is searched table function carry chain O9 with width and is connected, the 32nd input selector 46 Selection end be connected with input signal DX, the output end of the 13rd input selector 46 is with the seven or six input selector 37A's Input and the eight or six input selector 37B input connection.

For having the structure of multigroup programmable logic cells body, the carry output and second adder of first adder 2 12 carry input connection, the carry output of second adder 12 is connected with the carry input of the 3rd adder 22, the The carry output of three adders 22 is connected with the carry input of the 4th adder 32, the carry output of the 4th adder 32 Output carry output signal COUT.In addition, the output end of the one or two input selector 3 and the input of the five or three input selector 15 End connection, the output end of the five or three input selector 15 is connected with the selection end of the seven or two input selector 13, the seven or two input The output end of selector 13 is connected with the input of the seven or three input selector 25, the output end of the seven or three input selector 25 with The selection end connection of 13rd input selector 23, the output end of the 13rd input selector 23 is selected with the 9th 3 input The input connection of device 35, the output end of the 9th 3 input selector 35 connects with the selection end of the 18th input selector 33 Connect, the output end of the 18th input selector 33 can form logical extension carry-out chain LEO.

Structure as shown in Figure 3, programmable logic cells body LUTA output end O6_A and programmable logic cells body LUTB Output end O6_B, seven input look-up table LUT7A are configured to by the 25th input selector 41（Seven input look-up tables Input signal is respectively A1, A2, A3, A4, A5, A6, AX）, selection signal is AX, wherein requiring input signal A1 ~ A6 and input Signal B1 ~ B6 input signal is consistent；Equally, programmable logic cells body LUTC output end O6_C and FPGA Cell cube LUTD output end O6_D, seven input look-up table LUT7C are configured to by the 16th input selector 42（Seven inputs The input signal of look-up table is respectively C1, C2, C3, C4, C5, C6, CX）, selection signal is CX, wherein require input signal C1 ~ C6 and input signal D1 ~ D6 input signal are consistent.

Further, the output LUT7A of the 25th input selector 41 and the 26th input selector 42 LUT7C is exported, the look-up table LUT8A of one eight input is configured to by the 27th input selector 43（Eight inputs are searched The input signal of table is respectively A1, A2, A3, A4, A5, A6, AX, BX）, selection signal is BX, wherein require input signal CX with Input signal AX signals are consistent；The output LUT8A of 27th input selector 43 searches function carry chain O8 with wide, The wide function carry chain O8 that searches is the output signal that upper level eight inputs look-up table LUT8.Pass through the 28th input selector 44 are configured to the look-up table LUT9 of one nine input（The input signals of nine input look-up tables are respectively A1, A2, A3, A4, A5, A6, AX, BX, BY）, selection signal is BY, the 29th input selector 45, for selecting nine input look-up table LUT9 or eight defeated Enter look-up table LUT8A as output；The output LUT9 of 28th input selector 44 searches table function carry chain O9 with wide, The wide table function carry chain O9 that searches is the output that upper level nine inputs look-up table LUT9, is matched somebody with somebody by the 32nd input selector 46 It is set to the look-up table LUT10 of one ten input（The input signals of ten input look-up tables are respectively A1, A2, A3, A4, A5, A6, AX, BX, BY, DX)）, selection signal is DX.Therefore the programmable logic unit structure maximum can realize ten input look-up table logics Function, enhances the function fulfillment capability of user.

As shown in figure 5, above-mentioned programmable logic cells body LUTA, programmable logic cells body LUTB, FPGA list First body LUTC and programmable logic cells body LUTD includes eight identical outgoing routes, wherein output terminals A Q1, output AQ2, output end BQ1, output end BQ2, output end CQ1, output end CQ2, output end DQ1, output end DQ2 is held to be configured to completely Eight output ports of equal value, enhance data output capacities.By to the five or two input selector 10A, the six or two input selection Device 10B, the 11st input selector 20A, the 12nd input selector 20B, the 17th input selector 30A, the tenth Eight or two input selector 30B, the 23rd input selector 40A, the 24th input selector 40B selection both may be used To select D1 ~ D8 from six input selector output ends directly to export, it can select again from the first DFF trigger 9A, the 2nd DFF Trigger 9B, the 3rd DFF trigger 19A, the 4th DFF trigger 19B, the 5th DFF trigger 29A, the 6th DFF trigger 29B, 7th DFF trigger 39A, the 8th DFF trigger 39B sequential exports, abundant path resources largely add device Data throughput capabilities and configurability.

Three or two input selector 8A, the four or two input selector 8B, the 9th 2 input selector 18A, the 12nd are inputted Selector 18B, the 15th input selector 28A, the 16th input selector 28B, the 21st input selector 38A, the 22nd input selector 38B option value signal inputs are upper level DFF output, constitute one DFF grades Join chain.The DFF carry chain logics of random length can be made up of flexible option and installment, wherein the DFF carry chains of each unit Initial value include the selector 47 of one three input and be used as initial signal, the initial value signal of its input energy selection dynamic input The DFF carry-outs of AY, static state input initial value logical zero/1 or upper level, to constitute longer DFF cascade chains.The DFF is cascaded Structure can realize many user logics such as counter, frequency divider, time delay module, the function such as FIFO.Wherein described structure it is basic Igniter module DFF such as the first DFF trigger 9A, the 2nd DFF triggers 9B etc., by configuring, can be configured to trigger DFF, The logics such as latch LATCH, synchronous/asynchronous set function SRHIGH, synchronous/asynchronous reset function SRLOW.