CN104253590A - Fully differential operational amplifier module circuit, analog-to-digital converter and readout circuit - Google Patents
- ️Wed Dec 31 2014
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- CN104253590A CN104253590A CN201410474878.9A CN201410474878A CN104253590A CN 104253590 A CN104253590 A CN 104253590A CN 201410474878 A CN201410474878 A CN 201410474878A CN 104253590 A CN104253590 A CN 104253590A Authority
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Abstract
本发明实施例公开了一种全差分运算放大器模块电路，包括折叠式共源共栅全差分运算放大器和时钟馈通频率补偿电路，该电路包括电容性元件。电容性元件一端连接到折叠式共源共栅全差分运算放大器的偏压输入端，另一端连接到时钟信号CLK。该时钟信号CLK通过电容性元件馈通到偏压输入端，从而改变偏压输入端nbias1处的电压。本发明的实施例中，增加了一个电容性元件及控制时钟信号CLK的时钟馈通频率补偿电路，能够得到较好的阶跃响应及稳定的建立时间，对全差分运算放大器有很好的频率补偿效果。
The embodiment of the present invention discloses a fully differential operational amplifier module circuit, including a folded cascode fully differential operational amplifier and a clock feedthrough frequency compensation circuit, wherein the circuit includes a capacitive element. One end of the capacitive element is connected to the bias input terminal of the folded cascode fully differential operational amplifier, and the other end is connected to the clock signal CLK. The clock signal CLK is fed through the capacitive element to the bias input terminal, thereby changing the voltage at the bias input terminal nbias1. In the embodiment of the present invention, a capacitive element and a clock feedthrough frequency compensation circuit for controlling the clock signal CLK are added, so that a better step response and a stable setup time can be obtained, and a good frequency compensation effect is achieved for the fully differential operational amplifier.
Description
the
技术领域 technical field
本发明涉及非制冷红外焦平面阵列技术领域，尤其是涉及一种全差分运算放大器模块电路、使用该全差分运算放大器模块电路的模数转换器和使用该模数转换器的非制冷红外焦平面阵列的读出电路。 The present invention relates to the technical field of uncooled infrared focal plane arrays, in particular to a fully differential operational amplifier module circuit, an analog-to-digital converter using the fully differential operational amplifier module circuit, and an uncooled infrared focal plane using the analog-to-digital converter array readout circuitry.
the
背景技术 Background technique
非制冷红外焦平面阵列探测器可在常温下工作，无需制冷设备，并具有质量轻、体积小、寿命长、成本低、功耗小、启动快及稳定性好等优点，满足了民用红外系统和部分军事红外系统对长波红外探测器的迫切需要。因而使这项技术得到了快速的发展和广泛的应用。 The uncooled infrared focal plane array detector can work at room temperature without refrigeration equipment, and has the advantages of light weight, small size, long life, low cost, low power consumption, fast startup and good stability, etc., which meets the needs of civilian infrared systems. And some military infrared systems are in urgent need of long-wave infrared detectors. As a result, this technology has been rapidly developed and widely used.
读出电路(ROIC)是非制冷红外焦平面阵列（IRFPA）的关键部件之一，它的主要功能是对红外探测器感应的微弱信号进行预处理（如积分、放大、滤波、采样/保持等）和阵列信号的并/串行转换。视探测器所用材料和工作方式的不同，读出电路结构随之变化，以在满足帧频的要求下获得最大的信噪比（SNR）。 The readout circuit (ROIC) is one of the key components of the uncooled infrared focal plane array (IRFPA). Its main function is to preprocess the weak signals sensed by the infrared detector (such as integration, amplification, filtering, sampling/holding, etc.) Parallel/serial conversion of and array signals. Depending on the material used and the working method of the detector, the structure of the readout circuit changes accordingly to obtain the maximum signal-to-noise ratio (SNR) while meeting the requirements of the frame rate.
ROIC属于数模混合集成技术。像元电路部分属于模拟电路，它对MOS管沟道宽长比有特殊的要求，需要有比数字电路更加精确的设计。另外，为了增大积分电容的面积，复杂的电路设计在ROIC中也是不容许的。先进的ROIC为了减小读出噪声和提高帧刷新频率，将滤波电路、模数转换等功能器件集成在一块芯片内。 ROIC belongs to digital-analog hybrid integration technology. The pixel circuit part is an analog circuit, which has special requirements for the channel width-to-length ratio of the MOS tube, and requires a more precise design than a digital circuit. In addition, in order to increase the area of the integrating capacitor, complex circuit design is not allowed in ROIC. In order to reduce the readout noise and increase the frame refresh rate, the advanced ROIC integrates functional devices such as filter circuits and analog-to-digital conversion into one chip.
模数转换器集成到焦平面阵列中，不但可以简化阵列与系统的接口设计，也可将易受电磁干扰的模拟输出信号转为抗干扰能力强的数字信号，提高输出信号的可靠性与系统的整体性能。模数转换器中的全差分运算放大器在一定的程度上决定了其性能。在一定的时钟频率及不同的负载的情况下，要求全差分运算放大器能够保持较好的阶跃响应特性及稳定的建立时间，这就需要对全差分运算放大器进行频率补偿，进而需要深度的分析其频率特性。 The analog-to-digital converter is integrated into the focal plane array, which not only simplifies the interface design between the array and the system, but also converts the analog output signal susceptible to electromagnetic interference into a digital signal with strong anti-interference ability, improving the reliability of the output signal and the system overall performance. The fully differential op amp in an analog-to-digital converter determines its performance to some extent. In the case of a certain clock frequency and different loads, the fully differential operational amplifier is required to maintain good step response characteristics and stable settling time, which requires frequency compensation for the fully differential operational amplifier, and then requires in-depth analysis. its frequency characteristics.
在传统的分析中，由于全差分运算放大器的相位裕度一般大于60度，所以一般将全差分运算放大器等效成一阶系统，然而，要得到其在不同负载时的稳定的建立时间及较好的阶跃相应，需要对全差分运算放大器等效成二阶系统进行分析，进而得到有效的频率补偿方案。 In the traditional analysis, since the phase margin of the fully differential operational amplifier is generally greater than 60 degrees, the fully differential operational amplifier is generally equivalent to a first-order system. However, to obtain its stable settling time and better performance under different loads The step response of the fully differential operational amplifier needs to be analyzed as a second-order system equivalently, and then an effective frequency compensation scheme can be obtained.
the
发明内容 Contents of the invention
本发明的目的之一是提供一种能够有效地进行频率补偿的全差分运算放大器模块电路、使用该全差分运算放大器模块电路的模数转换器和使用该模数转换器的非制冷红外焦平面阵列的读出电路。 One of the objects of the present invention is to provide a fully differential operational amplifier module circuit capable of effective frequency compensation, an analog-to-digital converter using the fully differential operational amplifier module circuit and an uncooled infrared focal plane using the analog-to-digital converter array readout circuitry.
本发明的目的之一是提供一种在一定的时钟频率及负载变化的情况下仍然能够得到较好的阶跃响应特性及稳定的建立时间的全差分运算放大器模块电路、使用该全差分运算放大器模块电路的模数转换器和使用该模数转换器的非制冷红外焦平面阵列的读出电路。 One of the purposes of the present invention is to provide a fully differential operational amplifier module circuit that can still obtain better step response characteristics and stable settling time under certain clock frequency and load changes. An analog-to-digital converter of a module circuit and a readout circuit of an uncooled infrared focal plane array using the analog-to-digital converter.
本发明公开的技术方案包括： The technical solutions disclosed in the present invention include:
提供了一种全差分运算放大器模块电路，其特征在于，包括：折叠式共源共栅全差分运算放大器，所述折叠式共源共栅全差分运算放大器的输入级包括偏置电路，所述偏置电路具有偏压输入端nbias1；时钟馈通频率补偿电路，所述时钟馈通频率补偿电路包括电容性元件，所述电容性元件一端连接到所述偏压输入端nbias1，另一端连接到时钟信号CLK；其中所述时钟信号CLK通过所述电容性元件馈通到所述偏压输入端nbias1，从而改变所述偏压输入端nbias1处的电压。 A fully differential operational amplifier module circuit is provided, which is characterized in that it includes: a folded cascode fully differential operational amplifier, the input stage of the folded cascode fully differential operational amplifier includes a bias circuit, the The bias circuit has a bias voltage input terminal nbias1; a clock feedthrough frequency compensation circuit, the clock feedthrough frequency compensation circuit includes a capacitive element, one end of the capacitive element is connected to the bias voltage input terminal nbias1, and the other end is connected to A clock signal CLK; wherein the clock signal CLK is fed through the capacitive element to the bias input terminal nbias1, thereby changing the voltage at the bias input terminal nbias1.
本发明的一个实施例中，所述偏置电路包括偏置MOS管MN0，所述偏压输入端nbias1连接到所述偏置MOS管MN0的栅极。 In an embodiment of the present invention, the bias circuit includes a bias MOS transistor MN0, and the bias voltage input terminal nbias1 is connected to the gate of the bias MOS transistor MN0.
本发明的一个实施例中，所述电容性元件为时钟馈通MOS管（MNC），所述时钟馈通MOS管（MNC）的源极和漏极连接到所述偏压输入端（nbias1），所述时钟馈通MOS管（MNC）的栅极连接到所述时钟信号（CLK）。 In one embodiment of the present invention, the capacitive element is a clock feedthrough MOS transistor ( MNC ), and the source and drain of the clock feedthrough MOS transistor ( MNC ) are connected to the bias input terminal ( nbias1), the gate of the clock feedthrough MOS transistor ( MNC ) is connected to the clock signal (CLK).
本发明的一个实施例中，所述时钟馈通MOS管（MNC）的衬底连接到所述偏压输入端（nbias1）。 In an embodiment of the present invention, the substrate of the clock feedthrough MOS transistor ( MNC ) is connected to the bias input terminal (nbias1).
本发明的一个实施例中，所述电容性元件为电容器，所述电容器一端连接到所述偏压输入端（nbias1），另一端连接到所述时钟信号（CLK）。 In one embodiment of the present invention, the capacitive element is a capacitor, one end of the capacitor is connected to the bias voltage input end (nbias1 ), and the other end of the capacitor is connected to the clock signal (CLK).
本发明的一个实施例中，所述折叠式共源共栅全差分运算放大器还包括第一MOS管MN1、第二MOS管MN2、第三MOS管MP3、第四MOS管MP4、第五MOS管MN5、第六MOS管MN6、第七MOS管MN7、第八MOS管MN8、第九MOS管MP9和第十MOS管MP10，其中：所述第一MOS管MN1的源极连接到所述第二MOS管MN2的源极并且连接到所述偏置MOS管MN0的漏极，所述第一MOS管MN1的栅极连接到所述折叠式共源共栅全差分运算放大器的正相输入端VIP，所述第一MOS管MN1的漏极连接到所述第四MOS管MP4的源极；所述第二MOS管MN2的栅极连接到所述折叠式共源共栅全差分运算放大器的负相输入端VIN，所述第二MOS管MN2的漏极连接到所述第三MOS管MP3的源极；所述第三MOS管MP3的源极连接到所述第九MOS管MP9的漏极，所述第三MOS管MP3的栅极连接到所述第四MOS管MP4的栅极并连接到第一偏置信号pcas，所述第三MOS管MP3的漏极连接到所述折叠式共源共栅全差分运算放大器的正相输出端VOUTP并连接到所述第五MOS管MN5的漏极；所述第四MOS管MP4的源极连接到所述第十MOS管MP10的漏极，所述第四MOS管MP4的漏极连接到所述折叠式共源共栅全差分运算放大器的负相输出端VOUTN并连接到所述第六MOS管MN6的漏极；所述第五MOS管MN5的栅极连接到所述第六MOS管MN6的栅极并且连接到第二偏置信号ncas，所述第五MOS管MN5的源极连接到所述第七MOS管MN7的漏极；所述第六MOS管MN6的源极连接到所述第八MOS管MN8的漏极；所述第七MOS管MN7的栅极连接到所述第八MOS管MN8的栅极并且连接到第三偏置信号nbias，所述第七MOS管MN7的源极接地；所述第八MOS管MN8的源极接地；所述第九MOS管MP9的栅极连接到所述第十MOS管MP10的栅极并且连接到第四偏置信号pbias,所述第九MOS管MP9的源极连接到系统电源VDD；所述第十MOS管MP10的源极连接到系统电源VDD。 In an embodiment of the present invention, the folded cascode fully differential operational amplifier further includes a first MOS transistor MN1, a second MOS transistor MN2, a third MOS transistor MP3, a fourth MOS transistor MP4, a fifth MOS transistor MN5, the sixth MOS transistor MN6, the seventh MOS transistor MN7, the eighth MOS transistor MN8, the ninth MOS transistor MP9 and the tenth MOS transistor MP10, wherein: the source of the first MOS transistor MN1 is connected to the second The source of the MOS transistor MN2 is also connected to the drain of the bias MOS transistor MN0, and the gate of the first MOS transistor MN1 is connected to the non-inverting input terminal V of the folded cascode fully differential operational amplifier. IP , the drain of the first MOS transistor MN1 is connected to the source of the fourth MOS transistor MP4; the gate of the second MOS transistor MN2 is connected to the folded cascode fully differential operational amplifier Negative input terminal V IN , the drain of the second MOS transistor MN2 is connected to the source of the third MOS transistor MP3; the source of the third MOS transistor MP3 is connected to the ninth MOS transistor MP9 Drain, the gate of the third MOS transistor MP3 is connected to the gate of the fourth MOS transistor MP4 and connected to the first bias signal pcas, the drain of the third MOS transistor MP3 is connected to the folding The non-inverting output terminal V OUTP of the cascode fully differential operational amplifier is connected to the drain of the fifth MOS transistor MN5; the source of the fourth MOS transistor MP4 is connected to the tenth MOS transistor MP10 Drain, the drain of the fourth MOS transistor MP4 is connected to the negative phase output terminal V OUTN of the folded cascode fully differential operational amplifier and is connected to the drain of the sixth MOS transistor MN6; The gate of the fifth MOS transistor MN5 is connected to the gate of the sixth MOS transistor MN6 and connected to the second bias signal ncas, and the source of the fifth MOS transistor MN5 is connected to the gate of the seventh MOS transistor MN7. drain; the source of the sixth MOS transistor MN6 is connected to the drain of the eighth MOS transistor MN8; the gate of the seventh MOS transistor MN7 is connected to the gate of the eighth MOS transistor MN8 and connected to To the third bias signal nbias, the source of the seventh MOS transistor MN7 is grounded; the source of the eighth MOS transistor MN8 is grounded; the gate of the ninth MOS transistor MP9 is connected to the tenth MOS transistor The gate of MP10 is also connected to the fourth bias signal pbias, the source of the ninth MOS transistor MP9 is connected to the system power supply V DD ; the source of the tenth MOS transistor MP10 is connected to the system power supply V DD .
本发明的一个实施例中，还提供了一种模数转换器，其包括前述的全差分运算放大器模块电路。 In one embodiment of the present invention, there is also provided an analog-to-digital converter, which includes the aforementioned fully differential operational amplifier module circuit.
本发明的一个实施例中，还提供了一种非制冷红外焦平面阵列的读出电路，其包括前述的模数转换器。 In one embodiment of the present invention, a readout circuit of an uncooled infrared focal plane array is also provided, which includes the aforementioned analog-to-digital converter.
本发明的实施例中，增加了一个MOS电容及控制时钟信号CLK的时钟馈通频率补偿电路，能够得到较好的阶跃响应及稳定的建立时间，对全差分运算放大器有很好的频率补偿效果。 In the embodiment of the present invention, a MOS capacitor and a clock feed-through frequency compensation circuit for controlling the clock signal CLK are added, which can obtain better step response and stable settling time, and have good frequency compensation for fully differential operational amplifiers Effect.
the
附图说明 Description of drawings
图1是本发明一个实施例的全差分运算放大器模块电路的结构示意图。 FIG. 1 is a schematic structural diagram of a fully differential operational amplifier module circuit according to an embodiment of the present invention.
图2是本发明一个实施例的时钟馈通频率补偿前后阶跃瞬态响应对比的仿真示意图。 FIG. 2 is a simulation diagram of a comparison of step transient responses before and after clock feedthrough frequency compensation according to an embodiment of the present invention.
图3是本发明一个实施例的时钟馈通频率补偿前后建立时间随负载变化对比的仿真示意图。 FIG. 3 is a simulation schematic diagram of a comparison of settling time with load variation before and after clock feedthrough frequency compensation according to an embodiment of the present invention.
the
具体实施方式 Detailed ways
下面将结合附图详细说明本发明的实施例的全差分运算放大器模块电路的具体结构。 The specific structure of the fully differential operational amplifier module circuit of the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
图1为本发明一个实施例的全差分运算放大器模块电路的结构示意图。 FIG. 1 is a schematic structural diagram of a fully differential operational amplifier module circuit according to an embodiment of the present invention.
如图1所示，本发明一个实施例中，一种全差分运算放大器模块电路包括折叠式共源共栅全差分运算放大器10和时钟馈通频率补偿电路20。折叠式共源共栅全差分运算放大器10的输入级包括偏置电路，该偏置电路具有偏压输入端nbias1。时钟馈通频率补偿电路20包括电容性元件，该电容性元件一端连接到折叠式共源共栅全差分运算放大器10的偏压输入端nbias1，另一端连接到时钟信号CLK。该时钟信号CLK通过该电容性元件馈通到偏压输入端nbias1，从而改变偏压输入端nbias1处的电压。 As shown in FIG. 1 , in one embodiment of the present invention, a fully differential operational amplifier module circuit includes a folded cascode fully differential operational amplifier 10 and a clock feedthrough frequency compensation circuit 20 . The input stage of the folded cascode fully differential operational amplifier 10 includes a bias circuit having a bias input terminal nbias1. The clock feedthrough frequency compensation circuit 20 includes a capacitive element. One end of the capacitive element is connected to the bias input terminal nbias1 of the folded cascode fully differential operational amplifier 10 , and the other end is connected to the clock signal CLK. The clock signal CLK is fed through the capacitive element to the bias input nbias1, thereby changing the voltage at the bias input nbias1.
本发明的一个实施例中，这里的电容性元件可以是时钟馈通MOS管MNC，该时钟馈通MOS管MNC的源极和漏极都连接到折叠式共源共栅全差分运算放大器10的偏压输入端nbias1，其栅极连接到时钟信号CLK。 In an embodiment of the present invention, the capacitive element here may be a clock feedthrough MOS transistor MNC , the source and drain of the clock feedthrough MOS transistor MNC are connected to a folded cascode fully differential operational amplifier The bias voltage input terminal nbias1 of 10, its gate is connected to the clock signal CLK.
本实施例中，时钟馈通MOS管MNC连接成电容，起馈通作用，使得时钟信号CLK通过该时钟馈通MOS管MNC馈通到折叠式共源共栅全差分运算放大器10的偏压输入端nbias1，从而改变在该偏压输入端nbias1处的电压，即在nbias1处引入微小的变化，在整体折叠式共源共栅全差分运算放大器10总电流不变化的情况下，改变输入级与增益级的电流分配比，进而微小的折叠式共源共栅全差分运算放大器10的主极点与次极点的相对位置，达到对其的频率补偿功能，实现在一定时钟频率及负载变化时得到较好的阶跃响应及稳定的建立时间（下文中详述）。 In this embodiment, the clock feedthrough MOS transistor MNC is connected as a capacitor to act as a feedthrough, so that the clock signal CLK is fed through the clock feedthrough MOS transistor MNC to the bias of the folded cascode fully differential operational amplifier 10. Press the input terminal nbias1, thereby changing the voltage at the bias input terminal nbias1, that is, introducing a small change at nbias1, and changing the input The current distribution ratio between the stage and the gain stage, and then the relative position of the main pole and the secondary pole of the tiny folded cascode fully differential operational amplifier 10, achieves its frequency compensation function, and realizes that when a certain clock frequency and load change A better step response and stable settling time are obtained (detailed below).
本发明的一个实施例中，时钟馈通MOS管MNC的衬底也可以连接到折叠式共源共栅全差分运算放大器10的偏压输入端nbias1。 In an embodiment of the present invention, the substrate of the clock feedthrough MOS transistor MNC may also be connected to the bias input terminal nbias1 of the folded cascode fully differential operational amplifier 10 .
本发明的另外的实施例中，这里的电容性元件也可以是电容器（图中未示出）。该电容器一端连接到折叠式共源共栅全差分运算放大器10的偏压输入端nbias1，另一端连接到前述的时钟信号CLK。这里，电容器的作用与前述的时钟馈通MOS管MNC的作用类似。 In another embodiment of the present invention, the capacitive element here may also be a capacitor (not shown in the figure). One end of the capacitor is connected to the bias input terminal nbias1 of the folded cascode fully differential operational amplifier 10 , and the other end is connected to the aforementioned clock signal CLK. Here, the function of the capacitor is similar to that of the aforementioned clock feedthrough MOS transistor MNC .
本发明的一个实施例中，如图1所示，折叠式共源共栅全差分运算放大器10的偏置电路包括偏置MOS管MN0，前述的折叠式共源共栅全差分运算放大器10的偏压输入端nbias1连接到该偏置MOS管MN0的栅极。 In one embodiment of the present invention, as shown in FIG. 1, the bias circuit of the folded cascode fully differential operational amplifier 10 includes a bias MOS transistor MN0, and the aforementioned folded cascode fully differential operational amplifier 10 The bias voltage input terminal nbias1 is connected to the gate of the bias MOS transistor MN0.
如图1所示，本发明的一个实施例中，折叠式共源共栅全差分运算放大器10还包括第一MOS管MN1、第二MOS管MN2、第三MOS管MP3、第四MOS管MP4、第五MOS管MN5、第六MOS管MN6、第七MOS管MN7、第八MOS管MN8、第九MOS管MP9和第十MOS管MP10。 As shown in FIG. 1, in one embodiment of the present invention, the folded cascode fully differential operational amplifier 10 further includes a first MOS transistor MN1, a second MOS transistor MN2, a third MOS transistor MP3, and a fourth MOS transistor MP4 , the fifth MOS transistor MN5, the sixth MOS transistor MN6, the seventh MOS transistor MN7, the eighth MOS transistor MN8, the ninth MOS transistor MP9 and the tenth MOS transistor MP10.
第一MOS管MN1的源极连接到第二MOS管MN2的源极并且连接到偏置MOS管MN0的漏极，第一MOS管MN1的栅极连接到折叠式共源共栅全差分运算放大器的正相输入端VIP，第一MOS管MN1的漏极连接到第四MOS管MP4的源极。 The source of the first MOS transistor MN1 is connected to the source of the second MOS transistor MN2 and connected to the drain of the bias MOS transistor MN0, and the gate of the first MOS transistor MN1 is connected to a folded cascode fully differential operational amplifier The drain of the first MOS transistor MN1 is connected to the source of the fourth MOS transistor MP4.
第二MOS管MN2的栅极连接到折叠式共源共栅全差分运算放大器的负相输入端VIN，第二MOS管MN2的漏极连接到第三MOS管MP3的源极。 The gate of the second MOS transistor MN2 is connected to the negative input terminal V IN of the folded cascode fully differential operational amplifier, and the drain of the second MOS transistor MN2 is connected to the source of the third MOS transistor MP3.
第三MOS管MP3的源极连接到第九MOS管MP9的漏极，第三MOS管MP3的栅极连接到第四MOS管MP4的栅极并连接到第一偏置信号pcas，第三MOS管MP3的漏极连接到折叠式共源共栅全差分运算放大器的正相输出端VOUTP并连接到第五MOS管MN5的漏极。 The source of the third MOS transistor MP3 is connected to the drain of the ninth MOS transistor MP9, the gate of the third MOS transistor MP3 is connected to the gate of the fourth MOS transistor MP4 and connected to the first bias signal pcas, the third MOS transistor MP3 The drain of the transistor MP3 is connected to the non-inverting output terminal V OUTP of the folded cascode fully differential operational amplifier and is connected to the drain of the fifth MOS transistor MN5.
第四MOS管MP4的源极连接到第十MOS管MP10的漏极，第四MOS管MP4的漏极连接到折叠式共源共栅全差分运算放大器的负相输出端VOUTN并连接到第六MOS管MN6的漏极。 The source of the fourth MOS transistor MP4 is connected to the drain of the tenth MOS transistor MP10, and the drain of the fourth MOS transistor MP4 is connected to the negative phase output terminal V OUTN of the folded cascode fully differential operational amplifier and connected to the first The drain of the six MOS transistors MN6.
第五MOS管MN5的栅极连接到第六MOS管MN6的栅极并且连接到第二偏置信号ncas，第五MOS管MN5的源极连接到第七MOS管MN7的漏极。 The gate of the fifth MOS transistor MN5 is connected to the gate of the sixth MOS transistor MN6 and connected to the second bias signal ncas, and the source of the fifth MOS transistor MN5 is connected to the drain of the seventh MOS transistor MN7.
第六MOS管MN6的源极连接到第八MOS管MN8的漏极。 The source of the sixth MOS transistor MN6 is connected to the drain of the eighth MOS transistor MN8.
第七MOS管MN7的栅极连接到第八MOS管MN8的栅极并且连接到第三偏置信号nbias，第七MOS管MN7的源极接地。 The gate of the seventh MOS transistor MN7 is connected to the gate of the eighth MOS transistor MN8 and connected to the third bias signal nbias, and the source of the seventh MOS transistor MN7 is grounded.
第八MOS管MN8的源极接地。 The source of the eighth MOS transistor MN8 is grounded.
第九MOS管MP9的栅极连接到第十MOS管MP10的栅极并且连接到第四偏置信号pbias,第九MOS管MP9的源极连接到系统电源VDD。 The gate of the ninth MOS transistor MP9 is connected to the gate of the tenth MOS transistor MP10 and connected to the fourth bias signal pbias, and the source of the ninth MOS transistor MP9 is connected to the system power supply V DD .
第十MOS管MP10的源极连接到系统电源VDD。 The source of the tenth MOS transistor MP10 is connected to the system power supply V DD .
本发明的一个实施例中，前述的全差分运算放大器模块电路可以应用于非制冷红外焦平面阵列的读出电路的片上集成的模数转换器中。即，本发明的一个实施例中，一种非制冷红外焦平面阵列的读出电路包括模数转换器，该模数转换器包括前述的全差分运算放大器模块电路。本实施例中，该非制冷红外焦平面阵列的读出电路和/或该模数转换器的其他结构可以是本领域内常用的结构，在此不再赘述。 In one embodiment of the present invention, the aforementioned fully differential operational amplifier module circuit can be applied to an on-chip integrated analog-to-digital converter of a readout circuit of an uncooled infrared focal plane array. That is, in one embodiment of the present invention, a readout circuit of an uncooled infrared focal plane array includes an analog-to-digital converter, and the analog-to-digital converter includes the aforementioned fully differential operational amplifier module circuit. In this embodiment, the readout circuit of the uncooled infrared focal plane array and/or other structures of the analog-to-digital converter may be commonly used structures in the art, which will not be repeated here.
下面具体说明本发明实施例中的电路的工作原理。 The working principle of the circuit in the embodiment of the present invention will be described in detail below.
将传统折叠式共源共栅（Cascode）全差分运算放大器等效成二阶系统进行分析，在传统折叠式Cascode全差分运算放大器中存在的主极点与次极点分别位于相当于图1中的C（或者D）与A（或者B）处，通过推导系统的传输函数得到主极点ωC及次极点ωA为： The traditional folded cascode fully differential operational amplifier is equivalent to a second-order system for analysis. The main pole and the secondary pole in the traditional folded cascode fully differential operational amplifier are located at C (or D) and A (or B), the main pole ω C and the secondary pole ω A are obtained by deriving the transfer function of the system as:
（2） (2)
式（1）和式（2）中g ds1-9 分别表示对应的MOS管的导纳，g m3-5 分别表示对应MOS管的跨导，C A 、C C 分别表示A点与C点的总的电容。 In formula (1) and formula (2), g ds1-9 respectively represent the admittance of the corresponding MOS tube, g m3-5 respectively represent the transconductance of the corresponding MOS tube, C A , C C represent the transconductance of point A and point C respectively total capacitance.
其次，根据MOS管的特性，g ds1-9 =λ 1-9 ·I 1-9 并且g m1-9 =（2K·I 1-9 ）1/2，其中K=μ·Cox·W/L，λ表示对应的MOS管的沟道调制系数，μ表示对应的MOS管的沟道迁移率，Cox表示对应的MOS管的单位面积栅氧化层电容，进而化简得到主极点ωC除以次极点ωA为： Secondly, according to the characteristics of MOS tubes, g ds1-9 = λ 1-9 · I 1-9 and g m1-9 = (2 K · I 1-9 ) 1/2 , where K = μ · C ox · W /L, λ represents the channel modulation coefficient of the corresponding MOS transistor, μ represents the channel mobility of the corresponding MOS transistor, C ox represents the gate oxide layer capacitance per unit area of the corresponding MOS transistor, and then simplifies to obtain the main pole ω C Divided by the subpole ω A as:
式（3）中由于pbias为固定电压，则流过MP9与MP10的电流为固定值，在折叠式Cascode全差分运算放大器的输出端负载电容远大于此处的寄生电容，所以CA为固定的值，同时，电路参数设计完成后K也是固定的值，所以在式（3）中只能通过改变I 2的值来改变主极点ωC除以次极点ωA的比值，即通过改变流过输入管（第二MOS管）MN2的电流I 2的值，实现改变主极点ωC与次极点ωA的相对位置，进而改变全差分运算放大器的频率特性，最终实现对折叠式Cascode全差分放大器的频率补偿功能。 In formula (3), since pbias is a fixed voltage, the current flowing through MP9 and MP10 is a fixed value, and the load capacitance at the output end of the folded Cascode fully differential operational amplifier is much larger than the parasitic capacitance here, so C A is fixed At the same time, K is also a fixed value after the circuit parameter design is completed, so in formula (3), only by changing the value of I 2 can the ratio of the main pole ω C divided by the secondary pole ω A be changed, that is, by changing the flow through The value of the current I 2 of the input tube (second MOS tube) MN2 can change the relative position of the main pole ω C and the secondary pole ω A , and then change the frequency characteristics of the fully differential operational amplifier, and finally realize the folding Cascode fully differential amplifier. frequency compensation function.
最后，基于上述对折叠式Cascode全差分运算放大器频率特性的深度分析及结论，本发明的实施例的电路中：当MN0的偏置电压nbias1处接入时钟信号CLK向上跳变时，通过MOS电容漏极及源极交叠电容将时钟跳变耦合到偏置nbias1处，产生一个上升的脉冲信号，NM0为一个共源放大器，流过NMO的电流增加，同时NM0的漏极电压也一定程度的下降，增加MN1、MN2的栅源电压，使流过MN1、MN2的电流I 1 和I 2 增加，由于流过MP9、MP10的总电流I 9 和I 10 固定不变，则对应的增益级电流减小及输入级电流增加，折叠式Cascode全差分运算放大器输入级与增益级电流分配比在时钟向上跳变瞬间增加，同时，根据公式（3）可得主极点ωC与次极点ωA的相对位置改变。同理，当MN0的偏置电压nbias1处接入时钟信号CLK向下跳变时，可得主极点ωC与次极点ωA的相对位置也会改变。同时，可以调节MNC的面积来调节时钟馈通的影响程度。 Finally, based on the above in-depth analysis and conclusions on the frequency characteristics of the folded Cascode fully differential operational amplifier, in the circuit of the embodiment of the present invention: when the clock signal CLK jumps upward at the bias voltage nbias1 of MN0, the MOS capacitor The drain and source overlapping capacitors couple the clock jump to the bias nbias1 to generate a rising pulse signal. NM0 is a common source amplifier. The current flowing through NMO increases, and the drain voltage of NM0 also increases to a certain extent. Decrease, increase the gate-source voltage of MN1, MN2, so that the current I 1 and I 2 flowing through MN1, MN2 increase, because the total current I 9 and I 10 flowing through MP9, MP10 are constant, the corresponding gain stage current When the input stage current decreases and the input stage current increases, the current distribution ratio between the input stage and the gain stage of the folded Cascode fully differential operational amplifier increases instantaneously when the clock jumps upwards . The location changes. Similarly, when the clock signal CLK is connected to the bias voltage nbias1 of MN0 and jumps downward, it can be obtained that the relative positions of the primary pole ω C and the secondary pole ω A will also change. At the same time, the area of the MNC can be adjusted to adjust the degree of influence of the clock feedthrough.
图2为本发明一个实施例的时钟馈通频率补偿前后阶跃瞬态响应对比的仿真图。图3为本发明一个实施例的时钟馈通频率补偿前后建立时间随负载变化对比的仿真图。可见在增加时钟馈通频率补偿电路后，折叠式Cascode全差分运算放大器的阶跃响应与不同负载下的建立时间稳定性相比与没有增加时钟馈通频率补偿结构得到了十分明显的提高。 FIG. 2 is a simulation diagram of a step transient response comparison before and after clock feedthrough frequency compensation according to an embodiment of the present invention. FIG. 3 is a simulation diagram of a comparison of settling time with load variation before and after clock feedthrough frequency compensation according to an embodiment of the present invention. It can be seen that after adding the clock feedthrough frequency compensation circuit, the step response of the folded Cascode fully differential operational amplifier and the stability of the settling time under different loads are significantly improved compared with those without the clock feedthrough frequency compensation structure.
因此，本发明的实施例中，增加了一个MOS电容及控制时钟信号CLK的时钟馈通频率补偿电路，能够得到较好的阶跃响应及稳定的建立时间，对全差分运算放大器有很好的频率补偿效果。 Therefore, in the embodiment of the present invention, a MOS capacitor and a clock feed-through frequency compensation circuit for controlling the clock signal CLK are added to obtain better step response and stable settling time, which is very good for fully differential operational amplifiers. Frequency compensation effect.
以上通过具体的实施例对本发明进行了说明，但本发明并不限于这些具体的实施例。本领域技术人员应该明白，还可以对本发明做各种修改、等同替换、变化等等，这些变换只要未背离本发明的精神，都应在本发明的保护范围之内。此外，以上多处所述的“一个实施例”表示不同的实施例，当然也可以将其全部或部分结合在一个实施例中。 The present invention has been described above through specific examples, but the present invention is not limited to these specific examples. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present invention. As long as these changes do not deviate from the spirit of the present invention, they should all be within the protection scope of the present invention. In addition, "one embodiment" described in many places above represents different embodiments, and of course all or part of them may be combined in one embodiment.
Claims (8)
1.一种全差分运算放大器模块电路，其特征在于，包括： 1. A fully differential operational amplifier module circuit, characterized in that, comprising: 折叠式共源共栅全差分运算放大器，所述折叠式共源共栅全差分运算放大器的输入级包括偏置电路，所述偏置电路具有偏压输入端（nbias1）； A folded cascode fully differential operational amplifier, the input stage of the folded cascode fully differential operational amplifier includes a bias circuit, and the bias circuit has a bias input terminal (nbias1); 时钟馈通频率补偿电路，所述时钟馈通频率补偿电路包括电容性元件，所述电容性元件一端连接到所述偏压输入端（nbias1），另一端连接到时钟信号（CLK）； A clock feedthrough frequency compensation circuit, the clock feedthrough frequency compensation circuit includes a capacitive element, one end of the capacitive element is connected to the bias voltage input terminal (nbias1), and the other end is connected to a clock signal (CLK); 其中所述时钟信号（CLK）通过所述电容性元件馈通到所述偏压输入端（nbias1），从而改变所述偏压输入端（nbias1）处的电压。 Wherein the clock signal (CLK) is fed through to the bias input terminal (nbias1 ) through the capacitive element, thereby changing the voltage at the bias voltage input terminal (nbias1 ). 2.如权利要求1所述的电路，其特征在于：所述偏置电路包括偏置MOS管（MN0），所述偏压输入端（nbias1）连接到所述偏置MOS管（MN0）的栅极。 2. The circuit according to claim 1, characterized in that: the bias circuit includes a bias MOS transistor (MN0), and the bias voltage input terminal (nbias1) is connected to the bias MOS transistor (MN0) grid. 3.如权利要求1或者2所述的电路，其特征在于：所述电容性元件为时钟馈通MOS管（MNC），所述时钟馈通MOS管（MNC）的源极和漏极连接到所述偏压输入端（nbias1），所述时钟馈通MOS管（MNC）的栅极连接到所述时钟信号（CLK）。 3. The circuit according to claim 1 or 2, characterized in that: the capacitive element is a clock feedthrough MOS transistor ( MNC ), and the source and drain of the clock feedthrough MOS transistor ( MNC ) connected to the bias input terminal (nbias1), and the gate of the clock feedthrough MOS transistor ( MNC ) is connected to the clock signal (CLK). 4.如权利要求3所述的电路，其特征在于：所述时钟馈通MOS管（MNC）的衬底连接到所述偏压输入端（nbias1）。 4. The circuit according to claim 3, characterized in that: the substrate of the clock feedthrough MOS transistor ( MNC ) is connected to the bias input terminal (nbias1). 5.如权利要求1或者2所述的电路，其特征在于：所述电容性元件为电容器，所述电容器一端连接到所述偏压输入端（nbias1），另一端连接到所述时钟信号（CLK）。 5. The circuit according to claim 1 or 2, characterized in that: the capacitive element is a capacitor, one end of the capacitor is connected to the bias voltage input (nbias1), and the other end is connected to the clock signal ( CLK). 6.如权利要求1至5中任意一项所述的电路，其特征在于：所述折叠式共源共栅全差分运算放大器还包括第一MOS管（MN1）、第二MOS管（MN2）、第三MOS管（MP3）、第四MOS管（MP4）、第五MOS管（MN5）、第六MOS管（MN6）、第七MOS管（MN7）、第八MOS管（MN8）、第九MOS管（MP9）和第十MOS管（MP10），其中： 6. The circuit according to any one of claims 1 to 5, characterized in that: the folded cascode fully differential operational amplifier further includes a first MOS transistor (MN1), a second MOS transistor (MN2) , the third MOS tube (MP3), the fourth MOS tube (MP4), the fifth MOS tube (MN5), the sixth MOS tube (MN6), the seventh MOS tube (MN7), the eighth MOS tube (MN8), the Nine MOS tubes (MP9) and tenth MOS tubes (MP10), of which: 所述第一MOS管（MN1）的源极连接到所述第二MOS管（MN2）的源极并且连接到所述偏置MOS管（MN0）的漏极，所述第一MOS管（MN1）的栅极连接到所述折叠式共源共栅全差分运算放大器的正相输入端（VIP），所述第一MOS管（MN1）的漏极连接到所述第四MOS管（MP4）的源极； The source of the first MOS transistor (MN1) is connected to the source of the second MOS transistor (MN2) and connected to the drain of the bias MOS transistor (MN0), and the first MOS transistor (MN1 ) is connected to the non-inverting input terminal (V IP ) of the folded cascode fully differential operational amplifier, and the drain of the first MOS transistor (MN1) is connected to the fourth MOS transistor (MP4 ) source; 所述第二MOS管（MN2）的栅极连接到所述折叠式共源共栅全差分运算放大器的负相输入端（VIN），所述第二MOS管（MN2）的漏极连接到所述第三MOS管（MP3）的源极； The gate of the second MOS transistor (MN2) is connected to the negative phase input terminal (V IN ) of the folded cascode fully differential operational amplifier, and the drain of the second MOS transistor (MN2) is connected to the source of the third MOS transistor (MP3); 所述第三MOS管（MP3）的源极连接到所述第九MOS管（MP9）的漏极，所述第三MOS管（MP3）的栅极连接到所述第四MOS管（MP4）的栅极并连接到第一偏置信号（pcas），所述第三MOS管（MP3）的漏极连接到所述折叠式共源共栅全差分运算放大器的正相输出端（VOUTP）并连接到所述第五MOS管（MN5）的漏极； The source of the third MOS transistor (MP3) is connected to the drain of the ninth MOS transistor (MP9), and the gate of the third MOS transistor (MP3) is connected to the fourth MOS transistor (MP4) The gate is connected to the first bias signal (pcas), the drain of the third MOS transistor (MP3) is connected to the non-inverting output terminal (V OUTP ) of the folded cascode fully differential operational amplifier and connected to the drain of the fifth MOS transistor (MN5); 所述第四MOS管（MP4）的源极连接到所述第十MOS管（MP10）的漏极，所述第四MOS管（MP4）的漏极连接到所述折叠式共源共栅全差分运算放大器的负相输出端（VOUTN）并连接到所述第六MOS管（MN6）的漏极； The source of the fourth MOS transistor (MP4) is connected to the drain of the tenth MOS transistor (MP10), and the drain of the fourth MOS transistor (MP4) is connected to the folded cascode full The negative phase output terminal (V OUTN ) of the differential operational amplifier is connected to the drain of the sixth MOS transistor (MN6); 所述第五MOS管（MN5）的栅极连接到所述第六MOS管（MN6）的栅极并且连接到第二偏置信号（ncas），所述第五MOS管（MN5）的源极连接到所述第七MOS管（MN7）的漏极； The gate of the fifth MOS transistor (MN5) is connected to the gate of the sixth MOS transistor (MN6) and connected to the second bias signal (ncas), and the source of the fifth MOS transistor (MN5) connected to the drain of the seventh MOS transistor (MN7); 所述第六MOS管（MN6）的源极连接到所述第八MOS管（MN8）的漏极； The source of the sixth MOS transistor (MN6) is connected to the drain of the eighth MOS transistor (MN8); 所述第七MOS管（MN7）的栅极连接到所述第八MOS管（MN8）的栅极并且连接到第三偏置信号（nbias），所述第七MOS管（MN7）的源极接地； The gate of the seventh MOS transistor (MN7) is connected to the gate of the eighth MOS transistor (MN8) and connected to the third bias signal (nbias), and the source of the seventh MOS transistor (MN7) grounding; 所述第八MOS管（MN8）的源极接地； The source of the eighth MOS transistor (MN8) is grounded; 所述第九MOS管（MP9）的栅极连接到所述第十MOS管（MP10）的栅极并且连接到第四偏置信号（pbias）,所述第九MOS管（MP9）的源极连接到系统电源（VDD）； The gate of the ninth MOS transistor (MP9) is connected to the gate of the tenth MOS transistor (MP10) and connected to the fourth bias signal (pbias), and the source of the ninth MOS transistor (MP9) Connect to system power supply (V DD ); 所述第十MOS管（MP10）的源极连接到系统电源（VDD）。 The source of the tenth MOS transistor (MP10) is connected to the system power supply (V DD ). 7.一种模数转换器，其特征在于：包括如权利要求1至6中任意一项所述的全差分运算放大器模块电路。 7. An analog-to-digital converter, characterized in that it comprises the fully differential operational amplifier module circuit according to any one of claims 1 to 6. 8.一种非制冷红外焦平面阵列的读出电路，其特征在于：包括如权利要求7所述的模数转换器。 8. A readout circuit for an uncooled infrared focal plane array, characterized in that it comprises the analog-to-digital converter as claimed in claim 7.
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| CN201410474878.9A CN104253590A (en) | 2014-09-18 | 2014-09-18 | Fully differential operational amplifier module circuit, analog-to-digital converter and readout circuit |
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Cited By (5)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108683167A (en) * | 2018-07-03 | 2018-10-19 | 苏州锴威特半导体有限公司 | A kind of anti-surge circuit of PD equipment |
| CN109327195A (en) * | 2018-10-26 | 2019-02-12 | 成都锐成芯微科技股份有限公司 | A low noise operational amplifier circuit |
| CN110176911A (en) * | 2019-05-29 | 2019-08-27 | 宁波市芯能微电子科技有限公司 | The high-low pressure differential amplifier circuit of BMS |
| CN112865800A (en) * | 2020-12-31 | 2021-05-28 | 瑞声科技（南京）有限公司 | Sigma-delta ADC modulator for optimizing OTA and electronic equipment |
| CN113419594A (en) * | 2021-07-02 | 2021-09-21 | 合肥睿普康集成电路有限公司 | Quiescent current control circuit capable of being used for operational amplifier |
Citations (3)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1168602A1 (en) * | 2000-06-23 | 2002-01-02 | STMicroelectronics S.r.l. | Completely differential operational amplifier of the folded cascode type |
| US20100039179A1 (en) * | 2008-08-18 | 2010-02-18 | Samsung Electronics Co., Ltd. | Folded cascode operational amplifier having improved phase margin |
| CN102394581A (en) * | 2011-09-19 | 2012-03-28 | 张兴发 | Full differential operational amplifier |
-
2014
- 2014-09-18 CN CN201410474878.9A patent/CN104253590A/en active Pending
Patent Citations (3)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1168602A1 (en) * | 2000-06-23 | 2002-01-02 | STMicroelectronics S.r.l. | Completely differential operational amplifier of the folded cascode type |
| US20100039179A1 (en) * | 2008-08-18 | 2010-02-18 | Samsung Electronics Co., Ltd. | Folded cascode operational amplifier having improved phase margin |
| CN102394581A (en) * | 2011-09-19 | 2012-03-28 | 张兴发 | Full differential operational amplifier |
Non-Patent Citations (4)
* Cited by examiner, † Cited by third party| Title |
|---|
| NING NING 等: "A Novel Clock Feedthrough Frequency Compensation for Fast-Setting of Folded-Cascode OTA", 《半导体学报》 * |
| 刘俊 等: "一种用于流水线ADC中的全差分运算放大器", 《微处理机》 * |
| 王向展 等: "实现折叠共栅共源运放MST的时钟馈通频率补偿方法", 《电子与信息学报》 * |
| 郭晓丽 等: "一种用于流水线ADC中的全差分运算放大器", 《计算机仿真》 * |
Cited By (8)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108683167A (en) * | 2018-07-03 | 2018-10-19 | 苏州锴威特半导体有限公司 | A kind of anti-surge circuit of PD equipment |
| CN108683167B (en) * | 2018-07-03 | 2024-04-09 | 苏州锴威特半导体股份有限公司 | Anti-surge circuit of PD equipment |
| CN109327195A (en) * | 2018-10-26 | 2019-02-12 | 成都锐成芯微科技股份有限公司 | A low noise operational amplifier circuit |
| CN110176911A (en) * | 2019-05-29 | 2019-08-27 | 宁波市芯能微电子科技有限公司 | The high-low pressure differential amplifier circuit of BMS |
| CN112865800A (en) * | 2020-12-31 | 2021-05-28 | 瑞声科技（南京）有限公司 | Sigma-delta ADC modulator for optimizing OTA and electronic equipment |
| CN112865800B (en) * | 2020-12-31 | 2024-04-02 | 瑞声科技（南京）有限公司 | Sigma-delta ADC modulator for optimizing OTA and electronic equipment |
| CN113419594A (en) * | 2021-07-02 | 2021-09-21 | 合肥睿普康集成电路有限公司 | Quiescent current control circuit capable of being used for operational amplifier |
| CN113419594B (en) * | 2021-07-02 | 2022-02-11 | 合肥睿普康集成电路有限公司 | Quiescent current control circuit capable of being used for operational amplifier |
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