CN104301582B - A kind of composite video signal generation method - Google Patents

The present invention relates to a kind of composite video signal generation method, belong to electronic design art.The present invention exports sync level data and blanking level data according to synchronizing signal accordingly, D/A is exported corresponding level data simultaneously, in the vision signal period, determine the starting point of vision signal period, point-by-point output video data and change over clock, vision signal is exported for D/A.Composite video signal caused by the present invention and the composite synchronizing signal of input are in synchronous regime, meet time precision requirement, and whole generation process realization is simple, and hardware design is simple, easily implements.

A kind of composite video signal generation method

Technical field

The present invention relates to a kind of composite video signal generation method, belong to electronic design art.

Background technology

At present, the common scheme for producing composite video signal is to use video encoder chip.Encoder functionality is powerful, tool There are active and follower mode, can both receive the Dot Clock of outside, own clock can also be dependent on and worked independently.But encoder It is high using difficulty, parameter configuration must be carried out with serial communication after upper electricity, add the burden of designer.Have in systems In the case of having Dot Clock, video analog signal can also be produced with D/A, then fold by high-speed analog switch and synchronizing signal Add, produce whole composite video signals.Two-part voltage magnitude is accurately controlled during design, ensures 3:7 proportionate relationship. This project plan comparison is complicated, should be used less.

The content of the invention

It is an object of the invention to provide a kind of composite video signal generation method, is produced with solving current composite video signal The problem of process is complicated and uses difficulty high.

The present invention provides a kind of composite video signal generation method to solve above-mentioned technical problem, and this method includes following Step：

1）Synchronizing signal is produced according to the composite video signal of input, and synchronizing signal is input in FPGA；

2）FPGA synchronizing signals caused by export sync level data and blanking level data accordingly, make simultaneously D/A exports corresponding level data；

3）The starting point of vision signal period is determined according to synchronizing signal, it is point-by-point to export video data and change over clock, supply D/A exports vision signal；

4）It is after the sync level data, blanking level data and video data of D/A outputs are carried out into operation amplifier processing It can obtain composite video signal.

The generation of the change over clock is the clock of two kinds of with same frequency and reversed-phase will to be obtained after external stability clock inversion, in synchronization Change over clock source of the clock that rising edge or trailing edge first reach as the row is selected after the trailing edge of signal, is then passed through Count frequency dividing and obtain the frequency of change over clock, that is, obtain change over clock.

When described synchronizing signal trailing edge arrives, FPGA output sync level data；When synchronous signal impulse rising edge During arrival, FPGA output blanking level data.

The beneficial effects of the invention are as follows:The present invention exports sync level data and blanking level according to synchronizing signal accordingly Data, while make D/A export corresponding level data, in the vision signal period, the starting point of vision signal period is determined, point by point Video data and change over clock are exported, vision signal is exported for D/A.Composite video signal caused by the present invention is answered with input Close synchronizing signal and be in synchronous regime, meet time precision requirement, and the whole process that produces realizes that simply hardware design is simple, Easily implement.

Brief description of the drawings

Fig. 1 is that composite video signal of the present invention produces functional block diagram；

Fig. 2 is composite video signal timing diagram caused by the present invention；

Fig. 3 is the sequential relationship schematic diagram of the analog voltage of synchronizing signal of the present invention and output.

Embodiment

The embodiment of the present invention is further described below in conjunction with the accompanying drawings.

Composite video signal of the present invention produces the functional module of process as shown in figure 1, including FPGA, synchronization point From unit, D/A conversion unit, operation amplifier unit and external stability clock, composite video signal is by synchronous separating unit point From the rear input for producing synchronizing signal and being input to FPGA, when FPGA changes according to external stability clock and synchronizing signal generation Clock, and the Dot Clock using the change over clock of generation as D/A conversion unit, D/A conversion unit is according to the Dot Clock generated Digital-to-analogue conversion generation analog signal is carried out to composite video signal, and after the analog signal of generation is amplified by operational amplifier Output, the analog signal of output seek to caused composite video signal, composite video signal of the present invention according to input, clock With video data to be shown, video data is converted to the composite video signal synchronous with input, as shown in Fig. 2 compound regard Frequency signal can be divided into sync level, three kinds of periods of blanking level and vision signal.The composite video signal specifically produces Process is as follows：

Synchronizing signal is produced according to the composite video signal of input, and synchronizing signal is input in FPGA, then FPGA According to synchronizing signal and external stability clock output corresponding data, as shown in Fig. 2 when synchronous signal impulse trailing edge arrives, FPGA exports sync level data（The t1 periods）, it is delayed using hardware transport and exports change over clock, D/A is exported sync level； When synchronous signal impulse rising edge arrives, FPGA output blanking level data（The t2 periods）, it is delayed and is exported using hardware transport Change over clock, D/A is set to export blanking level；In the vision signal period（The t3 periods）, FPGA determines the t3 periods according to change over clock Starting point, it is point-by-point to export video data and change over clock, export vision signal for D/A.

The data/address bus data and change over clock daclk that FPGA exports to D/A chips and synchronizing signal and the simulation of output The sequential relationship of voltage is as shown in figure 3, change over clock signal need to export after hardware is delayed, to ensure to meet D/A chips ts Length.

Determine that the generating process of the change over clock of t3 period starting points is as follows：FPGA arrives in each composite video synchronizing signal Outside fixed clock is corrected when coming, FPGA by by obtained after external stability clock inversion two kinds of with same frequency and reversed-phase when Clock, rising edge is selected after the trailing edge of line synchronising signal（Or trailing edge）During conversion of the clock first reached as the row Zhong Yuan, the frequency of clock is obtained by counting frequency dividing, that is, exports change over clock, depending on frequency is according to the resolution ratio of video data, The as change over clock of D/A chips, data/address bus are that former video data value adds 110.After change over clock is determined, in every row Initial time starts counting up, and starts D/A output video datas in row significant instant as defined in video format, until one's own profession terminates, Composite video signal often go by synchronous head, forward position, row effectively, after form along 4 parts, the rule of each part having time length It is fixed.

The programming and the programming of t2 periods of t1 periods is provided separately below.

T1 period programmings are as follows：

T2 period programmings are as follows：

The present invention changes video data according to input composite video signal, external clock and video data to be shown For the composite video signal synchronous with input.The composite video signal of output is divided into sync level, blanking level and video Three kinds of periods of signal, FPGA export the signal of corresponding period according to synchronizing signal and change over clock.It is compound caused by the present invention Vision signal and the composite synchronizing signal of input are in synchronous regime, meet time precision requirement, and the whole process that produces is realized Simply, hardware design is simple, easily implements.